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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-03 22:11:29 +03:00
[xburst] Add support for enabling/disabling the aic controllers clock.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20043 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
ece5bacf60
commit
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@ -55,8 +55,8 @@
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#define JZ_CLOCK_GATE_RTC BIT(2)
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#define JZ_CLOCK_GATE_RTC BIT(2)
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#define JZ_CLOCK_GATE_I2C BIT(3)
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#define JZ_CLOCK_GATE_I2C BIT(3)
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#define JZ_CLOCK_GATE_SPI BIT(4)
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#define JZ_CLOCK_GATE_SPI BIT(4)
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#define JZ_CLOCK_GATE_AIC_PCLK BIT(5)
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#define JZ_CLOCK_GATE_AIC BIT(5)
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#define JZ_CLOCK_GATE_AIC BIT(6)
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#define JZ_CLOCK_GATE_I2S BIT(6)
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#define JZ_CLOCK_GATE_MMC BIT(7)
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#define JZ_CLOCK_GATE_MMC BIT(7)
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#define JZ_CLOCK_GATE_ADC BIT(8)
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#define JZ_CLOCK_GATE_ADC BIT(8)
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#define JZ_CLOCK_GATE_CIM BIT(9)
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#define JZ_CLOCK_GATE_CIM BIT(9)
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@ -626,7 +626,7 @@ static struct divided_clk jz4740_clock_divided_clks[] = {
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.clk = {
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.clk = {
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.name = "i2s",
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.name = "i2s",
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.parent = &jz_clk_ext.clk,
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.parent = &jz_clk_ext.clk,
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.gate_bit = JZ_CLOCK_GATE_AIC,
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.gate_bit = JZ_CLOCK_GATE_I2S,
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.ops = &jz_clk_i2s_ops,
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.ops = &jz_clk_i2s_ops,
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},
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},
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.reg = JZ_REG_CLOCK_I2S,
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.reg = JZ_REG_CLOCK_I2S,
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@ -721,6 +721,12 @@ static struct clk jz4740_clock_simple_clks[] = {
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.gate_bit = JZ_CLOCK_GATE_I2C,
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.gate_bit = JZ_CLOCK_GATE_I2C,
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.ops = &jz_clk_simple_ops,
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.ops = &jz_clk_simple_ops,
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},
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},
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{
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.name = "aic",
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.parent = &jz_clk_ext.clk,
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.gate_bit = JZ_CLOCK_GATE_AIC,
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.ops = &jz_clk_simple_ops,
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},
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};
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};
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static struct static_clk jz_clk_rtc = {
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static struct static_clk jz_clk_rtc = {
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@ -84,7 +84,8 @@ struct jz4740_i2s {
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void __iomem *base;
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void __iomem *base;
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dma_addr_t phys_base;
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dma_addr_t phys_base;
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struct clk *clk;
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struct clk *clk_aic;
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struct clk *clk_i2s;
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struct jz4740_pcm_config pcm_config;
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struct jz4740_pcm_config pcm_config;
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};
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};
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@ -141,7 +142,7 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
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clk_enable(i2s->clk);
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clk_enable(i2s->clk_i2s);
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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return 0;
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return 0;
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@ -153,14 +154,14 @@ static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct
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struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
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struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
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uint32_t conf;
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uint32_t conf;
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if (dai->active)
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if (!dai->active)
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return;
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return;
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf &= ~JZ_AIC_CONF_ENABLE;
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conf &= ~JZ_AIC_CONF_ENABLE;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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clk_disable(i2s->clk);
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clk_disable(i2s->clk_i2s);
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}
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}
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@ -198,7 +199,7 @@ static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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return -EINVAL;
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return -EINVAL;
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}
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}
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL,ctrl);
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jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
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return 0;
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return 0;
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}
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}
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@ -348,12 +349,12 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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switch (clk_id) {
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switch (clk_id) {
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case JZ4740_I2S_CLKSRC_EXT:
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case JZ4740_I2S_CLKSRC_EXT:
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parent = clk_get(NULL, "ext");
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parent = clk_get(NULL, "ext");
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clk_set_parent(i2s->clk, parent);
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clk_set_parent(i2s->clk_i2s, parent);
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break;
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break;
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case JZ4740_I2S_CLKSRC_PLL:
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case JZ4740_I2S_CLKSRC_PLL:
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parent = clk_get(NULL, "pll half");
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parent = clk_get(NULL, "pll half");
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clk_set_parent(i2s->clk, parent);
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clk_set_parent(i2s->clk_i2s, parent);
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ret = clk_set_rate(i2s->clk, freq);
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ret = clk_set_rate(i2s->clk_i2s, freq);
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break;
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break;
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default:
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default:
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return -EINVAL;
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return -EINVAL;
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@ -368,14 +369,16 @@ static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
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struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
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struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
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uint32_t conf;
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uint32_t conf;
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if (!dai->active)
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if (dai->active) {
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return 0;
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf &= ~JZ_AIC_CONF_ENABLE;
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conf &= ~JZ_AIC_CONF_ENABLE;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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clk_disable(i2s->clk);
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clk_disable(i2s->clk_i2s);
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}
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clk_disable(i2s->clk_aic);
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return 0;
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return 0;
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}
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}
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@ -384,15 +387,17 @@ static int jz4740_i2s_resume(struct snd_soc_dai *dai)
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struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
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struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
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uint32_t conf;
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uint32_t conf;
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if (!dai->active)
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clk_enable(i2s->clk_aic);
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return 0;
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clk_enable(i2s->clk);
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if (dai->active) {
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clk_enable(i2s->clk_i2s);
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
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conf |= JZ_AIC_CONF_ENABLE;
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conf |= JZ_AIC_CONF_ENABLE;
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
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}
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return 0;
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return 0;
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}
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}
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@ -487,13 +492,23 @@ static int __devinit jz4740_i2s_dev_probe(struct platform_device *pdev)
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ret = snd_soc_register_dai(&jz4740_i2s_dai);
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ret = snd_soc_register_dai(&jz4740_i2s_dai);
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i2s->clk = clk_get(&pdev->dev, "i2s");
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i2s->clk_aic = clk_get(&pdev->dev, "aic");
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if (IS_ERR(i2s->clk)) {
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if (IS_ERR(i2s->clk_aic)) {
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ret = PTR_ERR(i2s->clk);
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ret = PTR_ERR(i2s->clk_aic);
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goto err_iounmap;
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goto err_iounmap;
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}
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}
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i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
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if (IS_ERR(i2s->clk_i2s)) {
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ret = PTR_ERR(i2s->clk_i2s);
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goto err_iounmap;
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}
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clk_enable(i2s->clk_aic);
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platform_set_drvdata(pdev, i2s);
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platform_set_drvdata(pdev, i2s);
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return 0;
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return 0;
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@ -514,7 +529,9 @@ static int __devexit jz4740_i2s_dev_remove(struct platform_device *pdev)
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snd_soc_unregister_dai(&jz4740_i2s_dai);
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snd_soc_unregister_dai(&jz4740_i2s_dai);
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clk_put(i2s->clk);
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clk_disable(i2s->clk_aic);
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clk_put(i2s->clk_i2s);
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clk_put(i2s->clk_aic);
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iounmap(i2s->base);
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iounmap(i2s->base);
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release_mem_region(i2s->mem->start, resource_size(i2s->mem));
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release_mem_region(i2s->mem->start, resource_size(i2s->mem));
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