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ramips: add preliminary support for the RT3662/RT3883 SoCs
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30495 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
@@ -0,0 +1,23 @@
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/*
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* Platform data definition for the built-in NAND controller of the
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* Ralink RT305X/RT3662/RT3883 SoCs
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RAMIPS_NAND_PLATFORM_H
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#define _RAMIPS_NAND_PLATFORM_H
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#define RAMIPS_NAND_DRIVER_NAME "ramips-nand"
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struct ramips_nand_platform_data {
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const char *name;
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struct mtd_partition *parts;
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int nr_parts;
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};
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#endif /* _RAMIPS_NAND_PLATFORM_H */
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@@ -0,0 +1,133 @@
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/*
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* Ralink RT3662/RT3883 SoC specific definitions
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT3883_H_
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#define _RT3883_H_
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#include <linux/init.h>
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#include <linux/io.h>
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void rt3883_detect_sys_type(void);
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#define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024)
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#define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024)
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#define RT3883_CPU_IRQ_BASE 0
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#define RT3883_CPU_IRQ_COUNT 8
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#define RT3883_INTC_IRQ_BASE (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT)
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#define RT3883_INTC_IRQ_COUNT 32
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#define RT3883_GPIO_IRQ_BASE (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT)
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#define RT3883_CPU_IRQ_INTC (RT3883_CPU_IRQ_BASE + 2)
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#define RT3883_CPU_IRQ_PCI (RT3883_CPU_IRQ_BASE + 4)
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#define RT3883_CPU_IRQ_FE (RT3883_CPU_IRQ_BASE + 5)
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#define RT3883_CPU_IRQ_WLAN (RT3883_CPU_IRQ_BASE + 6)
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#define RT3883_CPU_IRQ_COUNTER (RT3883_CPU_IRQ_BASE + 7)
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#define RT3883_INTC_IRQ_SYSCTL (RT3883_INTC_IRQ_BASE + 0)
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#define RT3883_INTC_IRQ_TIMER0 (RT3883_INTC_IRQ_BASE + 1)
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#define RT3883_INTC_IRQ_TIMER1 (RT3883_INTC_IRQ_BASE + 2)
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#define RT3883_INTC_IRQ_IA (RT3883_INTC_IRQ_BASE + 3)
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#define RT3883_INTC_IRQ_PCM (RT3883_INTC_IRQ_BASE + 4)
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#define RT3883_INTC_IRQ_UART0 (RT3883_INTC_IRQ_BASE + 5)
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#define RT3883_INTC_IRQ_PIO (RT3883_INTC_IRQ_BASE + 6)
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#define RT3883_INTC_IRQ_DMA (RT3883_INTC_IRQ_BASE + 7)
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#define RT3883_INTC_IRQ_NAND (RT3883_INTC_IRQ_BASE + 8)
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#define RT3883_INTC_IRQ_PERFC (RT3883_INTC_IRQ_BASE + 9)
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#define RT3883_INTC_IRQ_I2S (RT3883_INTC_IRQ_BASE + 10)
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#define RT3883_INTC_IRQ_UART1 (RT3883_INTC_IRQ_BASE + 12)
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#define RT3883_INTC_IRQ_UHST (RT3883_INTC_IRQ_BASE + 18)
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#define RT3883_INTC_IRQ_UDEV (RT3883_INTC_IRQ_BASE + 19)
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extern void __iomem *rt3883_sysc_base;
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extern void __iomem *rt3883_memc_base;
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static inline void rt3883_sysc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt3883_sysc_base + reg);
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}
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static inline u32 rt3883_sysc_rr(unsigned reg)
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{
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return __raw_readl(rt3883_sysc_base + reg);
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}
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static inline void rt3883_memc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt3883_memc_base + reg);
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}
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static inline u32 rt3883_memc_rr(unsigned reg)
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{
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return __raw_readl(rt3883_memc_base + reg);
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}
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#define RT3883_GPIO_I2C_SD 1
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#define RT3883_GPIO_I2C_SCLK 2
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#define RT3883_GPIO_SPI_CS0 3
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#define RT3883_GPIO_SPI_CLK 4
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#define RT3883_GPIO_SPI_MOSI 5
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#define RT3883_GPIO_SPI_MISO 6
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/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
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#define RT3883_GPIO_7 7
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#define RT3883_GPIO_8 8
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#define RT3883_GPIO_9 9
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#define RT3883_GPIO_10 10
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#define RT3883_GPIO_11 11
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#define RT3883_GPIO_12 12
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#define RT3883_GPIO_13 13
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#define RT3883_GPIO_14 14
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#define RT3883_GPIO_UART1_TXD 15
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#define RT3883_GPIO_UART1_RXD 16
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#define RT3883_GPIO_JTAG_TDO 17
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#define RT3883_GPIO_JTAG_TDI 18
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#define RT3883_GPIO_JTAG_TMS 19
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#define RT3883_GPIO_JTAG_TCLK 20
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#define RT3883_GPIO_JTAG_TRST_N 21
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#define RT3883_GPIO_MDIO_MDC 22
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#define RT3883_GPIO_MDIO_MDIO 23
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#define RT3883_GPIO_LNA_PE_A0 32
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#define RT3883_GPIO_LNA_PE_A1 33
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#define RT3883_GPIO_LNA_PE_A2 34
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#define RT3883_GPIO_LNA_PE_G0 35
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#define RT3883_GPIO_LNA_PE_G1 36
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#define RT3883_GPIO_LNA_PE_G2 37
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#define RT3883_GPIO_PCI_AD0 40
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#define RT3883_GPIO_PCI_AD31 71
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#define RT3883_GPIO_GE2_TXD0 72
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#define RT3883_GPIO_GE2_TXD1 73
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#define RT3883_GPIO_GE2_TXD2 74
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#define RT3883_GPIO_GE2_TXD3 75
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#define RT3883_GPIO_GE2_TXEN 76
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#define RT3883_GPIO_GE2_TXCLK 77
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#define RT3883_GPIO_GE2_RXD0 78
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#define RT3883_GPIO_GE2_RXD1 79
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#define RT3883_GPIO_GE2_RXD2 80
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#define RT3883_GPIO_GE2_RXD3 81
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#define RT3883_GPIO_GE2_RXDV 82
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#define RT3883_GPIO_GE2_RXCLK 83
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#define RT3883_GPIO_GE1_TXD0 84
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#define RT3883_GPIO_GE1_TXD1 85
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#define RT3883_GPIO_GE1_TXD2 86
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#define RT3883_GPIO_GE1_TXD3 87
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#define RT3883_GPIO_GE1_TXEN 88
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#define RT3883_GPIO_GE1_TXCLK 89
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#define RT3883_GPIO_GE1_RXD0 90
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#define RT3883_GPIO_GE1_RXD1 91
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#define RT3883_GPIO_GE1_RXD2 92
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#define RT3883_GPIO_GE1_RXD3 93
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#define RT3883_GPIO_GE1_RXDV 94
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#define RT3883_GPIO_GE1_RXCLK 95
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void rt3883_gpio_init(u32 mode);
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#endif /* _RT3883_H_ */
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@@ -0,0 +1,55 @@
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/*
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* Ralink RT3662/RT3883 specific CPU feature overrides
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This file was derived from: include/asm-mips/cpu-features.h
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_sb1_cache 0
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#define cpu_has_fpu 0
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#define cpu_has_32fpr 0
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#define cpu_has_counter 1
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#define cpu_has_watch 1
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#define cpu_has_divec 1
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#define cpu_has_prefetch 1
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#define cpu_has_ejtag 1
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#define cpu_has_llsc 1
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#define cpu_has_mips16 1
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_smartmips 0
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#define cpu_has_mips32r1 1
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#define cpu_has_mips32r2 1
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#define cpu_has_dsp 0
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#define cpu_has_mipsmt 0
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#define cpu_has_64bits 0
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#define cpu_has_64bit_zero_reg 0
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#define cpu_has_64bit_gp_regs 0
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#define cpu_has_64bit_addresses 0
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 32
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#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */
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@@ -0,0 +1,18 @@
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/*
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* Ralink RT3662/RT3883 specific SOC defines
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT3883_RALINK_SOC_H
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#define _RT3883_RALINK_SOC_H
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#define RALINK_SOC_SDRAM_BASE 0
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#define RALINK_SOC_MEM_SIZE_MIN (2 * 1024 * 1024)
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#define RALINK_SOC_MEM_SIZE_MAX (256 * 1024 * 1024)
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#endif /* _RT3883_RALINK_SOC_H */
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@@ -0,0 +1,20 @@
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/*
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* Platform data definition for built-in EHCI controller of the
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* Ralink RT3662/RT3883 SoCs
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT3883_EHCI_PLATFORM_H
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#define _RT3883_EHCI_PLATFORM_H
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struct rt3883_ehci_platform_data {
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void (*start_hw)(void);
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void (*stop_hw)(void);
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};
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#endif /* _RT3883_EHCI_PLATFORM_H */
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@@ -0,0 +1,20 @@
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/*
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* Platform data definition for built-in OHCI controller of the
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* Ralink RT3662/RT3883 SoCs
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT3883_OHCI_PLATFORM_H
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#define _RT3883_OHCI_PLATFORM_H
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struct rt3883_ohci_platform_data {
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void (*start_hw)(void);
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void (*stop_hw)(void);
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};
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#endif /* _RT3883_OHCI_PLATFORM_H */
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@@ -0,0 +1,199 @@
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/*
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* Ralink RT3662/RT3883 SoC register definitions
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT3883_REGS_H_
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#define _RT3883_REGS_H_
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#include <linux/bitops.h>
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#define RT3883_SDRAM_BASE 0x00000000
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#define RT3883_SYSC_BASE 0x10000000
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#define RT3883_TIMER_BASE 0x10000100
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#define RT3883_INTC_BASE 0x10000200
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#define RT3883_MEMC_BASE 0x10000300
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#define RT3883_UART0_BASE 0x10000500
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#define RT3883_PIO_BASE 0x10000600
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#define RT3883_FSCC_BASE 0x10000700
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#define RT3883_NANDC_BASE 0x10000810
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#define RT3883_I2C_BASE 0x10000900
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#define RT3883_I2S_BASE 0x10000a00
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#define RT3883_SPI_BASE 0x10000b00
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#define RT3883_UART1_BASE 0x10000c00
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#define RT3883_PCM_BASE 0x10002000
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#define RT3883_GDMA_BASE 0x10002800
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#define RT3883_CODEC1_BASE 0x10003000
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#define RT3883_CODEC2_BASE 0x10003800
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#define RT3883_FE_BASE 0x10100000
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#define RT3883_ROM_BASE 0x10118000
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#define RT3883_USBDEV_BASE 0x10112000
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#define RT3883_PCI_BASE 0x10140000
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#define RT3883_WLAN_BASE 0x10180000
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#define RT3883_USBHOST_BASE 0x101c0000
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#define RT3883_BOOT_BASE 0x1c000000
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#define RT3883_SRAM_BASE 0x1e000000
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#define RT3883_PCIMEM_BASE 0x20000000
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#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
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#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
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#define RT3883_SYSC_SIZE 0x100
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#define RT3883_TIMER_SIZE 0x100
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#define RT3883_INTC_SIZE 0x100
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#define RT3883_MEMC_SIZE 0x100
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#define RT3883_UART0_SIZE 0x100
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#define RT3883_UART1_SIZE 0x100
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#define RT3883_PIO_SIZE 0x100
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#define RT3883_FSCC_SIZE 0x100
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#define RT3883_NANDC_SIZE 0x0f0
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#define RT3883_I2C_SIZE 0x100
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#define RT3883_I2S_SIZE 0x100
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#define RT3883_SPI_SIZE 0x100
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#define RT3883_PCM_SIZE 0x800
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#define RT3883_GDMA_SIZE 0x800
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#define RT3883_CODEC1_SIZE 0x800
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#define RT3883_CODEC2_SIZE 0x800
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#define RT3883_FE_SIZE 0x10000
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#define RT3883_ROM_SIZE 0x4000
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#define RT3883_USBDEV_SIZE 0x4000
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#define RT3883_PCI_SIZE 0x40000
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#define RT3883_WLAN_SIZE 0x40000
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#define RT3883_USBHOST_SIZE 0x40000
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#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
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#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
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/* SYSC registers */
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#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
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#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
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#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
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#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
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#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
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#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
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#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
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#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
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#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
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#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
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#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
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#define RT3883_SYSC_REG_PMU 0x88
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#define RT3883_SYSC_REG_PMU1 0x8c
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#define RT3883_REVID_VER_ID_MASK 0x0f
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#define RT3883_REVID_VER_ID_SHIFT 8
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#define RT3883_REVID_ECO_ID_MASK 0x0f
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#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
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#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
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#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
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#define RT3883_SYSCFG0_CPUCLK_250 0x0
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#define RT3883_SYSCFG0_CPUCLK_384 0x1
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#define RT3883_SYSCFG0_CPUCLK_480 0x2
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#define RT3883_SYSCFG0_CPUCLK_500 0x3
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#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
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#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
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#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
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#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
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#define RT3883_GPIO_MODE_I2C BIT(0)
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#define RT3883_GPIO_MODE_SPI BIT(1)
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#define RT3883_GPIO_MODE_UART0_SHIFT 2
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||||
#define RT3883_GPIO_MODE_UART0_MASK 0x7
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||||
#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
|
||||
#define RT3883_GPIO_MODE_UARTF 0x0
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#define RT3883_GPIO_MODE_PCM_UARTF 0x1
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#define RT3883_GPIO_MODE_PCM_I2S 0x2
|
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#define RT3883_GPIO_MODE_I2S_UARTF 0x3
|
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#define RT3883_GPIO_MODE_PCM_GPIO 0x4
|
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#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
|
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#define RT3883_GPIO_MODE_GPIO_I2S 0x6
|
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#define RT3883_GPIO_MODE_GPIO 0x7
|
||||
#define RT3883_GPIO_MODE_UART1 BIT(5)
|
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#define RT3883_GPIO_MODE_JTAG BIT(6)
|
||||
#define RT3883_GPIO_MODE_MDIO BIT(7)
|
||||
#define RT3883_GPIO_MODE_GE1 BIT(9)
|
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#define RT3883_GPIO_MODE_GE2 BIT(10)
|
||||
#define RT3883_GPIO_MODE_PCI_SHIFT 11
|
||||
#define RT3883_GPIO_MODE_PCI_MASK 0x7
|
||||
#define RT3883_GPIO_MODE_PCI(_x) ((_x) << RT3883_GPIO_MODE_PCI_SHIFT)
|
||||
#define RT3883_GPIO_MODE_PCI_DEV 0
|
||||
#define RT3883_GPIO_MODE_PCI_HOST2 1
|
||||
#define RT3883_GPIO_MODE_PCI_HOST1 2
|
||||
#define RT3883_GPIO_MODE_PCI_FNC 3
|
||||
#define RT3883_GPIO_MODE_PCI_GPIO 7
|
||||
#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
|
||||
#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
|
||||
#define RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
|
||||
#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
|
||||
#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
|
||||
#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
|
||||
#define RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
|
||||
#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
|
||||
|
||||
#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
|
||||
#define RT3883_RSTCTRL_FLASH BIT(26)
|
||||
#define RT3883_RSTCTRL_UDEV BIT(25)
|
||||
#define RT3883_RSTCTRL_PCI BIT(24)
|
||||
#define RT3883_RSTCTRL_PCIE BIT(23)
|
||||
#define RT3883_RSTCTRL_UHST BIT(22)
|
||||
#define RT3883_RSTCTRL_FE BIT(21)
|
||||
#define RT3883_RSTCTRL_WLAN BIT(20)
|
||||
#define RT3883_RSTCTRL_UART1 BIT(29)
|
||||
#define RT3883_RSTCTRL_SPI BIT(18)
|
||||
#define RT3883_RSTCTRL_I2S BIT(17)
|
||||
#define RT3883_RSTCTRL_I2C BIT(16)
|
||||
#define RT3883_RSTCTRL_NAND BIT(15)
|
||||
#define RT3883_RSTCTRL_DMA BIT(14)
|
||||
#define RT3883_RSTCTRL_PIO BIT(13)
|
||||
#define RT3883_RSTCTRL_UART BIT(12)
|
||||
#define RT3883_RSTCTRL_PCM BIT(11)
|
||||
#define RT3883_RSTCTRL_MC BIT(10)
|
||||
#define RT3883_RSTCTRL_INTC BIT(9)
|
||||
#define RT3883_RSTCTRL_TIMER BIT(8)
|
||||
#define RT3883_RSTCTRL_SYS BIT(0)
|
||||
|
||||
#define RT3883_INTC_INT_SYSCTL BIT(0)
|
||||
#define RT3883_INTC_INT_TIMER0 BIT(1)
|
||||
#define RT3883_INTC_INT_TIMER1 BIT(2)
|
||||
#define RT3883_INTC_INT_IA BIT(3)
|
||||
#define RT3883_INTC_INT_PCM BIT(4)
|
||||
#define RT3883_INTC_INT_UART0 BIT(5)
|
||||
#define RT3883_INTC_INT_PIO BIT(6)
|
||||
#define RT3883_INTC_INT_DMA BIT(7)
|
||||
#define RT3883_INTC_INT_NAND BIT(8)
|
||||
#define RT3883_INTC_INT_PERFC BIT(9)
|
||||
#define RT3883_INTC_INT_I2S BIT(10)
|
||||
#define RT3883_INTC_INT_UART1 BIT(12)
|
||||
#define RT3883_INTC_INT_UHST BIT(18)
|
||||
#define RT3883_INTC_INT_UDEV BIT(19)
|
||||
|
||||
/* FLASH/SRAM/Codec Controller registers */
|
||||
#define RT3883_FSCC_REG_FLASH_CFG0 0x00
|
||||
#define RT3883_FSCC_REG_FLASH_CFG1 0x04
|
||||
#define RT3883_FSCC_REG_CODEC_CFG0 0x40
|
||||
#define RT3883_FSCC_REG_CODEC_CFG1 0x44
|
||||
|
||||
#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
|
||||
#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
|
||||
#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
|
||||
#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
|
||||
#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
|
||||
|
||||
|
||||
/* UART registers */
|
||||
#define RT3883_UART_REG_RX 0
|
||||
#define RT3883_UART_REG_TX 1
|
||||
#define RT3883_UART_REG_IER 2
|
||||
#define RT3883_UART_REG_IIR 3
|
||||
#define RT3883_UART_REG_FCR 4
|
||||
#define RT3883_UART_REG_LCR 5
|
||||
#define RT3883_UART_REG_MCR 6
|
||||
#define RT3883_UART_REG_LSR 7
|
||||
|
||||
#endif /* _RT3883_REGS_H_ */
|
||||
Reference in New Issue
Block a user