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[lantiq] move files/ -> files-3.3/

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34060 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2012-11-02 20:07:02 +00:00
parent 961508b717
commit 1048c7b452
135 changed files with 0 additions and 0 deletions
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37
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/Kconfig Normal file
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config DWC_OTG
tristate "Synopsis DWC_OTG support"
depends on USB
help
This driver supports Synopsis DWC_OTG IP core
embebbed on many SOCs (ralink, infineon, etc)
choice
prompt "USB Operation Mode"
depends on DWC_OTG
default DWC_OTG_HOST_ONLY
config DWC_OTG_HOST_ONLY
bool "HOST ONLY MODE"
depends on DWC_OTG
#config DWC_OTG_DEVICE_ONLY
# bool "DEVICE ONLY MODE"
# depends on DWC_OTG
endchoice
choice
prompt "Platform"
depends on DWC_OTG
default DWC_OTG_LANTIQ
config DWC_OTG_LANTIQ
bool "Lantiq"
depends on LANTIQ
help
Danube USB Host Controller
platform support
endchoice
config DWC_OTG_DEBUG
bool "Enable debug mode"
depends on DWC_OTG

39
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/Makefile Normal file
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#
# Makefile for DWC_otg Highspeed USB controller driver
#
ifeq ($(CONFIG_DWC_OTG_DEBUG),y)
EXTRA_CFLAGS += -DDEBUG
endif
# Use one of the following flags to compile the software in host-only or
# device-only mode based on the configuration selected by the user
ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
EXTRA_CFLAGS += -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY
EXTRA_CFLAGS += -DDWC_OTG_EN_ISOC -DDWC_EN_ISOC
else ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y)
EXTRA_CFLAGS += -DDWC_OTG_DEVICE_ONLY
else
EXTRA_CFLAGS += -DDWC_OTG_MODE
endif
# EXTRA_CFLAGS += -DDWC_HS_ELECT_TST
# EXTRA_CFLAGS += -DDWC_OTG_EXT_CHG_PUMP
ifeq ($(CONFIG_DWC_OTG_LANTIQ),y)
EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -D__KERNEL__
endif
ifeq ($(CONFIG_DWC_OTG_LANTIQ),m)
EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_HOST_ONLY -DMODULE -D__KERNEL__ -DDEBUG
endif
obj-$(CONFIG_DWC_OTG) := dwc_otg.o
dwc_otg-objs := dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
#dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
dwc_otg-objs += dwc_otg_attr.o
dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
dwc_otg-objs += dwc_otg_ifx.o
dwc_otg-objs += dwc_otg_driver.o
#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o
#dwc_otg_ifx-objs := dwc_otg_ifx.o

802
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_attr.c Normal file
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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
/** @file
*
* The diagnostic interface will provide access to the controller for
* bringing up the hardware and testing. The Linux driver attributes
* feature will be used to provide the Linux Diagnostic
* Interface. These attributes are accessed through sysfs.
*/
/** @page "Linux Module Attributes"
*
* The Linux module attributes feature is used to provide the Linux
* Diagnostic Interface. These attributes are accessed through sysfs.
* The diagnostic interface will provide access to the controller for
* bringing up the hardware and testing.
The following table shows the attributes.
<table>
<tr>
<td><b> Name</b></td>
<td><b> Description</b></td>
<td><b> Access</b></td>
</tr>
<tr>
<td> mode </td>
<td> Returns the current mode: 0 for device mode, 1 for host mode</td>
<td> Read</td>
</tr>
<tr>
<td> hnpcapable </td>
<td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
Read returns the current value.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> srpcapable </td>
<td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
Read returns the current value.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> hnp </td>
<td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> srp </td>
<td> Initiates the Session Request Protocol. Read returns the status.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> buspower </td>
<td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
<td> Read/Write</td>
</tr>
<tr>
<td> bussuspend </td>
<td> Suspends the USB bus.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> busconnected </td>
<td> Gets the connection status of the bus</td>
<td> Read</td>
</tr>
<tr>
<td> gotgctl </td>
<td> Gets or sets the Core Control Status Register.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gusbcfg </td>
<td> Gets or sets the Core USB Configuration Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> grxfsiz </td>
<td> Gets or sets the Receive FIFO Size Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gnptxfsiz </td>
<td> Gets or sets the non-periodic Transmit Size Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gpvndctl </td>
<td> Gets or sets the PHY Vendor Control Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> ggpio </td>
<td> Gets the value in the lower 16-bits of the General Purpose IO Register
or sets the upper 16 bits.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> guid </td>
<td> Gets or sets the value of the User ID Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gsnpsid </td>
<td> Gets the value of the Synopsys ID Regester</td>
<td> Read</td>
</tr>
<tr>
<td> devspeed </td>
<td> Gets or sets the device speed setting in the DCFG register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> enumspeed </td>
<td> Gets the device enumeration Speed.</td>
<td> Read</td>
</tr>
<tr>
<td> hptxfsiz </td>
<td> Gets the value of the Host Periodic Transmit FIFO</td>
<td> Read</td>
</tr>
<tr>
<td> hprt0 </td>
<td> Gets or sets the value in the Host Port Control and Status Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regoffset </td>
<td> Sets the register offset for the next Register Access</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regvalue </td>
<td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> remote_wakeup </td>
<td> On read, shows the status of Remote Wakeup. On write, initiates a remote
wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
Wakeup signalling bit in the Device Control Register is set for 1
milli-second.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regdump </td>
<td> Dumps the contents of core registers.</td>
<td> Read</td>
</tr>
<tr>
<td> hcddump </td>
<td> Dumps the current HCD state.</td>
<td> Read</td>
</tr>
<tr>
<td> hcd_frrem </td>
<td> Shows the average value of the Frame Remaining
field in the Host Frame Number/Frame Remaining register when an SOF interrupt
occurs. This can be used to determine the average interrupt latency. Also
shows the average Frame Remaining value for start_transfer and the "a" and
"b" sample points. The "a" and "b" sample points may be used during debugging
bto determine how long it takes to execute a section of the HCD code.</td>
<td> Read</td>
</tr>
<tr>
<td> rd_reg_test </td>
<td> Displays the time required to read the GNPTXFSIZ register many times
(the output shows the number of times the register is read).
<td> Read</td>
</tr>
<tr>
<td> wr_reg_test </td>
<td> Displays the time required to write the GNPTXFSIZ register many times
(the output shows the number of times the register is written).
<td> Read</td>
</tr>
</table>
Example usage:
To get the current mode:
cat /sys/devices/lm0/mode
To power down the USB:
echo 0 > /sys/devices/lm0/buspower
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/stat.h> /* permission constants */
#include <asm/io.h>
#include "dwc_otg_plat.h"
#include "dwc_otg_attr.h"
#include "dwc_otg_driver.h"
// #include "dwc_otg_pcd.h"
#include "dwc_otg_hcd.h"
// 20070316, winder added.
#ifndef SZ_256K
#define SZ_256K 0x00040000
#endif
/*
* MACROs for defining sysfs attribute
*/
#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val; \
val = dwc_read_reg32 (_addr_); \
val = (val & (_mask_)) >> _shift_; \
return sprintf (buf, "%s = 0x%x\n", _string_, val); \
}
#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t set = simple_strtoul(buf, NULL, 16); \
uint32_t clear = set; \
clear = ((~clear) << _shift_) & _mask_; \
set = (set << _shift_) & _mask_; \
dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
dwc_modify_reg32(_addr_, clear, set); \
return count; \
}
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
/*
* MACROs for defining sysfs attribute for 32-bit registers
*/
#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val; \
val = dwc_read_reg32 (_addr_); \
return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
}
#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val = simple_strtoul(buf, NULL, 16); \
dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
dwc_write_reg32(_addr_, val); \
return count; \
}
#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
/** @name Functions for Show/Store of Attributes */
/**@{*/
/**
* Show the register offset of the Register Access.
*/
static ssize_t regoffset_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
}
/**
* Set the register offset for the next Register Access Read/Write
*/
static ssize_t regoffset_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t offset = simple_strtoul(buf, NULL, 16);
//dev_dbg(_dev, "Offset=0x%08x\n", offset);
if (offset < SZ_256K ) {
otg_dev->reg_offset = offset;
}
else {
dev_err( _dev, "invalid offset\n" );
}
return count;
}
DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, regoffset_show, regoffset_store);
/**
* Show the value of the register at the offset in the reg_offset
* attribute.
*/
static ssize_t regvalue_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t val;
volatile uint32_t *addr;
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t*)(otg_dev->reg_offset +
(uint8_t*)otg_dev->base);
//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
val = dwc_read_reg32( addr );
return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
"Reg@0x%06x = 0x%08x\n",
otg_dev->reg_offset, val);
}
else {
dev_err(_dev, "Invalid offset (0x%0x)\n",
otg_dev->reg_offset);
return sprintf(buf, "invalid offset\n" );
}
}
/**
* Store the value in the register at the offset in the reg_offset
* attribute.
*
*/
static ssize_t regvalue_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
volatile uint32_t * addr;
uint32_t val = simple_strtoul(buf, NULL, 16);
//dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t*)(otg_dev->reg_offset +
(uint8_t*)otg_dev->base);
//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
dwc_write_reg32( addr, val );
}
else {
dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
otg_dev->reg_offset);
}
return count;
}
DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
/*
* Attributes
*/
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
/**
* @todo Add code to initiate the HNP.
*/
/**
* Show the HNP status bit
*/
static ssize_t hnp_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
gotgctl_data_t val;
val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
}
/**
* Set the HNP Request bit
*/
static ssize_t hnp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t in = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
gotgctl_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.hnpreq = in;
dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
/**
* @todo Add code to initiate the SRP.
*/
/**
* Show the SRP status bit
*/
static ssize_t srp_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
gotgctl_data_t val;
val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
#else
return sprintf(buf, "Host Only Mode!\n");
#endif
}
/**
* Set the SRP Request bit
*/
static ssize_t srp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_pcd_initiate_srp(otg_dev->pcd);
#endif
return count;
}
DEVICE_ATTR(srp, 0644, srp_show, srp_store);
/**
* @todo Need to do more for power on/off?
*/
/**
* Show the Bus Power status
*/
static ssize_t buspower_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
hprt0_data_t val;
val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
}
/**
* Set the Bus Power status
*/
static ssize_t buspower_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t on = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
hprt0_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.prtpwr = on;
//dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
/**
* @todo Need to do more for suspend?
*/
/**
* Show the Bus Suspend status
*/
static ssize_t bussuspend_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
hprt0_data_t val;
val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
}
/**
* Set the Bus Suspend status
*/
static ssize_t bussuspend_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t in = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
hprt0_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.prtsusp = in;
dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
/**
* Show the status of Remote Wakeup.
*/
static ssize_t remote_wakeup_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dctl_data_t val;
val.d32 = dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
#else
return sprintf(buf, "Host Only Mode!\n");
#endif
}
/**
* Initiate a remote wakeup of the host. The Device control register
* Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
* flag is set.
*
*/
static ssize_t remote_wakeup_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
#ifndef DWC_HOST_ONLY
uint32_t val = simple_strtoul(buf, NULL, 16);
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
if (val&1) {
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
}
else {
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
}
#endif
return count;
}
DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
remote_wakeup_store);
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifdef DEBUG
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev);
dwc_otg_dump_global_registers( otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if)) {
dwc_otg_dump_host_registers( otg_dev->core_if);
} else {
dwc_otg_dump_dev_registers( otg_dev->core_if);
}
#endif
return sprintf( buf, "Register Dump\n" );
}
DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
/**
* Dump the current hcd state.
*/
static ssize_t hcddump_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_hcd_dump_state(otg_dev->hcd);
#endif
return sprintf( buf, "HCD Dump\n" );
}
DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
*/
static ssize_t hcd_frrem_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_hcd_dump_frrem(otg_dev->hcd);
#endif
return sprintf( buf, "HCD Dump Frame Remaining\n" );
}
DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
/**
* Displays the time required to read the GNPTXFSIZ register many times (the
* output shows the number of times the register is read).
*/
#define RW_REG_COUNT 10000000
#define MSEC_PER_JIFFIE 1000/HZ
static ssize_t rd_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
int i;
int time;
int start_jiffies;
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++) {
dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
}
time = jiffies - start_jiffies;
return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
}
DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
/**
* Displays the time required to write the GNPTXFSIZ register many times (the
* output shows the number of times the register is written).
*/
static ssize_t wr_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
int i;
int time;
int start_jiffies;
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t reg_val;
printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++) {
dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
}
time = jiffies - start_jiffies;
return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
}
DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
/**@}*/
/**
* Create the device files
*/
void dwc_otg_attr_create (struct device *_dev)
{
int retval;
retval = device_create_file(_dev, &dev_attr_regoffset);
retval += device_create_file(_dev, &dev_attr_regvalue);
retval += device_create_file(_dev, &dev_attr_mode);
retval += device_create_file(_dev, &dev_attr_hnpcapable);
retval += device_create_file(_dev, &dev_attr_srpcapable);
retval += device_create_file(_dev, &dev_attr_hnp);
retval += device_create_file(_dev, &dev_attr_srp);
retval += device_create_file(_dev, &dev_attr_buspower);
retval += device_create_file(_dev, &dev_attr_bussuspend);
retval += device_create_file(_dev, &dev_attr_busconnected);
retval += device_create_file(_dev, &dev_attr_gotgctl);
retval += device_create_file(_dev, &dev_attr_gusbcfg);
retval += device_create_file(_dev, &dev_attr_grxfsiz);
retval += device_create_file(_dev, &dev_attr_gnptxfsiz);
retval += device_create_file(_dev, &dev_attr_gpvndctl);
retval += device_create_file(_dev, &dev_attr_ggpio);
retval += device_create_file(_dev, &dev_attr_guid);
retval += device_create_file(_dev, &dev_attr_gsnpsid);
retval += device_create_file(_dev, &dev_attr_devspeed);
retval += device_create_file(_dev, &dev_attr_enumspeed);
retval += device_create_file(_dev, &dev_attr_hptxfsiz);
retval += device_create_file(_dev, &dev_attr_hprt0);
retval += device_create_file(_dev, &dev_attr_remote_wakeup);
retval += device_create_file(_dev, &dev_attr_regdump);
retval += device_create_file(_dev, &dev_attr_hcddump);
retval += device_create_file(_dev, &dev_attr_hcd_frrem);
retval += device_create_file(_dev, &dev_attr_rd_reg_test);
retval += device_create_file(_dev, &dev_attr_wr_reg_test);
if(retval != 0)
{
DWC_PRINT("cannot create sysfs device files.\n");
// DWC_PRINT("killing own sysfs device files!\n");
dwc_otg_attr_remove(_dev);
}
}
/**
* Remove the device files
*/
void dwc_otg_attr_remove (struct device *_dev)
{
device_remove_file(_dev, &dev_attr_regoffset);
device_remove_file(_dev, &dev_attr_regvalue);
device_remove_file(_dev, &dev_attr_mode);
device_remove_file(_dev, &dev_attr_hnpcapable);
device_remove_file(_dev, &dev_attr_srpcapable);
device_remove_file(_dev, &dev_attr_hnp);
device_remove_file(_dev, &dev_attr_srp);
device_remove_file(_dev, &dev_attr_buspower);
device_remove_file(_dev, &dev_attr_bussuspend);
device_remove_file(_dev, &dev_attr_busconnected);
device_remove_file(_dev, &dev_attr_gotgctl);
device_remove_file(_dev, &dev_attr_gusbcfg);
device_remove_file(_dev, &dev_attr_grxfsiz);
device_remove_file(_dev, &dev_attr_gnptxfsiz);
device_remove_file(_dev, &dev_attr_gpvndctl);
device_remove_file(_dev, &dev_attr_ggpio);
device_remove_file(_dev, &dev_attr_guid);
device_remove_file(_dev, &dev_attr_gsnpsid);
device_remove_file(_dev, &dev_attr_devspeed);
device_remove_file(_dev, &dev_attr_enumspeed);
device_remove_file(_dev, &dev_attr_hptxfsiz);
device_remove_file(_dev, &dev_attr_hprt0);
device_remove_file(_dev, &dev_attr_remote_wakeup);
device_remove_file(_dev, &dev_attr_regdump);
device_remove_file(_dev, &dev_attr_hcddump);
device_remove_file(_dev, &dev_attr_hcd_frrem);
device_remove_file(_dev, &dev_attr_rd_reg_test);
device_remove_file(_dev, &dev_attr_wr_reg_test);
}

67
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_attr.h Normal file
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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510275 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_ATTR_H__)
#define __DWC_OTG_ATTR_H__
/** @file
* This file contains the interface to the Linux device attributes.
*/
extern struct device_attribute dev_attr_regoffset;
extern struct device_attribute dev_attr_regvalue;
extern struct device_attribute dev_attr_mode;
extern struct device_attribute dev_attr_hnpcapable;
extern struct device_attribute dev_attr_srpcapable;
extern struct device_attribute dev_attr_hnp;
extern struct device_attribute dev_attr_srp;
extern struct device_attribute dev_attr_buspower;
extern struct device_attribute dev_attr_bussuspend;
extern struct device_attribute dev_attr_busconnected;
extern struct device_attribute dev_attr_gotgctl;
extern struct device_attribute dev_attr_gusbcfg;
extern struct device_attribute dev_attr_grxfsiz;
extern struct device_attribute dev_attr_gnptxfsiz;
extern struct device_attribute dev_attr_gpvndctl;
extern struct device_attribute dev_attr_ggpio;
extern struct device_attribute dev_attr_guid;
extern struct device_attribute dev_attr_gsnpsid;
extern struct device_attribute dev_attr_devspeed;
extern struct device_attribute dev_attr_enumspeed;
extern struct device_attribute dev_attr_hptxfsiz;
extern struct device_attribute dev_attr_hprt0;
void dwc_otg_attr_create (struct device *_dev);
void dwc_otg_attr_remove (struct device *_dev);
#endif

3025
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_cil.c Normal file
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target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_cil.h Normal file
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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 631780 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_CIL_H__)
#define __DWC_CIL_H__
#include "dwc_otg_plat.h"
#include "dwc_otg_regs.h"
#ifdef DEBUG
#include "linux/timer.h"
#endif
/* the OTG capabilities. */
#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
/* the maximum speed of operation in host and device mode. */
#define DWC_SPEED_PARAM_HIGH 0
#define DWC_SPEED_PARAM_FULL 1
/* the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. */
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
/* the type of PHY interface to use. */
#define DWC_PHY_TYPE_PARAM_FS 0
#define DWC_PHY_TYPE_PARAM_UTMI 1
#define DWC_PHY_TYPE_PARAM_ULPI 2
/* whether to use the internal or external supply to
* drive the vbus with a ULPI phy. */
#define DWC_PHY_ULPI_INTERNAL_VBUS 0
#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
/* EP type. */
/**
* @file
* This file contains the interface to the Core Interface Layer.
*/
/**
* The <code>dwc_ep</code> structure represents the state of a single
* endpoint when acting in device mode. It contains the data items
* needed for an endpoint to be activated and transfer packets.
*/
typedef struct dwc_ep {
/** EP number used for register address lookup */
uint8_t num;
/** EP direction 0 = OUT */
unsigned is_in : 1;
/** EP active. */
unsigned active : 1;
/** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
unsigned tx_fifo_num : 4;
/** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
unsigned type : 2;
#define DWC_OTG_EP_TYPE_CONTROL 0
#define DWC_OTG_EP_TYPE_ISOC 1
#define DWC_OTG_EP_TYPE_BULK 2
#define DWC_OTG_EP_TYPE_INTR 3
/** DATA start PID for INTR and BULK EP */
unsigned data_pid_start : 1;
/** Frame (even/odd) for ISOC EP */
unsigned even_odd_frame : 1;
/** Max Packet bytes */
unsigned maxpacket : 11;
/** @name Transfer state */
/** @{ */
/**
* Pointer to the beginning of the transfer buffer -- do not modify
* during transfer.
*/
uint32_t dma_addr;
uint8_t *start_xfer_buff;
/** pointer to the transfer buffer */
uint8_t *xfer_buff;
/** Number of bytes to transfer */
unsigned xfer_len : 19;
/** Number of bytes transferred. */
unsigned xfer_count : 19;
/** Sent ZLP */
unsigned sent_zlp : 1;
/** Total len for control transfer */
unsigned total_len : 19;
/** stall clear flag */
unsigned stall_clear_flag : 1;
/** @} */
} dwc_ep_t;
/*
* Reasons for halting a host channel.
*/
typedef enum dwc_otg_halt_status {
DWC_OTG_HC_XFER_NO_HALT_STATUS,
DWC_OTG_HC_XFER_COMPLETE,
DWC_OTG_HC_XFER_URB_COMPLETE,
DWC_OTG_HC_XFER_ACK,
DWC_OTG_HC_XFER_NAK,
DWC_OTG_HC_XFER_NYET,
DWC_OTG_HC_XFER_STALL,
DWC_OTG_HC_XFER_XACT_ERR,
DWC_OTG_HC_XFER_FRAME_OVERRUN,
DWC_OTG_HC_XFER_BABBLE_ERR,
DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
DWC_OTG_HC_XFER_AHB_ERR,
DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
DWC_OTG_HC_XFER_URB_DEQUEUE
} dwc_otg_halt_status_e;
/**
* Host channel descriptor. This structure represents the state of a single
* host channel when acting in host mode. It contains the data items needed to
* transfer packets to an endpoint via a host channel.
*/
typedef struct dwc_hc {
/** Host channel number used for register address lookup */
uint8_t hc_num;
/** Device to access */
unsigned dev_addr : 7;
/** EP to access */
unsigned ep_num : 4;
/** EP direction. 0: OUT, 1: IN */
unsigned ep_is_in : 1;
/**
* EP speed.
* One of the following values:
* - DWC_OTG_EP_SPEED_LOW
* - DWC_OTG_EP_SPEED_FULL
* - DWC_OTG_EP_SPEED_HIGH
*/
unsigned speed : 2;
#define DWC_OTG_EP_SPEED_LOW 0
#define DWC_OTG_EP_SPEED_FULL 1
#define DWC_OTG_EP_SPEED_HIGH 2
/**
* Endpoint type.
* One of the following values:
* - DWC_OTG_EP_TYPE_CONTROL: 0
* - DWC_OTG_EP_TYPE_ISOC: 1
* - DWC_OTG_EP_TYPE_BULK: 2
* - DWC_OTG_EP_TYPE_INTR: 3
*/
unsigned ep_type : 2;
/** Max packet size in bytes */
unsigned max_packet : 11;
/**
* PID for initial transaction.
* 0: DATA0,<br>
* 1: DATA2,<br>
* 2: DATA1,<br>
* 3: MDATA (non-Control EP),
* SETUP (Control EP)
*/
unsigned data_pid_start : 2;
#define DWC_OTG_HC_PID_DATA0 0
#define DWC_OTG_HC_PID_DATA2 1
#define DWC_OTG_HC_PID_DATA1 2
#define DWC_OTG_HC_PID_MDATA 3
#define DWC_OTG_HC_PID_SETUP 3
/** Number of periodic transactions per (micro)frame */
unsigned multi_count: 2;
/** @name Transfer State */
/** @{ */
/** Pointer to the current transfer buffer position. */
uint8_t *xfer_buff;
/** Total number of bytes to transfer. */
uint32_t xfer_len;
/** Number of bytes transferred so far. */
uint32_t xfer_count;
/** Packet count at start of transfer.*/
uint16_t start_pkt_count;
/**
* Flag to indicate whether the transfer has been started. Set to 1 if
* it has been started, 0 otherwise.
*/
uint8_t xfer_started;
/**
* Set to 1 to indicate that a PING request should be issued on this
* channel. If 0, process normally.
*/
uint8_t do_ping;
/**
* Set to 1 to indicate that the error count for this transaction is
* non-zero. Set to 0 if the error count is 0.
*/
uint8_t error_state;
/**
* Set to 1 to indicate that this channel should be halted the next
* time a request is queued for the channel. This is necessary in
* slave mode if no request queue space is available when an attempt
* is made to halt the channel.
*/
uint8_t halt_on_queue;
/**
* Set to 1 if the host channel has been halted, but the core is not
* finished flushing queued requests. Otherwise 0.
*/
uint8_t halt_pending;
/**
* Reason for halting the host channel.
*/
dwc_otg_halt_status_e halt_status;
/*
* Split settings for the host channel
*/
uint8_t do_split; /**< Enable split for the channel */
uint8_t complete_split; /**< Enable complete split */
uint8_t hub_addr; /**< Address of high speed hub */
uint8_t port_addr; /**< Port of the low/full speed device */
/** Split transaction position
* One of the following values:
* - DWC_HCSPLIT_XACTPOS_MID
* - DWC_HCSPLIT_XACTPOS_BEGIN
* - DWC_HCSPLIT_XACTPOS_END
* - DWC_HCSPLIT_XACTPOS_ALL */
uint8_t xact_pos;
/** Set when the host channel does a short read. */
uint8_t short_read;
/**
* Number of requests issued for this channel since it was assigned to
* the current transfer (not counting PINGs).
*/
uint8_t requests;
/**
* Queue Head for the transfer being processed by this channel.
*/
struct dwc_otg_qh *qh;
/** @} */
/** Entry in list of host channels. */
struct list_head hc_list_entry;
} dwc_hc_t;
/**
* The following parameters may be specified when starting the module. These
* parameters define how the DWC_otg controller should be configured.
* Parameter values are passed to the CIL initialization function
* dwc_otg_cil_init.
*/
typedef struct dwc_otg_core_params
{
int32_t opt;
//#define dwc_param_opt_default 1
/**
* Specifies the OTG capabilities. The driver will automatically
* detect the value for this parameter if none is specified.
* 0 - HNP and SRP capable (default)
* 1 - SRP Only capable
* 2 - No HNP/SRP capable
*/
int32_t otg_cap;
#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
/**
* Specifies whether to use slave or DMA mode for accessing the data
* FIFOs. The driver will automatically detect the value for this
* parameter if none is specified.
* 0 - Slave
* 1 - DMA (default, if available)
*/
int32_t dma_enable;
//#define dwc_param_dma_enable_default 1
/** The DMA Burst size (applicable only for External DMA
* Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
*/
int32_t dma_burst_size; /* Translate this to GAHBCFG values */
//#define dwc_param_dma_burst_size_default 32
/**
* Specifies the maximum speed of operation in host and device mode.
* The actual speed depends on the speed of the attached device and
* the value of phy_type. The actual speed depends on the speed of the
* attached device.
* 0 - High Speed (default)
* 1 - Full Speed
*/
int32_t speed;
//#define dwc_param_speed_default 0
#define DWC_SPEED_PARAM_HIGH 0
#define DWC_SPEED_PARAM_FULL 1
/** Specifies whether low power mode is supported when attached
* to a Full Speed or Low Speed device in host mode.
* 0 - Don't support low power mode (default)
* 1 - Support low power mode
*/
int32_t host_support_fs_ls_low_power;
//#define dwc_param_host_support_fs_ls_low_power_default 0
/** Specifies the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. This parameter is applicable only if
* HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
* then defaults to 6 MHZ otherwise 48 MHZ.
*
* 0 - 48 MHz
* 1 - 6 MHz
*/
int32_t host_ls_low_power_phy_clk;
//#define dwc_param_host_ls_low_power_phy_clk_default 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
/**
* 0 - Use cC FIFO size parameters
* 1 - Allow dynamic FIFO sizing (default)
*/
int32_t enable_dynamic_fifo;
//#define dwc_param_enable_dynamic_fifo_default 1
/** Total number of 4-byte words in the data FIFO memory. This
* memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
* Tx FIFOs.
* 32 to 32768 (default 8192)
* Note: The total FIFO memory depth in the FPGA configuration is 8192.
*/
int32_t data_fifo_size;
//#define dwc_param_data_fifo_size_default 8192
/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1064)
*/
int32_t dev_rx_fifo_size;
//#define dwc_param_dev_rx_fifo_size_default 1064
/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
* when dynamic FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t dev_nperio_tx_fifo_size;
//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in each of the periodic Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
//#define dwc_param_dev_perio_tx_fifo_size_default 256
/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t host_rx_fifo_size;
//#define dwc_param_host_rx_fifo_size_default 1024
/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
* when Dynamic FIFO sizing is enabled in the core.
* 16 to 32768 (default 1024)
*/
int32_t host_nperio_tx_fifo_size;
//#define dwc_param_host_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t host_perio_tx_fifo_size;
//#define dwc_param_host_perio_tx_fifo_size_default 1024
/** The maximum transfer size supported in bytes.
* 2047 to 65,535 (default 65,535)
*/
int32_t max_transfer_size;
//#define dwc_param_max_transfer_size_default 65535
/** The maximum number of packets in a transfer.
* 15 to 511 (default 511)
*/
int32_t max_packet_count;
//#define dwc_param_max_packet_count_default 511
/** The number of host channel registers to use.
* 1 to 16 (default 12)
* Note: The FPGA configuration supports a maximum of 12 host channels.
*/
int32_t host_channels;
//#define dwc_param_host_channels_default 12
/** The number of endpoints in addition to EP0 available for device
* mode operations.
* 1 to 15 (default 6 IN and OUT)
* Note: The FPGA configuration supports a maximum of 6 IN and OUT
* endpoints in addition to EP0.
*/
int32_t dev_endpoints;
//#define dwc_param_dev_endpoints_default 6
/**
* Specifies the type of PHY interface to use. By default, the driver
* will automatically detect the phy_type.
*
* 0 - Full Speed PHY
* 1 - UTMI+ (default)
* 2 - ULPI
*/
int32_t phy_type;
#define DWC_PHY_TYPE_PARAM_FS 0
#define DWC_PHY_TYPE_PARAM_UTMI 1
#define DWC_PHY_TYPE_PARAM_ULPI 2
//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
/**
* Specifies the UTMI+ Data Width. This parameter is
* applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
* PHY_TYPE, this parameter indicates the data width between
* the MAC and the ULPI Wrapper.) Also, this parameter is
* applicable only if the OTG_HSPHY_WIDTH cC parameter was set
* to "8 and 16 bits", meaning that the core has been
* configured to work at either data path width.
*
* 8 or 16 bits (default 16)
*/
int32_t phy_utmi_width;
//#define dwc_param_phy_utmi_width_default 16
/**
* Specifies whether the ULPI operates at double or single
* data rate. This parameter is only applicable if PHY_TYPE is
* ULPI.
*
* 0 - single data rate ULPI interface with 8 bit wide data
* bus (default)
* 1 - double data rate ULPI interface with 4 bit wide data
* bus
*/
int32_t phy_ulpi_ddr;
//#define dwc_param_phy_ulpi_ddr_default 0
/**
* Specifies whether to use the internal or external supply to
* drive the vbus with a ULPI phy.
*/
int32_t phy_ulpi_ext_vbus;
#define DWC_PHY_ULPI_INTERNAL_VBUS 0
#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
/**
* Specifies whether to use the I2Cinterface for full speed PHY. This
* parameter is only applicable if PHY_TYPE is FS.
* 0 - No (default)
* 1 - Yes
*/
int32_t i2c_enable;
//#define dwc_param_i2c_enable_default 0
int32_t ulpi_fs_ls;
//#define dwc_param_ulpi_fs_ls_default 0
int32_t ts_dline;
//#define dwc_param_ts_dline_default 0
/**
* Specifies whether dedicated transmit FIFOs are
* enabled for non periodic IN endpoints in device mode
* 0 - No
* 1 - Yes
*/
int32_t en_multiple_tx_fifo;
#define dwc_param_en_multiple_tx_fifo_default 1
/** Number of 4-byte words in each of the Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
#define dwc_param_dev_tx_fifo_size_default 256
/** Thresholding enable flag-
* bit 0 - enable non-ISO Tx thresholding
* bit 1 - enable ISO Tx thresholding
* bit 2 - enable Rx thresholding
*/
uint32_t thr_ctl;
#define dwc_param_thr_ctl_default 0
/** Thresholding length for Tx
* FIFOs in 32 bit DWORDs
*/
uint32_t tx_thr_length;
#define dwc_param_tx_thr_length_default 64
/** Thresholding length for Rx
* FIFOs in 32 bit DWORDs
*/
uint32_t rx_thr_length;
#define dwc_param_rx_thr_length_default 64
} dwc_otg_core_params_t;
#ifdef DEBUG
struct dwc_otg_core_if;
typedef struct hc_xfer_info
{
struct dwc_otg_core_if *core_if;
dwc_hc_t *hc;
} hc_xfer_info_t;
#endif
/**
* The <code>dwc_otg_core_if</code> structure contains information needed to manage
* the DWC_otg controller acting in either host or device mode. It
* represents the programming view of the controller as a whole.
*/
typedef struct dwc_otg_core_if
{
/** Parameters that define how the core should be configured.*/
dwc_otg_core_params_t *core_params;
/** Core Global registers starting at offset 000h. */
dwc_otg_core_global_regs_t *core_global_regs;
/** Device-specific information */
dwc_otg_dev_if_t *dev_if;
/** Host-specific information */
dwc_otg_host_if_t *host_if;
/*
* Set to 1 if the core PHY interface bits in USBCFG have been
* initialized.
*/
uint8_t phy_init_done;
/*
* SRP Success flag, set by srp success interrupt in FS I2C mode
*/
uint8_t srp_success;
uint8_t srp_timer_started;
/* Common configuration information */
/** Power and Clock Gating Control Register */
volatile uint32_t *pcgcctl;
#define DWC_OTG_PCGCCTL_OFFSET 0xE00
/** Push/pop addresses for endpoints or host channels.*/
uint32_t *data_fifo[MAX_EPS_CHANNELS];
#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
#define DWC_OTG_DATA_FIFO_SIZE 0x1000
/** Total RAM for FIFOs (Bytes) */
uint16_t total_fifo_size;
/** Size of Rx FIFO (Bytes) */
uint16_t rx_fifo_size;
/** Size of Non-periodic Tx FIFO (Bytes) */
uint16_t nperio_tx_fifo_size;
/** 1 if DMA is enabled, 0 otherwise. */
uint8_t dma_enable;
/** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
uint8_t en_multiple_tx_fifo;
/** Set to 1 if multiple packets of a high-bandwidth transfer is in
* process of being queued */
uint8_t queuing_high_bandwidth;
/** Hardware Configuration -- stored here for convenience.*/
hwcfg1_data_t hwcfg1;
hwcfg2_data_t hwcfg2;
hwcfg3_data_t hwcfg3;
hwcfg4_data_t hwcfg4;
/** The operational State, during transations
* (a_host>>a_peripherial and b_device=>b_host) this may not
* match the core but allows the software to determine
* transitions.
*/
uint8_t op_state;
/**
* Set to 1 if the HCD needs to be restarted on a session request
* interrupt. This is required if no connector ID status change has
* occurred since the HCD was last disconnected.
*/
uint8_t restart_hcd_on_session_req;
/** HCD callbacks */
/** A-Device is a_host */
#define A_HOST (1)
/** A-Device is a_suspend */
#define A_SUSPEND (2)
/** A-Device is a_peripherial */
#define A_PERIPHERAL (3)
/** B-Device is operating as a Peripheral. */
#define B_PERIPHERAL (4)
/** B-Device is operating as a Host. */
#define B_HOST (5)
/** HCD callbacks */
struct dwc_otg_cil_callbacks *hcd_cb;
/** PCD callbacks */
struct dwc_otg_cil_callbacks *pcd_cb;
/** Device mode Periodic Tx FIFO Mask */
uint32_t p_tx_msk;
/** Device mode Periodic Tx FIFO Mask */
uint32_t tx_msk;
#ifdef DEBUG
uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
#if 1 // winder
uint32_t hfnum_7_samples;
uint32_t hfnum_7_frrem_accum;
uint32_t hfnum_0_samples;
uint32_t hfnum_0_frrem_accum;
uint32_t hfnum_other_samples;
uint32_t hfnum_other_frrem_accum;
#else
uint32_t hfnum_7_samples;
uint64_t hfnum_7_frrem_accum;
uint32_t hfnum_0_samples;
uint64_t hfnum_0_frrem_accum;
uint32_t hfnum_other_samples;
uint64_t hfnum_other_frrem_accum;
#endif
resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */
#endif
} dwc_otg_core_if_t;
/*
* The following functions support initialization of the CIL driver component
* and the DWC_otg controller.
*/
extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
dwc_otg_core_params_t *_core_params);
extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
/** @name Device CIL Functions
* The following functions support managing the DWC_otg controller in device
* mode.
*/
/**@{*/
extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
/**@}*/
/** @name Host CIL Functions
* The following functions support managing the DWC_otg controller in host
* mode.
*/
/**@{*/
extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
dwc_hc_t *_hc,
dwc_otg_halt_status_e _halt_status);
extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
/**
* This function Reads HPRT0 in preparation to modify. It keeps the
* WC bits 0 so that if they are read as 1, they won't clear when you
* write it back
*/
static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
{
hprt0_data_t hprt0;
hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
hprt0.b.prtena = 0;
hprt0.b.prtconndet = 0;
hprt0.b.prtenchng = 0;
hprt0.b.prtovrcurrchng = 0;
return hprt0.d32;
}
extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
/**@}*/
/** @name Common CIL Functions
* The following functions support managing the DWC_otg controller in either
* device or host mode.
*/
/**@{*/
extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
uint8_t *dest,
uint16_t bytes);
extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
const int _num );
extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
#define NP_TXFIFO_EMPTY -1
#define MAX_NP_TXREQUEST_Q_SLOTS 8
/**
* This function returns the endpoint number of the request at
* the top of non-periodic TX FIFO, or -1 if the request FIFO is
* empty.
*/
static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) {
gnptxsts_data_t txstatus = {.d32 = 0};
txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ?
-1 : txstatus.b.nptxqtop_chnep);
}
/**
* This function returns the Core Interrupt register.
*/
static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
}
/**
* This function returns the OTG Interrupt register.
*/
static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
}
/**
* This function reads the Device All Endpoints Interrupt register and
* returns the IN endpoint interrupt bits.
*/
static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) {
uint32_t v;
v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
return (v & 0xffff);
}
/**
* This function reads the Device All Endpoints Interrupt register and
* returns the OUT endpoint interrupt bits.
*/
static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) {
uint32_t v;
v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
return ((v & 0xffff0000) >> 16);
}
/**
* This function returns the Device IN EP Interrupt register
*/
static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if,
dwc_ep_t *_ep)
{
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v, msk, emp;
msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
msk |= ((emp >> _ep->num) & 0x1) << 7;
v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk;
/*
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v;
v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) &
dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
*/
return v;
}
/**
* This function returns the Device OUT EP Interrupt register
*/
static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
dwc_ep_t *_ep)
{
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v;
v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) &
dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
return v;
}
/**
* This function returns the Host All Channel Interrupt register
*/
static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
{
return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
}
static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
{
return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
}
/**
* This function returns the mode of the operation, host or device.
*
* @return 0 - Device Mode, 1 - Host Mode
*/
static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
}
static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
{
return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
}
static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
{
return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
}
extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
/**@}*/
/**
* DWC_otg CIL callback structure. This structure allows the HCD and
* PCD to register functions used for starting and stopping the PCD
* and HCD for role change on for a DRD.
*/
typedef struct dwc_otg_cil_callbacks
{
/** Start function for role change */
int (*start) (void *_p);
/** Stop Function for role change */
int (*stop) (void *_p);
/** Disconnect Function for role change */
int (*disconnect) (void *_p);
/** Resume/Remote wakeup Function */
int (*resume_wakeup) (void *_p);
/** Suspend function */
int (*suspend) (void *_p);
/** Session Start (SRP) */
int (*session_start) (void *_p);
/** Pointer passed to start() and stop() */
void *p;
} dwc_otg_cil_callbacks_t;
extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
dwc_otg_cil_callbacks_t *_cb,
void *_p);
extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
dwc_otg_cil_callbacks_t *_cb,
void *_p);
#endif

58
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h Normal file
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@@ -0,0 +1,58 @@
/******************************************************************************
**
** FILE NAME : dwc_otg_cil_ifx.h
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 07 Sep. 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Default param value.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 April 2007 Sung Winder Initiate Version
*******************************************************************************/
#if !defined(__DWC_OTG_CIL_IFX_H__)
#define __DWC_OTG_CIL_IFX_H__
/* ================ Default param value ================== */
#define dwc_param_opt_default 1
#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
#define dwc_param_dma_enable_default 1
#define dwc_param_dma_burst_size_default 32
#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH
#define dwc_param_host_support_fs_ls_low_power_default 0
#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ
#define dwc_param_enable_dynamic_fifo_default 1
#define dwc_param_data_fifo_size_default 2048
#define dwc_param_dev_rx_fifo_size_default 1024
#define dwc_param_dev_nperio_tx_fifo_size_default 1024
#define dwc_param_dev_perio_tx_fifo_size_default 768
#define dwc_param_host_rx_fifo_size_default 640
#define dwc_param_host_nperio_tx_fifo_size_default 640
#define dwc_param_host_perio_tx_fifo_size_default 768
#define dwc_param_max_transfer_size_default 65535
#define dwc_param_max_packet_count_default 511
#define dwc_param_host_channels_default 16
#define dwc_param_dev_endpoints_default 6
#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
#define dwc_param_phy_utmi_width_default 16
#define dwc_param_phy_ulpi_ddr_default 0
#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
#define dwc_param_i2c_enable_default 0
#define dwc_param_ulpi_fs_ls_default 0
#define dwc_param_ts_dline_default 0
/* ======================================================= */
#endif // __DWC_OTG_CIL_IFX_H__

708
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_cil_intr.c Normal file
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@@ -0,0 +1,708 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil_intr.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 553126 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
/** @file
*
* The Core Interface Layer provides basic services for accessing and
* managing the DWC_otg hardware. These services are used by both the
* Host Controller Driver and the Peripheral Controller Driver.
*
* This file contains the Common Interrupt handlers.
*/
#include "dwc_otg_plat.h"
#include "dwc_otg_regs.h"
#include "dwc_otg_cil.h"
#ifdef DEBUG
inline const char *op_state_str( dwc_otg_core_if_t *_core_if )
{
return (_core_if->op_state==A_HOST?"a_host":
(_core_if->op_state==A_SUSPEND?"a_suspend":
(_core_if->op_state==A_PERIPHERAL?"a_peripheral":
(_core_if->op_state==B_PERIPHERAL?"b_peripheral":
(_core_if->op_state==B_HOST?"b_host":
"unknown")))));
}
#endif
/** This function will log a debug message
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
dwc_otg_mode(_core_if) ? "Host" : "Device");
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.modemismatch = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/** Start the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
_core_if->hcd_cb->start( _core_if->hcd_cb->p );
}
}
/** Stop the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_stop( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
_core_if->hcd_cb->stop( _core_if->hcd_cb->p );
}
}
/** Disconnect the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_disconnect( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
_core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
}
}
/** Inform the HCD the a New Session has begun. Helper function for
* using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_session_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->session_start) {
_core_if->hcd_cb->session_start( _core_if->hcd_cb->p );
}
}
/** Start the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->start ) {
_core_if->pcd_cb->start( _core_if->pcd_cb->p );
}
}
/** Stop the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_stop( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->stop ) {
_core_if->pcd_cb->stop( _core_if->pcd_cb->p );
}
}
/** Suspend the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_suspend( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->suspend ) {
_core_if->pcd_cb->suspend( _core_if->pcd_cb->p );
}
}
/** Resume the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_resume( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup ) {
_core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
}
}
/**
* This function handles the OTG Interrupts. It reads the OTG
* Interrupt Register (GOTGINT) to determine what interrupt has
* occurred.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *_core_if)
{
dwc_otg_core_global_regs_t *global_regs =
_core_if->core_global_regs;
gotgint_data_t gotgint;
gotgctl_data_t gotgctl;
gintmsk_data_t gintmsk;
gotgint.d32 = dwc_read_reg32( &global_regs->gotgint);
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
op_state_str(_core_if));
//DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32 );
if (gotgint.b.sesenddet) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Session End Detected++ (%s)\n",
op_state_str(_core_if));
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
if (_core_if->op_state == B_HOST) {
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else {
/* If not B_HOST and Device HNP still set. HNP
* Did not succeed!*/
if (gotgctl.b.devhnpen) {
DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
DWC_ERROR( "Device Not Connected/Responding!\n" );
}
/* If Session End Detected the B-Cable has
* been disconnected. */
/* Reset PCD and Gadget driver to a
* clean state. */
pcd_stop(_core_if);
}
gotgctl.d32 = 0;
gotgctl.b.devhnpen = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
}
if (gotgint.b.sesreqsucstschng) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Session Reqeust Success Status Change++\n");
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
if (gotgctl.b.sesreqscs) {
if ((_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
(_core_if->core_params->i2c_enable)) {
_core_if->srp_success = 1;
}
else {
pcd_resume( _core_if );
/* Clear Session Request */
gotgctl.d32 = 0;
gotgctl.b.sesreq = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
}
}
}
if (gotgint.b.hstnegsucstschng) {
/* Print statements during the HNP interrupt handling
* can cause it to fail.*/
gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
if (gotgctl.b.hstnegscs) {
if (dwc_otg_is_host_mode(_core_if) ) {
_core_if->op_state = B_HOST;
/*
* Need to disable SOF interrupt immediately.
* When switching from device to host, the PCD
* interrupt handler won't handle the
* interrupt if host mode is already set. The
* HCD interrupt handler won't get called if
* the HCD state is HALT. This means that the
* interrupt does not get handled and Linux
* complains loudly.
*/
gintmsk.d32 = 0;
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&global_regs->gintmsk,
gintmsk.d32, 0);
pcd_stop(_core_if);
/*
* Initialize the Core for Host mode.
*/
hcd_start( _core_if );
_core_if->op_state = B_HOST;
}
} else {
gotgctl.d32 = 0;
gotgctl.b.hnpreq = 1;
gotgctl.b.devhnpen = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
DWC_DEBUGPL( DBG_ANY, "HNP Failed\n");
DWC_ERROR( "Device Not Connected/Responding\n" );
}
}
if (gotgint.b.hstnegdet) {
/* The disconnect interrupt is set at the same time as
* Host Negotiation Detected. During the mode
* switch all interrupts are cleared so the disconnect
* interrupt handler will not get executed.
*/
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Host Negotiation Detected++ (%s)\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
if (dwc_otg_is_device_mode(_core_if)){
DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",_core_if->op_state);
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = A_PERIPHERAL;
} else {
/*
* Need to disable SOF interrupt immediately. When
* switching from device to host, the PCD interrupt
* handler won't handle the interrupt if host mode is
* already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that
* the interrupt does not get handled and Linux
* complains loudly.
*/
gintmsk.d32 = 0;
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&global_regs->gintmsk,
gintmsk.d32, 0);
pcd_stop( _core_if );
hcd_start( _core_if );
_core_if->op_state = A_HOST;
}
}
if (gotgint.b.adevtoutchng) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"A-Device Timeout Change++\n");
}
if (gotgint.b.debdone) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Debounce Done++\n");
}
/* Clear GOTGINT */
dwc_write_reg32 (&_core_if->core_global_regs->gotgint, gotgint.d32);
return 1;
}
/**
* This function handles the Connector ID Status Change Interrupt. It
* reads the OTG Interrupt Register (GOTCTL) to determine whether this
* is a Device to Host Mode transition or a Host Mode to Device
* Transition.
*
* This only occurs when the cable is connected/removed from the PHY
* connector.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *_core_if)
{
uint32_t count = 0;
gintsts_data_t gintsts = { .d32 = 0 };
gintmsk_data_t gintmsk = { .d32 = 0 };
gotgctl_data_t gotgctl = { .d32 = 0 };
/*
* Need to disable SOF interrupt immediately. If switching from device
* to host, the PCD interrupt handler won't handle the interrupt if
* host mode is already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that the interrupt does
* not get handled and Linux complains loudly.
*/
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts) {
/* Wait for switch to device mode. */
while (!dwc_otg_is_device_mode(_core_if) ){
DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
MDELAY(100);
if (++count > 10000) *(uint32_t*)NULL=0;
}
_core_if->op_state = B_PERIPHERAL;
dwc_otg_core_init(_core_if);
dwc_otg_enable_global_interrupts(_core_if);
pcd_start( _core_if );
} else {
/* A-Device connector (Host Mode) */
while (!dwc_otg_is_host_mode(_core_if) ) {
DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
MDELAY(100);
if (++count > 10000) *(uint32_t*)NULL=0;
}
_core_if->op_state = A_HOST;
/*
* Initialize the Core for Host mode.
*/
dwc_otg_core_init(_core_if);
dwc_otg_enable_global_interrupts(_core_if);
hcd_start( _core_if );
}
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device is initiating the Session
* Request Protocol to request the host to turn on bus power so a new
* session can begin. The handler responds by turning on bus power. If
* the DWC_otg controller is in low power mode, the handler brings the
* controller out of low power mode before turning on bus power.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_session_req_intr( dwc_otg_core_if_t *_core_if )
{
#ifndef DWC_HOST_ONLY // winder
hprt0_data_t hprt0;
#endif
gintsts_data_t gintsts;
#ifndef DWC_HOST_ONLY
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
if (dwc_otg_is_device_mode(_core_if) ) {
DWC_PRINT("SRP: Device mode\n");
} else {
DWC_PRINT("SRP: Host mode\n");
/* Turn on the port power bit. */
hprt0.d32 = dwc_otg_read_hprt0( _core_if );
hprt0.b.prtpwr = 1;
dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
/* Start the Connection timer. So a message can be displayed
* if connect does not occur within 10 seconds. */
hcd_session_start( _core_if );
}
#endif
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that the DWC_otg controller has detected a
* resume or remote wakeup sequence. If the DWC_otg controller is in
* low power mode, the handler must brings the controller out of low
* power mode. The controller automatically begins resume
* signaling. The handler schedules a time to stop resume signaling.
*/
int32_t dwc_otg_handle_wakeup_detected_intr( dwc_otg_core_if_t *_core_if )
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
if (dwc_otg_is_device_mode(_core_if) ) {
dctl_data_t dctl = {.d32=0};
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts));
#ifdef PARTIAL_POWER_DOWN
if (_core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32=0};
power.d32 = dwc_read_reg32( _core_if->pcgcctl );
DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
power.b.stoppclk = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.pwrclmp = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
}
#endif
/* Clear the Remote Wakeup Signalling */
dctl.b.rmtwkupsig = 1;
dwc_modify_reg32( &_core_if->dev_if->dev_global_regs->dctl,
dctl.d32, 0 );
if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) {
_core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
}
} else {
/*
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
* so that OPT tests pass with all PHYs).
*/
hprt0_data_t hprt0 = {.d32=0};
pcgcctl_data_t pcgcctl = {.d32=0};
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0);
UDELAY(10);
/* Now wait for 70 ms. */
hprt0.d32 = dwc_otg_read_hprt0( _core_if );
DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
MDELAY(70);
hprt0.b.prtres = 0; /* Resume */
dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(_core_if->host_if->hprt0));
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.wkupintr = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device has been disconnected from
* the root port.
*/
int32_t dwc_otg_handle_disconnect_intr( dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"),
op_state_str(_core_if));
/** @todo Consolidate this if statement. */
#ifndef DWC_HOST_ONLY
if (_core_if->op_state == B_HOST) {
/* If in device mode Disconnect and stop the HCD, then
* start the PCD. */
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else if (dwc_otg_is_device_mode(_core_if)) {
gotgctl_data_t gotgctl = { .d32 = 0 };
gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
if (gotgctl.b.hstsethnpen==1) {
/* Do nothing, if HNP in process the OTG
* interrupt "Host Negotiation Detected"
* interrupt will do the mode switch.
*/
} else if (gotgctl.b.devhnpen == 0) {
/* If in device mode Disconnect and stop the HCD, then
* start the PCD. */
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else {
DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
}
} else {
if (_core_if->op_state == A_HOST) {
/* A-Cable still connected but device disconnected. */
hcd_disconnect( _core_if );
}
}
#endif
/* Without OTG, we should use the disconnect function!? winder added.*/
#if 1 // NO OTG, so host only!!
hcd_disconnect( _core_if );
#endif
gintsts.d32 = 0;
gintsts.b.disconnect = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that SUSPEND state has been detected on
* the USB.
*
* For HNP the USB Suspend interrupt signals the change from
* "a_peripheral" to "a_host".
*
* When power management is enabled the core will be put in low power
* mode.
*/
int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *_core_if )
{
dsts_data_t dsts;
gintsts_data_t gintsts;
//805141:<IFTW-fchang>.removed DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
if (dwc_otg_is_device_mode( _core_if ) ) {
/* Check the Device status register to determine if the Suspend
* state is active. */
dsts.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts);
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
"HWCFG4.power Optimize=%d\n",
dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz);
#ifdef PARTIAL_POWER_DOWN
/** @todo Add a module parameter for power management. */
if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32=0};
DWC_DEBUGPL(DBG_CIL, "suspend\n");
power.b.pwrclmp = 1;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 1;
dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
power.b.stoppclk = 1;
dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
} else {
DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
}
#endif
/* PCD callback for suspend. */
pcd_suspend(_core_if);
} else {
if (_core_if->op_state == A_PERIPHERAL) {
DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
/* Clear the a_peripheral flag, back to a_host. */
pcd_stop( _core_if );
hcd_start( _core_if );
_core_if->op_state = A_HOST;
}
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.usbsuspend = 1;
dwc_write_reg32( &_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This function returns the Core Interrupt register.
*/
static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
gintmsk_data_t gintmsk;
gintmsk_data_t gintmsk_common = {.d32=0};
gintmsk_common.b.wkupintr = 1;
gintmsk_common.b.sessreqintr = 1;
gintmsk_common.b.conidstschng = 1;
gintmsk_common.b.otgintr = 1;
gintmsk_common.b.modemismatch = 1;
gintmsk_common.b.disconnect = 1;
gintmsk_common.b.usbsuspend = 1;
/** @todo: The port interrupt occurs while in device
* mode. Added code to CIL to clear the interrupt for now!
*/
gintmsk_common.b.portintr = 1;
gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts);
gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk);
#ifdef DEBUG
/* if any common interrupts set */
if (gintsts.d32 & gintmsk_common.d32) {
DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
gintsts.d32, gintmsk.d32);
}
#endif
return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
}
/**
* Common interrupt handler.
*
* The common interrupts are those that occur in both Host and Device mode.
* This handler handles the following interrupts:
* - Mode Mismatch Interrupt
* - Disconnect Interrupt
* - OTG Interrupt
* - Connector ID Status Change Interrupt
* - Session Request Interrupt.
* - Resume / Remote Wakeup Detected Interrupt.
*
*/
extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if )
{
int retval = 0;
gintsts_data_t gintsts;
gintsts.d32 = dwc_otg_read_common_intr(_core_if);
if (gintsts.b.modemismatch) {
retval |= dwc_otg_handle_mode_mismatch_intr( _core_if );
}
if (gintsts.b.otgintr) {
retval |= dwc_otg_handle_otg_intr( _core_if );
}
if (gintsts.b.conidstschng) {
retval |= dwc_otg_handle_conn_id_status_change_intr( _core_if );
}
if (gintsts.b.disconnect) {
retval |= dwc_otg_handle_disconnect_intr( _core_if );
}
if (gintsts.b.sessreqintr) {
retval |= dwc_otg_handle_session_req_intr( _core_if );
}
if (gintsts.b.wkupintr) {
retval |= dwc_otg_handle_wakeup_detected_intr( _core_if );
}
if (gintsts.b.usbsuspend) {
retval |= dwc_otg_handle_usb_suspend_intr( _core_if );
}
if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) {
/* The port interrupt occurs while in device mode with HPRT0
* Port Enable/Disable.
*/
gintsts.d32 = 0;
gintsts.b.portintr = 1;
dwc_write_reg32(&_core_if->core_global_regs->gintsts,
gintsts.d32);
retval |= 1;
}
return retval;
}

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510275 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_DRIVER_H__)
#define __DWC_OTG_DRIVER_H__
/** @file
* This file contains the interface to the Linux driver.
*/
#include "dwc_otg_cil.h"
/* Type declarations */
struct dwc_otg_pcd;
struct dwc_otg_hcd;
/**
* This structure is a wrapper that encapsulates the driver components used to
* manage a single DWC_otg controller.
*/
typedef struct dwc_otg_device
{
/** Base address returned from ioremap() */
void *base;
/** Pointer to the core interface structure. */
dwc_otg_core_if_t *core_if;
/** Register offset for Diagnostic API.*/
uint32_t reg_offset;
/** Pointer to the PCD structure. */
struct dwc_otg_pcd *pcd;
/** Pointer to the HCD structure. */
struct dwc_otg_hcd *hcd;
/** Flag to indicate whether the common IRQ handler is installed. */
uint8_t common_irq_installed;
/** Interrupt request number. */
unsigned int irq;
/** Physical address of Control and Status registers, used by
* release_mem_region().
*/
resource_size_t phys_addr;
/** Length of memory region, used by release_mem_region(). */
unsigned long base_len;
} dwc_otg_device_t;
//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg)
#endif

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef DWC_DEVICE_ONLY
#if !defined(__DWC_HCD_H__)
#define __DWC_HCD_H__
#include <linux/list.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
struct lm_device;
struct dwc_otg_device;
#include "dwc_otg_cil.h"
//#include "dwc_otg_ifx.h" // winder
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Host Contoller Driver (HCD).
*
* The Host Controller Driver (HCD) is responsible for translating requests
* from the USB Driver into the appropriate actions on the DWC_otg controller.
* It isolates the USBD from the specifics of the controller by providing an
* API to the USBD.
*/
/**
* Phases for control transfers.
*/
typedef enum dwc_otg_control_phase {
DWC_OTG_CONTROL_SETUP,
DWC_OTG_CONTROL_DATA,
DWC_OTG_CONTROL_STATUS
} dwc_otg_control_phase_e;
/** Transaction types. */
typedef enum dwc_otg_transaction_type {
DWC_OTG_TRANSACTION_NONE,
DWC_OTG_TRANSACTION_PERIODIC,
DWC_OTG_TRANSACTION_NON_PERIODIC,
DWC_OTG_TRANSACTION_ALL
} dwc_otg_transaction_type_e;
/**
* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
* interrupt, or isochronous transfer. A single QTD is created for each URB
* (of one of these types) submitted to the HCD. The transfer associated with
* a QTD may require one or multiple transactions.
*
* A QTD is linked to a Queue Head, which is entered in either the
* non-periodic or periodic schedule for execution. When a QTD is chosen for
* execution, some or all of its transactions may be executed. After
* execution, the state of the QTD is updated. The QTD may be retired if all
* its transactions are complete or if an error occurred. Otherwise, it
* remains in the schedule so more transactions can be executed later.
*/
struct dwc_otg_qh;
typedef struct dwc_otg_qtd {
/**
* Determines the PID of the next data packet for the data phase of
* control transfers. Ignored for other transfer types.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Current phase for control transfers (Setup, Data, or Status). */
dwc_otg_control_phase_e control_phase;
/** Keep track of the current split type
* for FS/LS endpoints on a HS Hub */
uint8_t complete_split;
/** How many bytes transferred during SSPLIT OUT */
uint32_t ssplit_out_xfer_count;
/**
* Holds the number of bus errors that have occurred for a transaction
* within this transfer.
*/
uint8_t error_count;
/**
* Index of the next frame descriptor for an isochronous transfer. A
* frame descriptor describes the buffer position and length of the
* data to be transferred in the next scheduled (micro)frame of an
* isochronous transfer. It also holds status for that transaction.
* The frame index starts at 0.
*/
int isoc_frame_index;
/** Position of the ISOC split on full/low speed */
uint8_t isoc_split_pos;
/** Position of the ISOC split in the buffer for the current frame */
uint16_t isoc_split_offset;
/** URB for this transfer */
struct urb *urb;
/** This list of QTDs */
struct list_head qtd_list_entry;
/* Field to track the qh pointer */
struct dwc_otg_qh *qtd_qh_ptr;
} dwc_otg_qtd_t;
/**
* A Queue Head (QH) holds the static characteristics of an endpoint and
* maintains a list of transfers (QTDs) for that endpoint. A QH structure may
* be entered in either the non-periodic or periodic schedule.
*/
typedef struct dwc_otg_qh {
/**
* Endpoint type.
* One of the following values:
* - USB_ENDPOINT_XFER_CONTROL
* - USB_ENDPOINT_XFER_ISOC
* - USB_ENDPOINT_XFER_BULK
* - USB_ENDPOINT_XFER_INT
*/
uint8_t ep_type;
uint8_t ep_is_in;
/** wMaxPacketSize Field of Endpoint Descriptor. */
uint16_t maxp;
/**
* Determines the PID of the next data packet for non-control
* transfers. Ignored for control transfers.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Ping state if 1. */
uint8_t ping_state;
/**
* List of QTDs for this QH.
*/
struct list_head qtd_list;
/** Host channel currently processing transfers for this QH. */
dwc_hc_t *channel;
/** QTD currently assigned to a host channel for this QH. */
dwc_otg_qtd_t *qtd_in_process;
/** Full/low speed endpoint on high-speed hub requires split. */
uint8_t do_split;
/** @name Periodic schedule information */
/** @{ */
/** Bandwidth in microseconds per (micro)frame. */
uint8_t usecs;
/** Interval between transfers in (micro)frames. */
uint16_t interval;
/**
* (micro)frame to initialize a periodic transfer. The transfer
* executes in the following (micro)frame.
*/
uint16_t sched_frame;
/** (micro)frame at which last start split was initialized. */
uint16_t start_split_frame;
/** @} */
uint16_t speed;
uint16_t frame_usecs[8];
/** Entry for QH in either the periodic or non-periodic schedule. */
struct list_head qh_list_entry;
} dwc_otg_qh_t;
/**
* This structure holds the state of the HCD, including the non-periodic and
* periodic schedules.
*/
typedef struct dwc_otg_hcd {
spinlock_t lock;
/** DWC OTG Core Interface Layer */
dwc_otg_core_if_t *core_if;
/** Internal DWC HCD Flags */
volatile union dwc_otg_hcd_internal_flags {
uint32_t d32;
struct {
unsigned port_connect_status_change : 1;
unsigned port_connect_status : 1;
unsigned port_reset_change : 1;
unsigned port_enable_change : 1;
unsigned port_suspend_change : 1;
unsigned port_over_current_change : 1;
unsigned reserved : 27;
} b;
} flags;
/**
* Inactive items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are not
* currently assigned to a host channel.
*/
struct list_head non_periodic_sched_inactive;
/**
* Deferred items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are not
* currently assigned to a host channel.
* When we get an NAK, the QH goes here.
*/
struct list_head non_periodic_sched_deferred;
/**
* Active items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are
* currently assigned to a host channel.
*/
struct list_head non_periodic_sched_active;
/**
* Pointer to the next Queue Head to process in the active
* non-periodic schedule.
*/
struct list_head *non_periodic_qh_ptr;
/**
* Inactive items in the periodic schedule. This is a list of QHs for
* periodic transfers that are _not_ scheduled for the next frame.
* Each QH in the list has an interval counter that determines when it
* needs to be scheduled for execution. This scheduling mechanism
* allows only a simple calculation for periodic bandwidth used (i.e.
* must assume that all periodic transfers may need to execute in the
* same frame). However, it greatly simplifies scheduling and should
* be sufficient for the vast majority of OTG hosts, which need to
* connect to a small number of peripherals at one time.
*
* Items move from this list to periodic_sched_ready when the QH
* interval counter is 0 at SOF.
*/
struct list_head periodic_sched_inactive;
/**
* List of periodic QHs that are ready for execution in the next
* frame, but have not yet been assigned to host channels.
*
* Items move from this list to periodic_sched_assigned as host
* channels become available during the current frame.
*/
struct list_head periodic_sched_ready;
/**
* List of periodic QHs to be executed in the next frame that are
* assigned to host channels.
*
* Items move from this list to periodic_sched_queued as the
* transactions for the QH are queued to the DWC_otg controller.
*/
struct list_head periodic_sched_assigned;
/**
* List of periodic QHs that have been queued for execution.
*
* Items move from this list to either periodic_sched_inactive or
* periodic_sched_ready when the channel associated with the transfer
* is released. If the interval for the QH is 1, the item moves to
* periodic_sched_ready because it must be rescheduled for the next
* frame. Otherwise, the item moves to periodic_sched_inactive.
*/
struct list_head periodic_sched_queued;
/**
* Total bandwidth claimed so far for periodic transfers. This value
* is in microseconds per (micro)frame. The assumption is that all
* periodic transfers may occur in the same (micro)frame.
*/
uint16_t periodic_usecs;
/**
* Total bandwidth claimed so far for all periodic transfers
* in a frame.
* This will include a mixture of HS and FS transfers.
* Units are microseconds per (micro)frame.
* We have a budget per frame and have to schedule
* transactions accordingly.
* Watch out for the fact that things are actually scheduled for the
* "next frame".
*/
uint16_t frame_usecs[8];
/**
* Frame number read from the core at SOF. The value ranges from 0 to
* DWC_HFNUM_MAX_FRNUM.
*/
uint16_t frame_number;
/**
* Free host channels in the controller. This is a list of
* dwc_hc_t items.
*/
struct list_head free_hc_list;
/**
* Number of available host channels.
*/
int available_host_channels;
/**
* Array of pointers to the host channel descriptors. Allows accessing
* a host channel descriptor given the host channel number. This is
* useful in interrupt handlers.
*/
dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
/**
* Buffer to use for any data received during the status phase of a
* control transfer. Normally no data is transferred during the status
* phase. This buffer is used as a bit bucket.
*/
uint8_t *status_buf;
/**
* DMA address for status_buf.
*/
dma_addr_t status_buf_dma;
#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
/**
* Structure to allow starting the HCD in a non-interrupt context
* during an OTG role change.
*/
struct work_struct start_work;
struct usb_hcd *_p;
/**
* Connection timer. An OTG host must display a message if the device
* does not connect. Started when the VBus power is turned on via
* sysfs attribute "buspower".
*/
struct timer_list conn_timer;
/* Tasket to do a reset */
struct tasklet_struct *reset_tasklet;
#ifdef DEBUG
uint32_t frrem_samples;
uint64_t frrem_accum;
uint32_t hfnum_7_samples_a;
uint64_t hfnum_7_frrem_accum_a;
uint32_t hfnum_0_samples_a;
uint64_t hfnum_0_frrem_accum_a;
uint32_t hfnum_other_samples_a;
uint64_t hfnum_other_frrem_accum_a;
uint32_t hfnum_7_samples_b;
uint64_t hfnum_7_frrem_accum_b;
uint32_t hfnum_0_samples_b;
uint64_t hfnum_0_frrem_accum_b;
uint32_t hfnum_other_samples_b;
uint64_t hfnum_other_frrem_accum_b;
#endif
} dwc_otg_hcd_t;
/** Gets the dwc_otg_hcd from a struct usb_hcd */
static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
{
return (dwc_otg_hcd_t *)(hcd->hcd_priv);
}
/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
{
return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
}
/** @name HCD Create/Destroy Functions */
/** @{ */
extern int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device);
extern void dwc_otg_hcd_remove(struct device *_dev);
/** @} */
/** @name Linux HC Driver API Functions */
/** @{ */
extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
struct urb *urb,
gfp_t mem_flags);
extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
struct urb *urb,
int status);
extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
struct usb_host_endpoint *ep);
extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
char *buf);
extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
u16 typeReq,
u16 wValue,
u16 wIndex,
char *buf,
u16 wLength);
/** @} */
/** @name Transaction Execution Functions */
/** @{ */
extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd);
extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
dwc_otg_transaction_type_e _tr_type);
extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *_urb,
int _status);
/** @} */
/** @name Interrupt Handler Functions */
/** @{ */
extern int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num);
extern int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
/** @} */
/** @name Schedule Queue Functions */
/** @{ */
/* Implemented in dwc_otg_hcd_queue.c */
extern dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb);
extern void dwc_otg_hcd_qh_init (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb);
extern void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh);
extern int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
extern void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
extern void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_csplit);
extern int dwc_otg_hcd_qh_deferr (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int delay);
/** Remove and free a QH */
static inline void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *_hcd,
dwc_otg_qh_t *_qh)
{
dwc_otg_hcd_qh_remove (_hcd, _qh);
dwc_otg_hcd_qh_free (_qh);
}
/** Allocates memory for a QH structure.
* @return Returns the memory allocate or NULL on error. */
static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc (void)
{
#ifdef _SC_BUILD_
return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_ATOMIC);
#else
return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_KERNEL);
#endif
}
extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb);
extern void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb);
extern int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
/** Allocates memory for a QTD structure.
* @return Returns the memory allocate or NULL on error. */
static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc (void)
{
#ifdef _SC_BUILD_
return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_ATOMIC);
#else
return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_KERNEL);
#endif
}
/** Frees the memory for a QTD structure. QTD should already be removed from
* list.
* @param[in] _qtd QTD to free.*/
static inline void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *_qtd)
{
kfree (_qtd);
}
/** Removes a QTD from list.
* @param[in] _qtd QTD to remove from list. */
static inline void dwc_otg_hcd_qtd_remove (dwc_otg_qtd_t *_qtd)
{
unsigned long flags;
local_irq_save (flags);
list_del (&_qtd->qtd_list_entry);
local_irq_restore (flags);
}
/** Remove and free a QTD */
static inline void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_qtd_t *_qtd)
{
dwc_otg_hcd_qtd_remove (_qtd);
dwc_otg_hcd_qtd_free (_qtd);
}
/** @} */
/** @name Internal Functions */
/** @{ */
dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb);
void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd);
void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd);
/** @} */
/** Gets the usb_host_endpoint associated with an URB. */
static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *_urb)
{
struct usb_device *dev = _urb->dev;
int ep_num = usb_pipeendpoint(_urb->pipe);
if (usb_pipein(_urb->pipe))
return dev->ep_in[ep_num];
else
return dev->ep_out[ep_num];
}
/**
* Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
* qualified with its direction (possible 32 endpoints per device).
*/
#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) \
((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
/** Gets the QH that contains the list_head */
#define dwc_list_to_qh(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qh_t,qh_list_entry))
/** Gets the QTD that contains the list_head */
#define dwc_list_to_qtd(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qtd_t,qtd_list_entry))
/** Check if QH is non-periodic */
#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
(_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
/** Packet size for any kind of endpoint descriptor */
#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
/**
* Returns true if _frame1 is less than or equal to _frame2. The comparison is
* done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
* frame number when the max frame number is reached.
*/
static inline int dwc_frame_num_le(uint16_t _frame1, uint16_t _frame2)
{
return ((_frame2 - _frame1) & DWC_HFNUM_MAX_FRNUM) <=
(DWC_HFNUM_MAX_FRNUM >> 1);
}
/**
* Returns true if _frame1 is greater than _frame2. The comparison is done
* modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
* number when the max frame number is reached.
*/
static inline int dwc_frame_num_gt(uint16_t _frame1, uint16_t _frame2)
{
return (_frame1 != _frame2) &&
(((_frame1 - _frame2) & DWC_HFNUM_MAX_FRNUM) <
(DWC_HFNUM_MAX_FRNUM >> 1));
}
/**
* Increments _frame by the amount specified by _inc. The addition is done
* modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
*/
static inline uint16_t dwc_frame_num_inc(uint16_t _frame, uint16_t _inc)
{
return (_frame + _inc) & DWC_HFNUM_MAX_FRNUM;
}
static inline uint16_t dwc_full_frame_num (uint16_t _frame)
{
return ((_frame) & DWC_HFNUM_MAX_FRNUM) >> 3;
}
static inline uint16_t dwc_micro_frame_num (uint16_t _frame)
{
return (_frame) & 0x7;
}
#ifdef DEBUG
/**
* Macro to sample the remaining PHY clocks left in the current frame. This
* may be used during debugging to determine the average time it takes to
* execute sections of code. There are two possible sample points, "a" and
* "b", so the _letter argument must be one of these values.
*
* To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
* example, "cat /sys/devices/lm0/hcd_frrem".
*/
#define dwc_sample_frrem(_hcd, _qh, _letter) \
{ \
hfnum_data_t hfnum; \
dwc_otg_qtd_t *qtd; \
qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
switch (hfnum.b.frnum & 0x7) { \
case 7: \
_hcd->hfnum_7_samples_##_letter++; \
_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
case 0: \
_hcd->hfnum_0_samples_##_letter++; \
_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
default: \
_hcd->hfnum_other_samples_##_letter++; \
_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
} \
} \
}
#else // DEBUG
#define dwc_sample_frrem(_hcd, _qh, _letter)
#endif // DEBUG
#endif // __DWC_HCD_H__
#endif /* DWC_DEVICE_ONLY */

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef DWC_DEVICE_ONLY
/**
* @file
*
* This file contains the functions to manage Queue Heads and Queue
* Transfer Descriptors.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include "dwc_otg_driver.h"
#include "dwc_otg_hcd.h"
#include "dwc_otg_regs.h"
/**
* This function allocates and initializes a QH.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param[in] _urb Holds the information about the device/endpoint that we need
* to initialize the QH.
*
* @return Returns pointer to the newly allocated QH, or NULL on error. */
dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
{
dwc_otg_qh_t *qh;
/* Allocate memory */
/** @todo add memflags argument */
qh = dwc_otg_hcd_qh_alloc ();
if (qh == NULL) {
return NULL;
}
dwc_otg_hcd_qh_init (_hcd, qh, _urb);
return qh;
}
/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
* removed from a list. QTD list should already be empty if called from URB
* Dequeue.
*
* @param[in] _qh The QH to free.
*/
void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
{
dwc_otg_qtd_t *qtd;
struct list_head *pos;
unsigned long flags;
/* Free each QTD in the QTD list */
local_irq_save (flags);
for (pos = _qh->qtd_list.next;
pos != &_qh->qtd_list;
pos = _qh->qtd_list.next)
{
list_del (pos);
qtd = dwc_list_to_qtd (pos);
dwc_otg_hcd_qtd_free (qtd);
}
local_irq_restore (flags);
kfree (_qh);
return;
}
/** Initializes a QH structure.
*
* @param[in] _hcd The HCD state structure for the DWC OTG controller.
* @param[in] _qh The QH to init.
* @param[in] _urb Holds the information about the device/endpoint that we need
* to initialize the QH. */
#define SCHEDULE_SLOP 10
void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
{
memset (_qh, 0, sizeof (dwc_otg_qh_t));
/* Initialize QH */
switch (usb_pipetype(_urb->pipe)) {
case PIPE_CONTROL:
_qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
break;
case PIPE_BULK:
_qh->ep_type = USB_ENDPOINT_XFER_BULK;
break;
case PIPE_ISOCHRONOUS:
_qh->ep_type = USB_ENDPOINT_XFER_ISOC;
break;
case PIPE_INTERRUPT:
_qh->ep_type = USB_ENDPOINT_XFER_INT;
break;
}
_qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
_qh->data_toggle = DWC_OTG_HC_PID_DATA0;
_qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
INIT_LIST_HEAD(&_qh->qtd_list);
INIT_LIST_HEAD(&_qh->qh_list_entry);
_qh->channel = NULL;
/* FS/LS Enpoint on HS Hub
* NOT virtual root hub */
_qh->do_split = 0;
_qh->speed = _urb->dev->speed;
if (((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)) &&
(_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) {
DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
_urb->dev->ttport);
_qh->do_split = 1;
}
if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
_qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
/* Compute scheduling parameters once and save them. */
hprt0_data_t hprt;
/** @todo Account for split transfers in the bus time. */
int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
_qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed,
usb_pipein(_urb->pipe),
(_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount));
/* Start in a slightly future (micro)frame. */
_qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP);
_qh->interval = _urb->interval;
#if 0
/* Increase interrupt polling rate for debugging. */
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
_qh->interval = 8;
}
#endif
hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)))
{
_qh->interval *= 8;
_qh->sched_frame |= 0x7;
_qh->start_split_frame = _qh->sched_frame;
}
}
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
_urb->dev->devnum);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
usb_pipeendpoint(_urb->pipe),
usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
({ char *speed; switch (_urb->dev->speed) {
case USB_SPEED_LOW: speed = "low"; break;
case USB_SPEED_FULL: speed = "full"; break;
case USB_SPEED_HIGH: speed = "high"; break;
default: speed = "?"; break;
}; speed;}));
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
({ char *type; switch (_qh->ep_type) {
case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
default: type = "?"; break;
}; type;}));
#ifdef DEBUG
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
_qh->usecs);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
_qh->interval);
}
#endif
return;
}
/**
* Microframe scheduler
* track the total use in hcd->frame_usecs
* keep each qh use in qh->frame_usecs
* when surrendering the qh then donate the time back
*/
const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
/*
* called from dwc_otg_hcd.c:dwc_otg_hcd_init
*/
int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
{
int i;
for (i=0; i<8; i++) {
_hcd->frame_usecs[i] = max_uframe_usecs[i];
}
return 0;
}
static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int i;
unsigned short utime;
int t_left;
int ret;
int done;
ret = -1;
utime = _qh->usecs;
t_left = utime;
i = 0;
done = 0;
while (done == 0) {
/* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
if (utime <= _hcd->frame_usecs[i]) {
_hcd->frame_usecs[i] -= utime;
_qh->frame_usecs[i] += utime;
t_left -= utime;
ret = i;
done = 1;
return ret;
} else {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
}
}
return ret;
}
/*
* use this for FS apps that can span multiple uframes
*/
static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int i;
int j;
unsigned short utime;
int t_left;
int ret;
int done;
unsigned short xtime;
ret = -1;
utime = _qh->usecs;
t_left = utime;
i = 0;
done = 0;
loop:
while (done == 0) {
if(_hcd->frame_usecs[i] <= 0) {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
goto loop;
}
/*
* we need n consequtive slots
* so use j as a start slot j plus j+1 must be enough time (for now)
*/
xtime= _hcd->frame_usecs[i];
for (j = i+1 ; j < 8 ; j++ ) {
/*
* if we add this frame remaining time to xtime we may
* be OK, if not we need to test j for a complete frame
*/
if ((xtime+_hcd->frame_usecs[j]) < utime) {
if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
j = 8;
ret = -1;
continue;
}
}
if (xtime >= utime) {
ret = i;
j = 8; /* stop loop with a good value ret */
continue;
}
/* add the frame time to x time */
xtime += _hcd->frame_usecs[j];
/* we must have a fully available next frame or break */
if ((xtime < utime)
&& (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
ret = -1;
j = 8; /* stop loop with a bad value ret */
continue;
}
}
if (ret >= 0) {
t_left = utime;
for (j = i; (t_left>0) && (j < 8); j++ ) {
t_left -= _hcd->frame_usecs[j];
if ( t_left <= 0 ) {
_qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
_hcd->frame_usecs[j]= -t_left;
ret = i;
done = 1;
} else {
_qh->frame_usecs[j] += _hcd->frame_usecs[j];
_hcd->frame_usecs[j] = 0;
}
}
} else {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
}
}
return ret;
}
static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int ret;
ret = -1;
if (_qh->speed == USB_SPEED_HIGH) {
/* if this is a hs transaction we need a full frame */
ret = find_single_uframe(_hcd, _qh);
} else {
/* if this is a fs transaction we may need a sequence of frames */
ret = find_multi_uframe(_hcd, _qh);
}
return ret;
}
/**
* Checks that the max transfer size allowed in a host channel is large enough
* to handle the maximum data transfer in a single (micro)frame for a periodic
* transfer.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for a periodic endpoint.
*
* @return 0 if successful, negative error code otherwise.
*/
static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int status;
uint32_t max_xfer_size;
uint32_t max_channel_xfer_size;
status = 0;
max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
if (max_xfer_size > max_channel_xfer_size) {
DWC_NOTICE("%s: Periodic xfer length %d > "
"max xfer length for channel %d\n",
__func__, max_xfer_size, max_channel_xfer_size);
status = -ENOSPC;
}
return status;
}
/**
* Schedules an interrupt or isochronous transfer in the periodic schedule.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for the periodic transfer. The QH should already contain the
* scheduling information.
*
* @return 0 if successful, negative error code otherwise.
*/
static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int status = 0;
int frame;
status = find_uframe(_hcd, _qh);
frame = -1;
if (status == 0) {
frame = 7;
} else {
if (status > 0 )
frame = status-1;
}
/* Set the new frame up */
if (frame > -1) {
_qh->sched_frame &= ~0x7;
_qh->sched_frame |= (frame & 7);
}
if (status != -1 )
status = 0;
if (status) {
DWC_NOTICE("%s: Insufficient periodic bandwidth for "
"periodic transfer.\n", __func__);
return status;
}
status = check_max_xfer_size(_hcd, _qh);
if (status) {
DWC_NOTICE("%s: Channel max transfer size too small "
"for periodic transfer.\n", __func__);
return status;
}
/* Always start in the inactive schedule. */
list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
/* Update claimed usecs per (micro)frame. */
_hcd->periodic_usecs += _qh->usecs;
/* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
} else {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
}
return status;
}
/**
* This function adds a QH to either the non periodic or periodic schedule if
* it is not already in the schedule. If the QH is already in the schedule, no
* action is taken.
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
unsigned long flags;
int status = 0;
local_irq_save(flags);
if (!list_empty(&_qh->qh_list_entry)) {
/* QH already in a schedule. */
goto done;
}
/* Add the new QH to the appropriate schedule */
if (dwc_qh_is_non_per(_qh)) {
/* Always start in the inactive schedule. */
list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
} else {
status = schedule_periodic(_hcd, _qh);
}
done:
local_irq_restore(flags);
return status;
}
/**
* This function adds a QH to the non periodic deferred schedule.
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
unsigned long flags;
local_irq_save(flags);
if (!list_empty(&_qh->qh_list_entry)) {
/* QH already in a schedule. */
goto done;
}
/* Add the new QH to the non periodic deferred schedule */
if (dwc_qh_is_non_per(_qh)) {
list_add_tail(&_qh->qh_list_entry,
&_hcd->non_periodic_sched_deferred);
}
done:
local_irq_restore(flags);
return 0;
}
/**
* Removes an interrupt or isochronous transfer from the periodic schedule.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for the periodic transfer.
*/
static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int i;
list_del_init(&_qh->qh_list_entry);
/* Update claimed usecs per (micro)frame. */
_hcd->periodic_usecs -= _qh->usecs;
for (i = 0; i < 8; i++) {
_hcd->frame_usecs[i] += _qh->frame_usecs[i];
_qh->frame_usecs[i] = 0;
}
/* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
} else {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
}
}
/**
* Removes a QH from either the non-periodic or periodic schedule. Memory is
* not freed.
*
* @param[in] _hcd The HCD state structure.
* @param[in] _qh QH to remove from schedule. */
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_qh->qh_list_entry)) {
/* QH is not in a schedule. */
goto done;
}
if (dwc_qh_is_non_per(_qh)) {
if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
_hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
}
list_del_init(&_qh->qh_list_entry);
} else {
deschedule_periodic(_hcd, _qh);
}
done:
local_irq_restore(flags);
}
/**
* Defers a QH. For non-periodic QHs, removes the QH from the active
* non-periodic schedule. The QH is added to the deferred non-periodic
* schedule if any QTDs are still attached to the QH.
*/
int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay)
{
int deact = 1;
unsigned long flags;
local_irq_save(flags);
if (dwc_qh_is_non_per(_qh)) {
_qh->sched_frame =
dwc_frame_num_inc(_hcd->frame_number,
delay);
_qh->channel = NULL;
_qh->qtd_in_process = NULL;
deact = 0;
dwc_otg_hcd_qh_remove(_hcd, _qh);
if (!list_empty(&_qh->qtd_list)) {
/* Add back to deferred non-periodic schedule. */
dwc_otg_hcd_qh_add_deferred(_hcd, _qh);
}
}
local_irq_restore(flags);
return deact;
}
/**
* Deactivates a QH. For non-periodic QHs, removes the QH from the active
* non-periodic schedule. The QH is added to the inactive non-periodic
* schedule if any QTDs are still attached to the QH.
*
* For periodic QHs, the QH is removed from the periodic queued schedule. If
* there are any QTDs still attached to the QH, the QH is added to either the
* periodic inactive schedule or the periodic ready schedule and its next
* scheduled frame is calculated. The QH is placed in the ready schedule if
* the scheduled frame has been reached already. Otherwise it's placed in the
* inactive schedule. If there are no QTDs attached to the QH, the QH is
* completely removed from the periodic schedule.
*/
void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
{
unsigned long flags;
local_irq_save(flags);
if (dwc_qh_is_non_per(_qh)) {
dwc_otg_hcd_qh_remove(_hcd, _qh);
if (!list_empty(&_qh->qtd_list)) {
/* Add back to inactive non-periodic schedule. */
dwc_otg_hcd_qh_add(_hcd, _qh);
}
} else {
uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
if (_qh->do_split) {
/* Schedule the next continuing periodic split transfer */
if (sched_next_periodic_split) {
_qh->sched_frame = frame_number;
if (dwc_frame_num_le(frame_number,
dwc_frame_num_inc(_qh->start_split_frame, 1))) {
/*
* Allow one frame to elapse after start
* split microframe before scheduling
* complete split, but DONT if we are
* doing the next start split in the
* same frame for an ISOC out.
*/
if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
_qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
}
}
} else {
_qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
_qh->interval);
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
_qh->sched_frame = frame_number;
}
_qh->sched_frame |= 0x7;
_qh->start_split_frame = _qh->sched_frame;
}
} else {
_qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
_qh->sched_frame = frame_number;
}
}
if (list_empty(&_qh->qtd_list)) {
dwc_otg_hcd_qh_remove(_hcd, _qh);
} else {
/*
* Remove from periodic_sched_queued and move to
* appropriate queue.
*/
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
list_move(&_qh->qh_list_entry,
&_hcd->periodic_sched_ready);
} else {
list_move(&_qh->qh_list_entry,
&_hcd->periodic_sched_inactive);
}
}
}
local_irq_restore(flags);
}
/**
* This function allocates and initializes a QTD.
*
* @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
* pointing to each other so each pair should have a unique correlation.
*
* @return Returns pointer to the newly allocated QTD, or NULL on error. */
dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
{
dwc_otg_qtd_t *qtd;
qtd = dwc_otg_hcd_qtd_alloc ();
if (qtd == NULL) {
return NULL;
}
dwc_otg_hcd_qtd_init (qtd, _urb);
return qtd;
}
/**
* Initializes a QTD structure.
*
* @param[in] _qtd The QTD to initialize.
* @param[in] _urb The URB to use for initialization. */
void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
{
memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
_qtd->urb = _urb;
if (usb_pipecontrol(_urb->pipe)) {
/*
* The only time the QTD data toggle is used is on the data
* phase of control transfers. This phase always starts with
* DATA1.
*/
_qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
_qtd->control_phase = DWC_OTG_CONTROL_SETUP;
}
/* start split */
_qtd->complete_split = 0;
_qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
_qtd->isoc_split_offset = 0;
/* Store the qtd ptr in the urb to reference what QTD. */
_urb->hcpriv = _qtd;
return;
}
/**
* This function adds a QTD to the QTD-list of a QH. It will find the correct
* QH to place the QTD into. If it does not find a QH, then it will create a
* new QH. If the QH to which the QTD is added is not currently scheduled, it
* is placed into the proper schedule based on its EP type.
*
* @param[in] _qtd The QTD to add
* @param[in] _dwc_otg_hcd The DWC HCD structure
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd)
{
struct usb_host_endpoint *ep;
dwc_otg_qh_t *qh;
unsigned long flags;
int retval = 0;
struct urb *urb = _qtd->urb;
local_irq_save(flags);
/*
* Get the QH which holds the QTD-list to insert to. Create QH if it
* doesn't exist.
*/
ep = dwc_urb_to_endpoint(urb);
qh = (dwc_otg_qh_t *)ep->hcpriv;
if (qh == NULL) {
qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
if (qh == NULL) {
retval = -1;
goto done;
}
ep->hcpriv = qh;
}
_qtd->qtd_qh_ptr = qh;
retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
if (retval == 0) {
list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
}
done:
local_irq_restore(flags);
return retval;
}
#endif /* DWC_DEVICE_ONLY */

103
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_ifx.c Normal file
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@@ -0,0 +1,103 @@
/******************************************************************************
**
** FILE NAME : dwc_otg_ifx.c
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 12 Auguest 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Platform specific initialization.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 Auguest 2007 Sung Winder Initiate Version
*******************************************************************************/
#include "dwc_otg_ifx.h"
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/gpio.h>
#include <asm/io.h>
//#include <asm/mach-ifxmips/ifxmips.h>
#include <lantiq_soc.h>
#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
#define writel ltq_w32
#define readl ltq_r32
void dwc_otg_power_on (void)
{
// clear power
writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
// set clock gating
if (ltq_is_ase())
writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR);
else
writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
// set power
writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);
writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR);
#if 1//defined (DWC_HOST_ONLY)
// make the hardware be a host controller (default)
//clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_HDSEL_BIT), DANUBE_RCU_UBSCFG);
//#elif defined (DWC_DEVICE_ONLY)
/* set the controller to the device mode */
// set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
#else
#error "For Danube/Twinpass, it should be HOST or Device Only."
#endif
// set the HC's byte-order to big-endian
//set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) | (1<<DANUBE_USBCFG_HOST_END_BIT), DANUBE_RCU_UBSCFG);
//clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_SLV_END_BIT), DANUBE_RCU_UBSCFG);
//writel(0x400, DANUBE_RCU_UBSCFG);
// PHY configurations.
writel (0x14014, (volatile unsigned long *)0xbe10103c);
}
int ifx_usb_hc_init(unsigned long base_addr, int irq)
{
return 0;
}
void ifx_usb_hc_remove(void)
{
}

85
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_ifx.h Normal file
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@@ -0,0 +1,85 @@
/******************************************************************************
**
** FILE NAME : dwc_otg_ifx.h
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 12 April 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Platform specific initialization.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 April 2007 Sung Winder Initiate Version
*******************************************************************************/
#if !defined(__DWC_OTG_IFX_H__)
#define __DWC_OTG_IFX_H__
#include <linux/irq.h>
#include <irq.h>
// 20070316, winder added.
#ifndef SZ_256K
#define SZ_256K 0x00040000
#endif
extern void dwc_otg_power_on (void);
/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */
// #include <asm/danube/danube.h>
// #include <asm/ifx/irq.h>
/* winder, I used the Danube parameter as default. *
* We could change this through module param. */
#define IFX_USB_IOMEM_BASE 0x1e101000
#define IFX_USB_IOMEM_SIZE SZ_256K
#define IFX_USB_IRQ LTQ_USB_INT
/**
* This function is called to set correct clock gating and power.
* For Twinpass/Danube board.
*/
#ifndef DANUBE_RCU_BASE_ADDR
#define DANUBE_RCU_BASE_ADDR (0xBF203000)
#endif
#ifndef DANUBE_CGU
#define DANUBE_CGU (0xBF103000)
#endif
#ifndef DANUBE_CGU_IFCCR
/***CGU Interface Clock Control Register***/
#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
#endif
#ifndef DANUBE_PMU
#define DANUBE_PMU (KSEG1+0x1F102000)
#endif
#ifndef DANUBE_PMU_PWDCR
/* PMU Power down Control Register */
#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C))
#endif
#define DANUBE_RCU_UBSCFG ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18))
#define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device
#define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end
#define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end
extern void ltq_mask_and_ack_irq(struct irq_data *d);
static void inline mask_and_ack_ifx_irq(int x)
{
struct irq_data d;
d.irq = x;
ltq_mask_and_ack_irq(&d);
}
#endif //__DWC_OTG_IFX_H__

269
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_plat.h Normal file
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@@ -0,0 +1,269 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/platform/dwc_otg_plat.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510301 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_PLAT_H__)
#define __DWC_OTG_PLAT_H__
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <asm/io.h>
/**
* @file
*
* This file contains the Platform Specific constants, interfaces
* (functions and macros) for Linux.
*
*/
/*#if !defined(__LINUX__)
#error "The contents of this file is Linux specific!!!"
#endif
*/
#include <lantiq_soc.h>
#define writel ltq_w32
#define readl ltq_r32
/**
* Reads the content of a register.
*
* @param _reg address of register to read.
* @return contents of the register.
*
* Usage:<br>
* <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
*/
static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg)
{
return readl(_reg);
};
/**
* Writes a register with a 32 bit value.
*
* @param _reg address of register to read.
* @param _value to write to _reg.
*
* Usage:<br>
* <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
*/
static __inline__ void dwc_write_reg32( volatile uint32_t *_reg, const uint32_t _value)
{
writel( _value, _reg );
};
/**
* This function modifies bit values in a register. Using the
* algorithm: (reg_contents & ~clear_mask) | set_mask.
*
* @param _reg address of register to read.
* @param _clear_mask bit mask to be cleared.
* @param _set_mask bit mask to be set.
*
* Usage:<br>
* <code> // Clear the SOF Interrupt Mask bit and <br>
* // set the OTG Interrupt mask bit, leaving all others as they were.
* dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
*/
static __inline__
void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
{
writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg );
};
/**
* Wrapper for the OS micro-second delay function.
* @param[in] _usecs Microseconds of delay
*/
static __inline__ void UDELAY( const uint32_t _usecs )
{
udelay( _usecs );
}
/**
* Wrapper for the OS milli-second delay function.
* @param[in] _msecs milliseconds of delay
*/
static __inline__ void MDELAY( const uint32_t _msecs )
{
mdelay( _msecs );
}
/**
* Wrapper for the Linux spin_lock. On the ARM (Integrator)
* spin_lock() is a nop.
*
* @param _lock Pointer to the spinlock.
*/
static __inline__ void SPIN_LOCK( spinlock_t *_lock )
{
spin_lock(_lock);
}
/**
* Wrapper for the Linux spin_unlock. On the ARM (Integrator)
* spin_lock() is a nop.
*
* @param _lock Pointer to the spinlock.
*/
static __inline__ void SPIN_UNLOCK( spinlock_t *_lock )
{
spin_unlock(_lock);
}
/**
* Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM
* (Integrator) spin_lock() is a nop.
*
* @param _l Pointer to the spinlock.
* @param _f unsigned long for irq flags storage.
*/
#define SPIN_LOCK_IRQSAVE( _l, _f ) { \
spin_lock_irqsave(_l,_f); \
}
/**
* Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM
* (Integrator) spin_lock() is a nop.
*
* @param _l Pointer to the spinlock.
* @param _f unsigned long for irq flags storage.
*/
#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) {\
spin_unlock_irqrestore(_l,_f); \
}
/*
* Debugging support vanishes in non-debug builds.
*/
/**
* The Debug Level bit-mask variable.
*/
extern uint32_t g_dbg_lvl;
/**
* Set the Debug Level variable.
*/
static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new )
{
uint32_t old = g_dbg_lvl;
g_dbg_lvl = _new;
return old;
}
/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
#define DBG_CIL (0x2)
/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
* messages */
#define DBG_CILV (0x20)
/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
* messages */
#define DBG_PCD (0x4)
/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
* messages */
#define DBG_PCDV (0x40)
/** When debug level has the DBG_HCD bit set, display Host debug messages */
#define DBG_HCD (0x8)
/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
* messages */
#define DBG_HCDV (0x80)
/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
* mode. */
#define DBG_HCD_URB (0x800)
/** When debug level has any bit set, display debug messages */
#define DBG_ANY (0xFF)
/** All debug messages off */
#define DBG_OFF 0
/** Prefix string for DWC_DEBUG print macros. */
#define USB_DWC "DWC_otg: "
/**
* Print a debug message when the Global debug level variable contains
* the bit defined in <code>lvl</code>.
*
* @param[in] lvl - Debug level, use one of the DBG_ constants above.
* @param[in] x - like printf
*
* Example:<p>
* <code>
* DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
* </code>
* <br>
* results in:<br>
* <code>
* usb-DWC_otg: dwc_otg_cil_init(ca867000)
* </code>
*/
#ifdef DEBUG
# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
#else
# define DWC_DEBUGPL(lvl, x...) do{}while(0)
# define DWC_DEBUGP(x...)
# define CHK_DEBUG_LEVEL(level) (0)
#endif /*DEBUG*/
/**
* Print an Error message.
*/
#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
/**
* Print a Warning message.
*/
#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
/**
* Print a notice (normal but significant message).
*/
#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
/**
* Basic message printing.
*/
#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
#endif

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target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/Kconfig Normal file
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config USB_HOST_IFX
tristate "Infineon USB Host Controller Driver"
depends on USB
default n
help
Infineon USB Host Controller
config USB_HOST_IFX_B
bool "USB host mode on core 1 and 2"
depends on USB_HOST_IFX
help
Both cores run as host
#config USB_HOST_IFX_1
#config USB_HOST_IFX_2
#config IFX_DANUBE
#config IFX_AMAZON_SE
config IFX_AR9
depends on USB_HOST_IFX
bool "AR9"
config IFX_VR9
depends on USB_HOST_IFX
bool "VR9"
#config USB_HOST_IFX_FORCE_USB11
# bool "Forced USB1.1"
# depends on USB_HOST_IFX
# default n
# help
# force to be USB 1.1
#config USB_HOST_IFX_WITH_HS_ELECT_TST
# bool "With HS_Electrical Test"
# depends on USB_HOST_IFX
# default n
# help
# With USBIF HSET routines
#config USB_HOST_IFX_WITH_ISO
# bool "With ISO transfer"
# depends on USB_HOST_IFX
# default n
# help
# With USBIF ISO transfer
config USB_HOST_IFX_UNALIGNED_ADJ
bool "Adjust"
depends on USB_HOST_IFX
help
USB_HOST_IFX_UNALIGNED_ADJ
#config USB_HOST_IFX_UNALIGNED_CHK
#config USB_HOST_IFX_UNALIGNED_NONE

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#
# Makefile for USB Core files and filesystem
#
ifxusb_host-objs := ifxusb_driver.o
ifxusb_host-objs += ifxusb_ctl.o
ifxusb_host-objs += ifxusb_cif.o
ifxusb_host-objs += ifxusb_cif_h.o
ifxusb_host-objs += ifxhcd.o
ifxusb_host-objs += ifxhcd_es.o
ifxusb_host-objs += ifxhcd_intr.o
ifxusb_host-objs += ifxhcd_queue.o
ifeq ($(CONFIG_IFX_TWINPASS),y)
EXTRA_CFLAGS += -D__IS_TWINPASS__
endif
ifeq ($(CONFIG_IFX_DANUBE),y)
EXTRA_CFLAGS += -D__IS_DANUBE__
endif
ifeq ($(CONFIG_IFX_AMAZON_SE),y)
EXTRA_CFLAGS += -D__IS_AMAZON_SE__
endif
ifeq ($(CONFIG_IFX_AR9),y)
EXTRA_CFLAGS += -D__IS_AR9__
endif
ifeq ($(CONFIG_IFX_AMAZON_S),y)
EXTRA_CFLAGS += -D__IS_AR9__
endif
ifeq ($(CONFIG_IFX_VR9),y)
EXTRA_CFLAGS += -D__IS_VR9__
endif
ifeq ($(CONFIG_USB_HOST_IFX),y)
EXTRA_CFLAGS += -Dlinux -D__LINUX__
EXTRA_CFLAGS += -D__IS_HOST__
EXTRA_CFLAGS += -D__KERNEL__
endif
ifeq ($(CONFIG_USB_HOST_IFX),m)
EXTRA_CFLAGS += -Dlinux -D__LINUX__
EXTRA_CFLAGS += -D__IS_HOST__
EXTRA_CFLAGS += -D__KERNEL__
endif
ifeq ($(CONFIG_USB_DEBUG),y)
EXTRA_CFLAGS += -D__DEBUG__
EXTRA_CFLAGS += -D__ENABLE_DUMP__
endif
ifeq ($(CONFIG_USB_HOST_IFX_B),y)
EXTRA_CFLAGS += -D__IS_DUAL__
endif
ifeq ($(CONFIG_USB_HOST_IFX_1),y)
EXTRA_CFLAGS += -D__IS_FIRST__
endif
ifeq ($(CONFIG_USB_HOST_IFX_2),y)
EXTRA_CFLAGS += -D__IS_SECOND__
endif
ifeq ($(CONFIG_USB_HOST_IFX_FORCE_USB11),y)
EXTRA_CFLAGS += -D__FORCE_USB11__
endif
ifeq ($(CONFIG_USB_HOST_IFX_WITH_HS_ELECT_TST),y)
EXTRA_CFLAGS += -D__WITH_HS_ELECT_TST__
endif
ifeq ($(CONFIG_USB_HOST_IFX_WITH_ISO),y)
EXTRA_CFLAGS += -D__EN_ISOC__
endif
ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_ADJ),y)
EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_ADJ__
endif
ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_CHK),y)
EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_CHK__
endif
# EXTRA_CFLAGS += -D__DYN_SOF_INTR__
EXTRA_CFLAGS += -D__UEIP__
# EXTRA_CFLAGS += -D__EN_ISOC__
# EXTRA_CFLAGS += -D__EN_ISOC_SPLIT__
## 20110628 AVM/WK New flag for less SOF IRQs
EXTRA_CFLAGS += -D__USE_TIMER_4_SOF__
obj-$(CONFIG_USB_HOST_IFX) += ifxusb_host.o

171
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/TagHistory Normal file
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+----------------------------------------------------------------------+
| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.18-r240-non_musb_ar9_vr9-SOF_Timer_Fixed
| Erzeugt mit SVN-Tagger Version 3.74.
+----------------------------------------------------------------------+
FIX - Korrektur bei der SOF-Timer/IRQ Steuerung. (Bug in Tag 5.17)
FIX - Fehlerbehandlung an mehreren Stellen korrigiert bzw. eingebaut.
+----------------------------------------------------------------------+
| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.17-r237-non_musb_ar9_vr9-2_6_32_41_Kompatibel
| Erzeugt mit SVN-Tagger Version 3.73.
+----------------------------------------------------------------------+
FIX - Kompatiblität zum Update auf Kernel 2.6.32-41. Weiterhin für 28er geeignet.
ENH - Reduktion der Interrruptlast durch Nutzung eines hrtimers anstatt SOF-IRQ.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.16-r208-non_musb_ar9_vr9-20110421_Zero_Paket_Optimiert
| Erzeugt mit SVN-Tagger Version 3.66.
+----------------------------------------------------------------------+
FIX - VR9 / AR9 - Zero Packet. Optimierung korrigiert.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.15-r205-non_musb_ar9_vr9-20110421_Zero_Paket_WA_funktioniert
| Erzeugt mit SVN-Tagger Version 3.66.
+----------------------------------------------------------------------+
FIX - VR9 / AR9 - "Zero Packet" funktioniert nun wirklich. Letzter Tag hatte einen Bug.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.14-r202-non_musb_ar9_vr9-20110420_Zero_Paket_WA
| Erzeugt mit SVN-Tagger Version 3.66.
+----------------------------------------------------------------------+
FIX - VR9 / AR9 - Zero Packet Workaround: ZLP wird nun geschickt wenn URB_ZERO_PACKET aktiv ist.
Wird von LTE Altair Firmware benoetig.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.13-r199-non_musb_ar9_vr9-20110310_Init_Fix
| Erzeugt mit SVN-Tagger Version 3.64.
+----------------------------------------------------------------------+
FIX - VR9 / AR9 - Timing der Initialisierungsphase angepasst zum Kernel 2.6.28 mit UGW-4.3.1.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.12-r184-non_musb_ar9_vr9-20110118_Full_Speed_Fix
| Erzeugt mit SVN-Tagger Version 3.58.
+----------------------------------------------------------------------+
AR9/VR9 (3370,6840,7320):
Makefile - FIX - (Workaround) Debug Modus hilft gegen Enumerationsfehler bei Full Speed Drucker.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.11-r175-non_musb_ar9_vr9-20101220_VR9_2_Ports_DMA_Fix
| Erzeugt mit SVN-Tagger Version 3.58.
+----------------------------------------------------------------------+
FIX - VR9 - Workaround DMA Burst Size. Wenn beiden USB Ports benutzt werden, geht der USB Host nicht mehr.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.10-r169-non_musb_ar9_vr9-Fix_Spontan_Reboot
| Erzeugt mit SVN-Tagger Version 3.58.
+----------------------------------------------------------------------+
FIX - Endlosschleife führte zu einem spontanen Reboot.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.9-r166-non_musb_ar9_vr9-20101112_deferred_completion
| Erzeugt mit SVN-Tagger Version 3.58.
+----------------------------------------------------------------------+
ENH - Deferred URB Completion Mechanismus eingebaut. Nun ca. 10% schneller bei usb-storage.
FIX - PING Flow Control gefixt.
FIX - Channel Halt wird nun immer angerufen. (Split Transaction wurde nicht erfolgreich gestoppt).
FIX - Spinlock Benutzung verbessert. Mehr Stabilitaet.
CHG - Ubersetztungsoption __DEBUG__ ist nun abhaengig von CONFIG_USB_DEBUG
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.8-r149-non_musb_ar9_vr9-20100827_LTE_Interrupt_EP_Fix
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
AR9/VR9 - FIX - Interrupt Packets gingen verloren, wegen falschem Timing beim OddFrame Bit.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.7-r142-non_musb_ar9_vr9-20100728_Unaligned_Buf_Fix
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
FIX - "Unaligned Data" Flag wieder nach Transfer geloescht.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.6-r133-non_musb_ar9_vr9-20100714_Toggle_Datenverlust_Fix
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
TL5508 - Einige UMTS Modems funktionierten nicht korrekt an der 7320 (AR9).
FIX - USB Data Toggle des usbcore benutzen. Datenverlust nach EP-Halt.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.5-r130-non_musb_ar9_vr9-20100712_USB_Ports_abschaltbar
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
Power - Fix - Beide USB Port abschaltbar bei rmmod.
rmmod - FIX - URB_Dequeue funktionierte beim Entladen des Treibers nicht (mehrere Ursachen).
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.4-r126-non_musb_ar9_vr9-20100701_Lost_Interrupt_Workaround
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
FIX - Workaround wegen verpasstem Interrupt, bei Full-Speed Interrupt EP.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.3-r123-non_musb_ar9_vr9-20100630_UMTS_Fixes
| Erzeugt mit SVN-Tagger Version 3.57.
+----------------------------------------------------------------------+
FIX - Full-Speed Interrupt Endpoint hinter Hi-Speed Hub funktioniert nun (UMTS Modems)
FIX - usb_hcd_link_urb_from_ep API von USBCore muss benutzt werden.
FIX - Interrupt URBs nicht bei NAK completen.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.2-r114-non_musb_ar9_vr9-20100520_StickAndSurf_funktioniert
| Erzeugt mit SVN-Tagger Version 3.56.
+----------------------------------------------------------------------+
- Merge mit neuen LANTIQ Sourcen "3.0alpha B100312"
- Fix - Spin_lock eingebaut, Stick&Surf funktioniert nun
- DEP - CONFIG_USB_HOST_IFX_WITH_ISO wird nicht unterstuetzt: In der Kernel Config deaktivieren.
+----------------------------------------------------------------------+
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.1-r107-non_musb_ar9_vr9-20100505_IFXUSB_Host_mit_Energiemonitor
| Erzeugt mit SVN-Tagger Version 3.56.
+----------------------------------------------------------------------+
USB Host Treiber für AR9 und VR9
--------------------------------
FIX - Toggle Error nach STALL - Einfacher Workaround - Nun werden Massenspeicherpartitionen erkannt!
AVM_POWERMETER - USB Energiemonitor Support.
Bekanntes Problem: Stick and Surf funktioniert nur sporadisch, weil CONTROL_IRQ manchmal ausbleibt.

2523
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target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd.h Normal file
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/*****************************************************************************
** FILE NAME : ifxhcd.h
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : This file contains the structures, constants, and interfaces for
** the Host Contoller Driver (HCD).
**
** The Host Controller Driver (HCD) is responsible for translating requests
** from the USB Driver into the appropriate actions on the IFXUSB controller.
** It isolates the USBD from the specifics of the controller by providing an
** API to the USBD.
** FUNCTIONS :
** COMPILER : gcc
** REFERENCE : Synopsys DWC-OTG Driver 2.7
** COPYRIGHT :
** Version Control Section **
** $Author$
** $Date$
** $Revisions$
** $Log$ Revision history
*****************************************************************************/
/*!
\defgroup IFXUSB_HCD HCD Interface
\ingroup IFXUSB_DRIVER_V3
\brief The Host Controller Driver (HCD) is responsible for translating requests
from the USB Driver into the appropriate actions on the IFXUSB controller.
It isolates the USBD from the specifics of the controller by providing an
API to the USBD.
*/
/*!
\file ifxhcd.h
\ingroup IFXUSB_DRIVER_V3
\brief This file contains the structures, constants, and interfaces for
the Host Contoller Driver (HCD).
*/
#if !defined(__IFXHCD_H__)
#define __IFXHCD_H__
#include <linux/list.h>
#include <linux/usb.h>
#ifdef __USE_TIMER_4_SOF__
#include <linux/hrtimer.h>
#endif
#include <linux/usb/hcd.h>
#include "ifxusb_cif.h"
#include "ifxusb_plat.h"
/*!
\addtogroup IFXUSB_HCD
*/
/*@{*/
/* Phases for control transfers.*/
typedef enum ifxhcd_control_phase {
IFXHCD_CONTROL_SETUP,
IFXHCD_CONTROL_DATA,
IFXHCD_CONTROL_STATUS
} ifxhcd_control_phase_e;
/* Reasons for halting a host channel. */
typedef enum ifxhcd_halt_status
{
HC_XFER_NO_HALT_STATUS, // Initial
HC_XFER_COMPLETE, // Xact complete without error, upward
HC_XFER_URB_COMPLETE, // Xfer complete without error, short upward
HC_XFER_STALL, // HC stopped abnormally, upward/downward
HC_XFER_XACT_ERR, // HC stopped abnormally, upward
HC_XFER_FRAME_OVERRUN, // HC stopped abnormally, upward
HC_XFER_BABBLE_ERR, // HC stopped abnormally, upward
HC_XFER_AHB_ERR, // HC stopped abnormally, upward
HC_XFER_DATA_TOGGLE_ERR,
HC_XFER_URB_DEQUEUE, // HC stopper manually, downward
HC_XFER_NAK // HC stopped by nak monitor, downward
} ifxhcd_halt_status_e;
struct ifxhcd_urbd;
struct ifxhcd_hc ;
struct ifxhcd_epqh ;
struct ifxhcd_hcd;
/*!
\brief A URB Descriptor (URBD) holds the state of a bulk, control,
interrupt, or isochronous transfer. A single URBD is created for each URB
(of one of these types) submitted to the HCD. The transfer associated with
a URBD may require one or multiple transactions.
A URBD is linked to a EP Queue Head, which is entered in either the
isoc, intr or non-periodic schedule for execution. When a URBD is chosen for
execution, some or all of its transactions may be executed. After
execution, the state of the URBD is updated. The URBD may be retired if all
its transactions are complete or if an error occurred. Otherwise, it
remains in the schedule so more transactions can be executed later.
*/
typedef struct ifxhcd_urbd {
struct list_head urbd_list_entry; // Hook for EPQH->urbd_list and ifxhcd->urbd_complete_list
struct urb *urb; /*!< URB for this transfer */
//struct urb {
// struct list_head urb_list;
// struct list_head anchor_list;
// struct usb_anchor * anchor;
// struct usb_device * dev;
// struct usb_host_endpoint * ep;
// unsigned int pipe;
// int status;
// unsigned int transfer_flags;
// void * transfer_buffer;
// dma_addr_t transfer_dma;
// u32 transfer_buffer_length;
// u32 actual_length;
// unsigned char * setup_packet;
// dma_addr_t setup_dma;
// int start_frame;
// int number_of_packets;
// int interval;
// int error_count;
// void * context;
// usb_complete_t complete;
// struct usb_iso_packet_descriptor iso_frame_desc[0];
//};
//urb_list For use by current owner of the URB.
//anchor_list membership in the list of an anchor
//anchor to anchor URBs to a common mooring
//dev Identifies the USB device to perform the request.
//ep Points to the endpoint's data structure. Will
// eventually replace pipe.
//pipe Holds endpoint number, direction, type, and more.
// Create these values with the eight macros available; u
// sb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is
// "ctrl", "bulk", "int" or "iso". For example
// usb_sndbulkpipe or usb_rcvintpipe. Endpoint numbers
// range from zero to fifteen. Note that "in" endpoint two
// is a different endpoint (and pipe) from "out" endpoint
// two. The current configuration controls the existence,
// type, and maximum packet size of any given endpoint.
//status This is read in non-iso completion functions to get
// the status of the particular request. ISO requests
// only use it to tell whether the URB was unlinked;
// detailed status for each frame is in the fields of
// the iso_frame-desc.
//transfer_flags A variety of flags may be used to affect how URB
// submission, unlinking, or operation are handled.
// Different kinds of URB can use different flags.
// URB_SHORT_NOT_OK
// URB_ISO_ASAP
// URB_NO_TRANSFER_DMA_MAP
// URB_NO_SETUP_DMA_MAP
// URB_NO_FSBR
// URB_ZERO_PACKET
// URB_NO_INTERRUPT
//transfer_buffer This identifies the buffer to (or from) which the I/O
// request will be performed (unless URB_NO_TRANSFER_DMA_MAP
// is set). This buffer must be suitable for DMA; allocate it
// with kmalloc or equivalent. For transfers to "in"
// endpoints, contents of this buffer will be modified. This
// buffer is used for the data stage of control transfers.
//transfer_dma When transfer_flags includes URB_NO_TRANSFER_DMA_MAP, the
// device driver is saying that it provided this DMA address,
// which the host controller driver should use in preference
// to the transfer_buffer.
//transfer_buffer_length How big is transfer_buffer. The transfer may be broken
// up into chunks according to the current maximum packet size
// for the endpoint, which is a function of the configuration
// and is encoded in the pipe. When the length is zero, neither
// transfer_buffer nor transfer_dma is used.
//actual_length This is read in non-iso completion functions, and it tells
// how many bytes (out of transfer_buffer_length) were transferred.
// It will normally be the same as requested, unless either an error
// was reported or a short read was performed. The URB_SHORT_NOT_OK
// transfer flag may be used to make such short reads be reported
// as errors.
//setup_packet Only used for control transfers, this points to eight bytes of
// setup data. Control transfers always start by sending this data
// to the device. Then transfer_buffer is read or written, if needed.
//setup_dma For control transfers with URB_NO_SETUP_DMA_MAP set, the device
// driver has provided this DMA address for the setup packet. The
// host controller driver should use this in preference to setup_packet.
//start_frame Returns the initial frame for isochronous transfers.
//number_of_packets Lists the number of ISO transfer buffers.
//interval Specifies the polling interval for interrupt or isochronous transfers.
// The units are frames (milliseconds) for for full and low speed devices,
// and microframes (1/8 millisecond) for highspeed ones.
//error_count Returns the number of ISO transfers that reported errors.
//context For use in completion functions. This normally points to request-specific
// driver context.
//complete Completion handler. This URB is passed as the parameter to the completion
// function. The completion function may then do what it likes with the URB,
// including resubmitting or freeing it.
//iso_frame_desc[0] Used to provide arrays of ISO transfer buffers and to collect the transfer
// status for each buffer.
struct ifxhcd_epqh *epqh;
// Actual data portion, not SETUP or STATUS in case of CTRL XFER
// DMA adjusted
uint8_t *setup_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/
uint8_t *xfer_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/
uint32_t xfer_len; /*!< Total number of bytes to transfer in this xfer. */
unsigned is_in :1;
unsigned is_active:1;
// For ALL XFER
uint8_t error_count; /*!< Holds the number of bus errors that have occurred for a transaction
within this transfer.
*/
/*== AVM/BC 20101111 Needed for URB Complete List ==*/
int status;
// For ISOC XFER only
#ifdef __EN_ISOC__
int isoc_frame_index; /*!< Index of the next frame descriptor for an isochronous transfer. A
frame descriptor describes the buffer position and length of the
data to be transferred in the next scheduled (micro)frame of an
isochronous transfer. It also holds status for that transaction.
The frame index starts at 0.
*/
// For SPLITed ISOC XFER only
uint8_t isoc_split_pos; /*!< Position of the ISOC split on full/low speed */
uint16_t isoc_split_offset;/*!< Position of the ISOC split in the buffer for the current frame */
#endif
} ifxhcd_urbd_t;
/*!
\brief A EP Queue Head (EPQH) holds the static characteristics of an endpoint and
maintains a list of transfers (URBDs) for that endpoint. A EPQH structure may
be entered in either the isoc, intr or non-periodic schedule.
*/
typedef struct ifxhcd_epqh {
struct list_head epqh_list_entry; // Hook for EP Queues
struct list_head urbd_list; /*!< List of URBDs for this EPQH. */
struct ifxhcd_hc *hc; /*!< Host channel currently processing transfers for this EPQH. */
struct ifxhcd_urbd *urbd; /*!< URBD currently assigned to a host channel for this EPQH. */
struct usb_host_endpoint *sysep;
uint8_t ep_type; /*!< Endpoint type. One of the following values:
- IFXUSB_EP_TYPE_CTRL
- IFXUSB_EP_TYPE_ISOC
- IFXUSB_EP_TYPE_BULK
- IFXUSB_EP_TYPE_INTR
*/
uint16_t mps; /*!< wMaxPacketSize Field of Endpoint Descriptor. */
/* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/
/*uint8_t data_toggle;*/ /*!< Determines the PID of the next data packet
One of the following values:
- IFXHCD_HC_PID_DATA0
- IFXHCD_HC_PID_DATA1
*/
uint8_t is_active;
uint8_t pkt_count_limit;
#ifdef __EPQD_DESTROY_TIMEOUT__
struct timer_list destroy_timer;
#endif
uint16_t wait_for_sof;
uint8_t need_split; /*!< Full/low speed endpoint on high-speed hub requires split. */
uint16_t interval; /*!< Interval between transfers in (micro)frames. (for INTR)*/
uint16_t period_counter; /*!< Interval between transfers in (micro)frames. */
uint8_t period_do;
uint8_t aligned_checked;
#if defined(__UNALIGNED_BUFFER_ADJ__)
uint8_t using_aligned_setup;
uint8_t *aligned_setup;
uint8_t using_aligned_buf;
uint8_t *aligned_buf;
unsigned aligned_buf_len : 19;
#endif
uint8_t *dump_buf;
} ifxhcd_epqh_t;
#if defined(__HC_XFER_TIMEOUT__)
struct ifxusb_core_if;
struct ifxhcd_hc;
typedef struct hc_xfer_info
{
struct ifxusb_core_if *core_if;
struct ifxhcd_hc *hc;
} hc_xfer_info_t;
#endif //defined(__HC_XFER_TIMEOUT__)
/*!
\brief Host channel descriptor. This structure represents the state of a single
host channel when acting in host mode. It contains the data items needed to
transfer packets to an endpoint via a host channel.
*/
typedef struct ifxhcd_hc
{
struct list_head hc_list_entry ; // Hook to free hc
struct ifxhcd_epqh *epqh ; /*!< EP Queue Head for the transfer being processed by this channel. */
uint8_t hc_num ; /*!< Host channel number used for register address lookup */
uint8_t *xfer_buff ; /*!< Pointer to the entire transfer buffer. */
uint32_t xfer_count ; /*!< Number of bytes transferred so far. The offset of the begin of the buf */
uint32_t xfer_len ; /*!< Total number of bytes to transfer in this xfer. */
uint16_t start_pkt_count ; /*!< Packet count at start of transfer. Used to calculate the actual xfer size*/
ifxhcd_halt_status_e halt_status; /*!< Reason for halting the host channel. */
unsigned dev_addr : 7; /*!< Device to access */
unsigned ep_num : 4; /*!< EP to access */
unsigned is_in : 1; /*!< EP direction. 0: OUT, 1: IN */
unsigned speed : 2; /*!< EP speed. */
unsigned ep_type : 2; /*!< Endpoint type. */
unsigned mps :11; /*!< Max packet size in bytes */
unsigned data_pid_start : 2; /*!< PID for initial transaction. */
unsigned do_ping : 1; /*!< Set to 1 to indicate that a PING request should be issued on this
channel. If 0, process normally.
*/
unsigned xfer_started : 1; /*!< Flag to indicate whether the transfer has been started. Set to 1 if
it has been started, 0 otherwise.
*/
unsigned halting : 1; /*!< Set to 1 if the host channel has been halted, but the core is not
finished flushing queued requests. Otherwise 0.
*/
unsigned short_rw : 1; /*!< When Tx, means termination needed.
When Rx, indicate Short Read */
/* Split settings for the host channel */
unsigned split : 2; /*!< Split: 0-Non Split, 1-SSPLIT, 2&3 CSPLIT */
/*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/
unsigned nyet_count;
/* nak monitor */
unsigned nak_retry_r : 16;
unsigned nak_retry : 16;
#define nak_retry_max 40000
unsigned nak_countdown : 8;
unsigned nak_countdown_r: 8;
#define nak_countdown_max 1
uint16_t wait_for_sof;
ifxhcd_control_phase_e control_phase; /*!< Current phase for control transfers (Setup, Data, or Status). */
uint32_t ssplit_out_xfer_count; /*!< How many bytes transferred during SSPLIT OUT */
#ifdef __DEBUG__
uint32_t start_hcchar_val;
#endif
#ifdef __HC_XFER_TIMEOUT__
hc_xfer_info_t hc_xfer_info;
struct timer_list hc_xfer_timer;
#endif
uint32_t hcchar;
/* Split settings for the host channel */
uint8_t hub_addr; /*!< Address of high speed hub */
uint8_t port_addr; /*!< Port of the low/full speed device */
#ifdef __EN_ISOC__
uint8_t isoc_xact_pos; /*!< Split transaction position */
#endif
} ifxhcd_hc_t;
/*!
\brief This structure holds the state of the HCD, including the non-periodic and
periodic schedules.
*/
typedef struct ifxhcd_hcd
{
struct device *dev;
struct hc_driver hc_driver;
ifxusb_core_if_t core_if; /*!< Pointer to the core interface structure. */
struct usb_hcd *syshcd;
volatile union ifxhcd_internal_flags
{
uint32_t d32;
struct
{
unsigned port_connect_status_change : 1;
unsigned port_connect_status : 1;
unsigned port_reset_change : 1;
unsigned port_enable_change : 1;
unsigned port_suspend_change : 1;
unsigned port_over_current_change : 1;
unsigned reserved : 27;
} b;
} flags; /*!< Internal HCD Flags */
struct ifxhcd_hc ifxhc[MAX_EPS_CHANNELS]; /*!< Array of pointers to the host channel descriptors. Allows accessing
a host channel descriptor given the host channel number. This is
useful in interrupt handlers.
*/
struct list_head free_hc_list; /*!< Free host channels in the controller. This is a list of ifxhcd_hc_t items. */
uint8_t *status_buf; /*!< Buffer to use for any data received during the status phase of a
control transfer. Normally no data is transferred during the status
phase. This buffer is used as a bit bucket.
*/
#define IFXHCD_STATUS_BUF_SIZE 64
struct list_head epqh_np_active; // with URBD, with HC
struct list_head epqh_np_ready; // with URBD, No HC
struct list_head epqh_intr_active; // with URBD, with HC
struct list_head epqh_intr_ready; // with URBD, no pass, No HC
#ifdef __EN_ISOC__
struct list_head epqh_isoc_active; // with URBD, with HC
struct list_head epqh_isoc_ready; // with URBD, no pass, No HC
#endif
/*== AVM/BC 20101111 URB Complete List ==*/
struct list_head urbd_complete_list;
struct list_head epqh_stdby;
/* AVM/BC 20101111 flags removed */
//unsigned process_channels_in_use : 1;
//unsigned select_eps_in_use : 1;
struct tasklet_struct select_eps; /*!< Tasket to do a reset */
uint32_t lastframe;
spinlock_t lock;
#ifdef __USE_TIMER_4_SOF__
struct hrtimer hr_timer;
#endif
} ifxhcd_hcd_t;
/* Gets the ifxhcd_hcd from a struct usb_hcd */
static inline ifxhcd_hcd_t *syshcd_to_ifxhcd(struct usb_hcd *syshcd)
{
return (ifxhcd_hcd_t *)(syshcd->hcd_priv[0]);
}
/* Gets the struct usb_hcd that contains a ifxhcd_hcd_t. */
static inline struct usb_hcd *ifxhcd_to_syshcd(ifxhcd_hcd_t *ifxhcd)
{
return (struct usb_hcd *)(ifxhcd->syshcd);
}
/*! \brief HCD Create/Destroy Functions */
/*@{*/
extern int ifxhcd_init (ifxhcd_hcd_t *_ifxhcd);
extern void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd);
/*@}*/
/*! \brief Linux HC Driver API Functions */
/*@{*/
extern int ifxhcd_start(struct usb_hcd *hcd);
extern void ifxhcd_stop (struct usb_hcd *hcd);
extern int ifxhcd_get_frame_number(struct usb_hcd *hcd);
/*!
\brief This function does the setup for a data transfer for a host channel and
starts the transfer. May be called in either Slave mode or DMA mode. In
Slave mode, the caller must ensure that there is sufficient space in the
request queue and Tx Data FIFO.
For an OUT transfer in Slave mode, it loads a data packet into the
appropriate FIFO. If necessary, additional data packets will be loaded in
the Host ISR.
For an IN transfer in Slave mode, a data packet is requested. The data
packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
additional data packets are requested in the Host ISR.
For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
register along with a packet count of 1 and the channel is enabled. This
causes a single PING transaction to occur. Other fields in HCTSIZ are
simply set to 0 since no data transfer occurs in this case.
For a PING transfer in DMA mode, the HCTSIZ register is initialized with
all the information required to perform the subsequent data transfer. In
addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
controller performs the entire PING protocol, then starts the data
transfer.
@param _ifxhc Information needed to initialize the host channel. The xfer_len
value may be reduced to accommodate the max widths of the XferSize and
PktCnt fields in the HCTSIZn register. The multi_count value may be changed
to reflect the final xfer_len value.
*/
extern void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
//extern int ifxhcd_urb_enqueue(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep, struct urb *_urb, gfp_t mem_flags);
//extern int ifxhcd_urb_dequeue(struct usb_hcd *_syshcd, struct urb *_urb);
extern irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd);
int ifxhcd_urb_enqueue( struct usb_hcd *_syshcd,
/*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/
struct urb *_urb,
gfp_t _mem_flags);
int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd,
struct urb *_urb, int status /* Parameter neu in 2.6.28 */);
extern void ifxhcd_endpoint_disable(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep);
extern int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf);
extern int ifxhcd_hub_control( struct usb_hcd *_syshcd,
u16 _typeReq,
u16 _wValue,
u16 _wIndex,
char *_buf,
u16 _wLength);
/*@}*/
/*! \brief Transaction Execution Functions */
/*@{*/
extern void ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status);
/*@}*/
/*! \brief Deferred Transaction Execution Functions */
/*@{*/
/*== AVM/BC 20101111 URB Complete List ==*/
extern void defer_ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status);
/*!
\brief Clears the transfer state for a host channel. This function is normally
called after a transfer is done and the host channel is being released.
*/
extern void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
/*!
\brief Attempts to halt a host channel. This function should only be called in
Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
normal circumstances in DMA mode, the controller halts the channel when the
transfer is complete or a condition occurs that requires application
intervention.
In slave mode, checks for a free request queue entry, then sets the Channel
Enable and Channel Disable bits of the Host Channel Characteristics
register of the specified channel to intiate the halt. If there is no free
request queue entry, sets only the Channel Disable bit of the HCCHARn
register to flush requests for this channel. In the latter case, sets a
flag to indicate that the host channel needs to be halted when a request
queue slot is open.
In DMA mode, always sets the Channel Enable and Channel Disable bits of the
HCCHARn register. The controller ensures there is space in the request
queue before submitting the halt request.
Some time may elapse before the core flushes any posted requests for this
host channel and halts. The Channel Halted interrupt handler completes the
deactivation of the host channel.
*/
extern void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if,
ifxhcd_hc_t *_ifxhc,
ifxhcd_halt_status_e _halt_status);
/*!
\brief Prepares a host channel for transferring packets to/from a specific
endpoint. The HCCHARn register is set up with the characteristics specified
in _ifxhc. Host channel interrupts that may need to be serviced while this
transfer is in progress are enabled.
*/
extern void ifxhcd_hc_init(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
/*!
\brief This function is called to handle the disconnection of host port.
*/
int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd);
/*@}*/
/*! \brief Interrupt Handler Functions */
/*@{*/
extern irqreturn_t ifxhcd_oc_irq(int _irq, void *_dev);
extern int32_t ifxhcd_handle_oc_intr(ifxhcd_hcd_t *_ifxhcd);
extern int32_t ifxhcd_handle_intr (ifxhcd_hcd_t *_ifxhcd);
/*@}*/
/*! \brief Schedule Queue Functions */
/*@{*/
extern ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb);
extern void ifxhcd_epqh_free ( ifxhcd_epqh_t *_epqh);
extern void select_eps (ifxhcd_hcd_t *_ifxhcd);
extern void process_channels(ifxhcd_hcd_t *_ifxhcd);
extern void process_channels_sub(ifxhcd_hcd_t *_ifxhcd);
extern void complete_channel(ifxhcd_hcd_t *_ifxhcd, ifxhcd_hc_t *_ifxhc, ifxhcd_urbd_t *_urbd);
extern void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
extern void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
extern void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
extern void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh);
extern int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb);
/*@}*/
/*! \brief Gets the usb_host_endpoint associated with an URB. */
static inline struct usb_host_endpoint *ifxhcd_urb_to_endpoint(struct urb *_urb)
{
struct usb_device *dev = _urb->dev;
int ep_num = usb_pipeendpoint(_urb->pipe);
return (usb_pipein(_urb->pipe))?(dev->ep_in[ep_num]):(dev->ep_out[ep_num]);
}
/*!
* \brief Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
* qualified with its direction (possible 32 endpoints per device).
*/
#define ifxhcd_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
/* AVM/WK: not needed?
extern struct usb_device *usb_alloc_dev (struct usb_device *parent, struct usb_bus *, unsigned port);
extern int usb_add_hcd (struct usb_hcd *syshcd, unsigned int irqnum, unsigned long irqflags);
extern void usb_remove_hcd (struct usb_hcd *syshcd);
extern struct usb_hcd *usb_create_hcd (const struct hc_driver *driver, struct device *dev, char *bus_name);
extern void usb_hcd_giveback_urb (struct usb_hcd *syshcd, struct urb *urb);
extern void usb_put_hcd (struct usb_hcd *syshcd);
extern long usb_calc_bus_time (int speed, int is_input, int isoc, int bytecount);
*/
/** Internal Functions */
void ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd);
extern char *syserr(int errno);
/*@}*//*IFXUSB_HCD*/
#endif // __IFXHCD_H__

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@@ -0,0 +1,549 @@
/*****************************************************************************
** FILE NAME : ifxhcd_es.c
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : The file contain function to enable host mode USB-IF Electrical Test function.
*****************************************************************************/
/*!
\file ifxhcd_es.c
\ingroup IFXUSB_DRIVER_V3
\brief The file contain function to enable host mode USB-IF Electrical Test function.
*/
#include <linux/version.h>
#include "ifxusb_version.h"
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/dma-mapping.h>
#include "ifxusb_plat.h"
#include "ifxusb_regs.h"
#include "ifxusb_cif.h"
#include "ifxhcd.h"
#ifdef __WITH_HS_ELECT_TST__
/*
* Quick and dirty hack to implement the HS Electrical Test
* SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
*
* This code was copied from our userspace app "hset". It sends a
* Get Device Descriptor control sequence in two parts, first the
* Setup packet by itself, followed some time later by the In and
* Ack packets. Rather than trying to figure out how to add this
* functionality to the normal driver code, we just hijack the
* hardware, using these two function to drive the hardware
* directly.
*/
void do_setup(ifxusb_core_if_t *_core_if)
{
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0];
uint32_t *data_fifo = _core_if->data_fifo[0];
gint_data_t gintsts;
hctsiz_data_t hctsiz;
hcchar_data_t hcchar;
haint_data_t haint;
hcint_data_t hcint;
/* Enable HAINTs */
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
/* Enable HCINTs */
ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/*
* Send Setup packet (Get Device Descriptor)
*/
/* Make sure channel is disabled */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
if (hcchar.b.chen) {
//fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
hcchar.b.chdis = 1;
// hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
//sleep(1);
mdelay(1000);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//if (hcchar.b.chen) {
// fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
//}
}
/* Set HCTSIZ */
hctsiz.d32 = 0;
hctsiz.b.xfersize = 8;
hctsiz.b.pktcnt = 1;
hctsiz.b.pid = IFXUSB_HC_PID_SETUP;
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
/* Set HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
hcchar.b.epdir = 0;
hcchar.b.epnum = 0;
hcchar.b.mps = 8;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
/* Fill FIFO with Setup data for Get Device Descriptor */
ifxusb_wreg(data_fifo++, 0x01000680);
ifxusb_wreg(data_fifo++, 0x00080000);
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
/* Wait for host channel interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.hcintr == 0);
//fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
/* Disable HCINTs */
ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
/* Disable HAINTs */
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
}
void do_in_ack(ifxusb_core_if_t *_core_if)
{
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0];
uint32_t *data_fifo = _core_if->data_fifo[0];
gint_data_t gintsts;
hctsiz_data_t hctsiz;
hcchar_data_t hcchar;
haint_data_t haint;
hcint_data_t hcint;
grxsts_data_t grxsts;
/* Enable HAINTs */
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
/* Enable HCINTs */
ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/*
* Receive Control In packet
*/
/* Make sure channel is disabled */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
if (hcchar.b.chen) {
//fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
hcchar.b.chdis = 1;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
//sleep(1);
mdelay(1000);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//if (hcchar.b.chen) {
// fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
//}
}
/* Set HCTSIZ */
hctsiz.d32 = 0;
hctsiz.b.xfersize = 8;
hctsiz.b.pktcnt = 1;
hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
/* Set HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
hcchar.b.epdir = 1;
hcchar.b.epnum = 0;
hcchar.b.mps = 8;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
/* Wait for receive status queue interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.rxstsqlvl == 0);
//fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
/* Read RXSTS */
grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
/* Clear RXSTSQLVL in GINTSTS */
gintsts.d32 = 0;
gintsts.b.rxstsqlvl = 1;
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
switch (grxsts.hb.pktsts) {
case IFXUSB_HSTS_DATA_UPDT:
/* Read the data into the host buffer */
if (grxsts.hb.bcnt > 0) {
int i;
int word_count = (grxsts.hb.bcnt + 3) / 4;
for (i = 0; i < word_count; i++) {
(void)ifxusb_rreg(data_fifo++);
}
}
//fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.hb.bcnt);
break;
default:
//fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
break;
}
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
/* Wait for receive status queue interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.rxstsqlvl == 0);
//fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
/* Read RXSTS */
grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
/* Clear RXSTSQLVL in GINTSTS */
gintsts.d32 = 0;
gintsts.b.rxstsqlvl = 1;
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
switch (grxsts.hb.pktsts) {
case IFXUSB_HSTS_XFER_COMP:
break;
default:
//fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
break;
}
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
/* Wait for host channel interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.hcintr == 0);
//fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
// usleep(100000);
// mdelay(100);
mdelay(1);
/*
* Send handshake packet
*/
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Make sure channel is disabled */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
if (hcchar.b.chen) {
//fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
hcchar.b.chdis = 1;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
//sleep(1);
mdelay(1000);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//if (hcchar.b.chen) {
// fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
//}
}
/* Set HCTSIZ */
hctsiz.d32 = 0;
hctsiz.b.xfersize = 0;
hctsiz.b.pktcnt = 1;
hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
/* Set HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
hcchar.b.epdir = 0;
hcchar.b.epnum = 0;
hcchar.b.mps = 8;
hcchar.b.chen = 1;
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
/* Wait for host channel interrupt */
do {
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
} while (gintsts.b.hcintr == 0);
//fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
/* Disable HCINTs */
ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
/* Disable HAINTs */
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
/* Read HAINT */
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
/* Read HCINT */
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
/* Read HCCHAR */
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
/* Clear HCINT */
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
/* Clear HAINT */
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
/* Clear GINTSTS */
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
/* Read GINTSTS */
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
}
#endif //__WITH_HS_ELECT_TST__

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target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_intr.c Normal file
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target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_queue.c Normal file
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/*****************************************************************************
** FILE NAME : ifxhcd_queue.c
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : This file contains the functions to manage Queue Heads and Queue
** Transfer Descriptors.
*****************************************************************************/
/*!
\file ifxhcd_queue.c
\ingroup IFXUSB_DRIVER_V3
\brief This file contains the functions to manage Queue Heads and Queue
Transfer Descriptors.
*/
#include <linux/version.h>
#include "ifxusb_version.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include "ifxusb_plat.h"
#include "ifxusb_regs.h"
#include "ifxusb_cif.h"
#include "ifxhcd.h"
#ifdef __EPQD_DESTROY_TIMEOUT__
#define epqh_self_destroy_timeout 5
static void eqph_destroy_func(unsigned long _ptr)
{
ifxhcd_epqh_t *epqh=(ifxhcd_epqh_t *)_ptr;
if(epqh)
{
ifxhcd_epqh_free (epqh);
}
}
#endif
#define SCHEDULE_SLOP 10
/*!
\brief This function allocates and initializes a EPQH.
\param _ifxhcd The HCD state structure for the USB Host controller.
\param[in] _urb Holds the information about the device/endpoint that we need
to initialize the EPQH.
\return Returns pointer to the newly allocated EPQH, or NULL on error.
*/
ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb)
{
ifxhcd_epqh_t *epqh;
hprt0_data_t hprt0;
struct usb_host_endpoint *sysep = ifxhcd_urb_to_endpoint(_urb);
/* Allocate memory */
// epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_KERNEL);
epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_ATOMIC);
if(epqh == NULL)
return NULL;
memset (epqh, 0, sizeof (ifxhcd_epqh_t));
epqh->sysep=sysep;
/* Initialize EPQH */
switch (usb_pipetype(_urb->pipe))
{
case PIPE_CONTROL : epqh->ep_type = IFXUSB_EP_TYPE_CTRL; break;
case PIPE_BULK : epqh->ep_type = IFXUSB_EP_TYPE_BULK; break;
case PIPE_ISOCHRONOUS: epqh->ep_type = IFXUSB_EP_TYPE_ISOC; break;
case PIPE_INTERRUPT : epqh->ep_type = IFXUSB_EP_TYPE_INTR; break;
}
//epqh->data_toggle = IFXUSB_HC_PID_DATA0;
epqh->mps = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if);
INIT_LIST_HEAD(&epqh->urbd_list);
INIT_LIST_HEAD(&epqh->epqh_list_entry);
epqh->hc = NULL;
epqh->dump_buf = ifxusb_alloc_buf(epqh->mps, 0);
/* FS/LS Enpoint on HS Hub
* NOT virtual root hub */
epqh->need_split = 0;
epqh->pkt_count_limit=0;
if(epqh->ep_type == IFXUSB_EP_TYPE_BULK && !(usb_pipein(_urb->pipe)) )
epqh->pkt_count_limit=4;
if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED &&
((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)) &&
(_urb->dev->tt) && (_urb->dev->tt->hub->devnum != 1))
{
IFX_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
_urb->dev->ttport);
epqh->need_split = 1;
epqh->pkt_count_limit=1;
}
if (epqh->ep_type == IFXUSB_EP_TYPE_INTR ||
epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
{
/* Compute scheduling parameters once and save them. */
epqh->interval = _urb->interval;
if(epqh->need_split)
epqh->interval *= 8;
}
epqh->period_counter=0;
epqh->is_active=0;
#ifdef __EPQD_DESTROY_TIMEOUT__
/* Start a timer for this transfer. */
init_timer(&epqh->destroy_timer);
epqh->destroy_timer.function = eqph_destroy_func;
epqh->destroy_timer.data = (unsigned long)(epqh);
#endif
#ifdef __DEBUG__
IFX_DEBUGPL(DBG_HCD , "IFXUSB HCD EPQH Initialized\n");
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - epqh = %p\n", epqh);
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Device Address = %d EP %d, %s\n",
_urb->dev->devnum,
usb_pipeendpoint(_urb->pipe),
usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Speed = %s\n",
({ char *speed; switch (_urb->dev->speed) {
case USB_SPEED_LOW: speed = "low" ; break;
case USB_SPEED_FULL: speed = "full"; break;
case USB_SPEED_HIGH: speed = "high"; break;
default: speed = "?"; break;
}; speed;}));
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Type = %s\n",
({
char *type; switch (epqh->ep_type)
{
case IFXUSB_EP_TYPE_ISOC: type = "isochronous"; break;
case IFXUSB_EP_TYPE_INTR: type = "interrupt" ; break;
case IFXUSB_EP_TYPE_CTRL: type = "control" ; break;
case IFXUSB_EP_TYPE_BULK: type = "bulk" ; break;
default: type = "?"; break;
};
type;
}));
if (epqh->ep_type == IFXUSB_EP_TYPE_INTR)
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - interval = %d\n", epqh->interval);
#endif
return epqh;
}
/*!
\brief Free the EPQH. EPQH should already be removed from a list.
URBD list should already be empty if called from URB Dequeue.
\param[in] _epqh The EPQH to free.
*/
void ifxhcd_epqh_free (ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
if(_epqh->sysep) _epqh->sysep->hcpriv=NULL;
_epqh->sysep=NULL;
if(!_epqh)
return;
/* Free each QTD in the QTD list */
local_irq_save (flags);
if (!list_empty(&_epqh->urbd_list))
IFX_WARN("%s() invalid epqh state\n",__func__);
#if defined(__UNALIGNED_BUFFER_ADJ__)
if(_epqh->aligned_buf)
ifxusb_free_buf(_epqh->aligned_buf);
if(_epqh->aligned_setup)
ifxusb_free_buf(_epqh->aligned_setup);
#endif
if (!list_empty(&_epqh->epqh_list_entry))
list_del_init(&_epqh->epqh_list_entry);
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
#endif
if(_epqh->dump_buf)
ifxusb_free_buf(_epqh->dump_buf);
_epqh->dump_buf=0;
kfree (_epqh);
local_irq_restore (flags);
}
/*!
\brief This function adds a EPQH to
\return 0 if successful, negative error code otherwise.
*/
void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_epqh->epqh_list_entry))
{
#ifdef __EN_ISOC__
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
else
#endif
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
else
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
_epqh->is_active=0;
}
else if(!_epqh->is_active)
{
#ifdef __EN_ISOC__
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
else
#endif
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
else
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
}
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
#endif
local_irq_restore(flags);
}
void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_epqh->epqh_list_entry))
IFX_WARN("%s() invalid epqh state\n",__func__);
#ifdef __EN_ISOC__
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active);
else
#endif
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active);
else
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_active);
_epqh->is_active=1;
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
#endif
local_irq_restore(flags);
}
void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_epqh->urbd_list))
{
if(_epqh->ep_type == IFXUSB_EP_TYPE_ISOC || _epqh->ep_type == IFXUSB_EP_TYPE_INTR)
{
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_stdby);
}
else
{
list_del_init(&_epqh->epqh_list_entry);
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
_epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout);
add_timer(&_epqh->destroy_timer );
#endif
}
}
else
{
#ifdef __EN_ISOC__
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
else
#endif
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
else
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
}
_epqh->is_active=0;
local_irq_restore(flags);
}
void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh)
{
unsigned long flags;
if(_epqh->ep_type != IFXUSB_EP_TYPE_ISOC && _epqh->ep_type != IFXUSB_EP_TYPE_INTR)
return;
local_irq_save(flags);
if (list_empty(&_epqh->epqh_list_entry))
IFX_WARN("%s() invalid epqh state\n",__func__);
if (!list_empty(&_epqh->urbd_list))
IFX_WARN("%s() invalid epqh state(not empty)\n",__func__);
_epqh->is_active=0;
list_del_init(&_epqh->epqh_list_entry);
#ifdef __EPQD_DESTROY_TIMEOUT__
del_timer(&_epqh->destroy_timer);
_epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout);
add_timer(&_epqh->destroy_timer );
#endif
local_irq_restore(flags);
}
int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb)
{
ifxhcd_urbd_t *urbd;
struct usb_host_endpoint *sysep;
ifxhcd_epqh_t *epqh;
unsigned long flags;
/* == AVM/WK 20100714 retval correctly initialized ==*/
int retval = -ENOMEM;
/*== AVM/BC 20100630 - Spinlock ==*/
//local_irq_save(flags);
SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
// urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_KERNEL);
urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_ATOMIC);
if (urbd != NULL) /* Initializes a QTD structure.*/
{
retval = 0;
memset (urbd, 0, sizeof (ifxhcd_urbd_t));
sysep = ifxhcd_urb_to_endpoint(_urb);
epqh = (ifxhcd_epqh_t *)sysep->hcpriv;
if (epqh == NULL)
{
epqh = ifxhcd_epqh_create (_ifxhcd, _urb);
if (epqh == NULL)
{
retval = -ENOSPC;
kfree(urbd);
//local_irq_restore (flags);
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
return retval;
}
sysep->hcpriv = epqh;
}
INIT_LIST_HEAD(&urbd->urbd_list_entry);
/*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/
retval = usb_hcd_link_urb_to_ep(ifxhcd_to_syshcd(_ifxhcd), _urb);
if (unlikely(retval)){
kfree(urbd);
kfree(epqh);
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
return retval;
}
list_add_tail(&urbd->urbd_list_entry, &epqh->urbd_list);
urbd->urb = _urb;
_urb->hcpriv = urbd;
urbd->epqh=epqh;
urbd->is_in=usb_pipein(_urb->pipe) ? 1 : 0;;
urbd->xfer_len=_urb->transfer_buffer_length;
#define URB_NO_SETUP_DMA_MAP 0
if(urbd->xfer_len>0)
{
if(_urb->transfer_flags && URB_NO_TRANSFER_DMA_MAP)
urbd->xfer_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->transfer_dma));
else
urbd->xfer_buff = (uint8_t *) _urb->transfer_buffer;
}
if(epqh->ep_type == IFXUSB_EP_TYPE_CTRL)
{
if(_urb->transfer_flags && URB_NO_SETUP_DMA_MAP)
urbd->setup_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->setup_dma));
else
urbd->setup_buff = (uint8_t *) _urb->setup_packet;
}
}
//local_irq_restore (flags);
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
return retval;
}

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/*****************************************************************************
** FILE NAME : ifxusb_cif.h
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : The Core Interface provides basic services for accessing and
** managing the IFX USB hardware. These services are used by both the
** Host Controller Driver and the Peripheral Controller Driver.
** FUNCTIONS :
** COMPILER : gcc
** REFERENCE : IFX hardware ref handbook for each plateforms
** COPYRIGHT :
** Version Control Section **
** $Author$
** $Date$
** $Revisions$
** $Log$ Revision history
*****************************************************************************/
/*!
\defgroup IFXUSB_DRIVER_V3 IFX USB SS Project
\brief IFX USB subsystem V3.x
*/
/*!
\defgroup IFXUSB_CIF Core Interface APIs
\ingroup IFXUSB_DRIVER_V3
\brief The Core Interface provides basic services for accessing and
managing the IFXUSB hardware. These services are used by both the
Host Controller Driver and the Peripheral Controller Driver.
*/
/*!
\file ifxusb_cif.h
\ingroup IFXUSB_DRIVER_V3
\brief This file contains the interface to the IFX USB Core.
*/
#if !defined(__IFXUSB_CIF_H__)
#define __IFXUSB_CIF_H__
#include <linux/workqueue.h>
#include <linux/version.h>
#include <asm/param.h>
#include "ifxusb_plat.h"
#include "ifxusb_regs.h"
#ifdef __DEBUG__
#include "linux/timer.h"
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define IFXUSB_PARAM_SPEED_HIGH 0
#define IFXUSB_PARAM_SPEED_FULL 1
#define IFXUSB_EP_SPEED_LOW 0
#define IFXUSB_EP_SPEED_FULL 1
#define IFXUSB_EP_SPEED_HIGH 2
#define IFXUSB_EP_TYPE_CTRL 0
#define IFXUSB_EP_TYPE_ISOC 1
#define IFXUSB_EP_TYPE_BULK 2
#define IFXUSB_EP_TYPE_INTR 3
#define IFXUSB_HC_PID_DATA0 0
#define IFXUSB_HC_PID_DATA2 1
#define IFXUSB_HC_PID_DATA1 2
#define IFXUSB_HC_PID_MDATA 3
#define IFXUSB_HC_PID_SETUP 3
/*!
\addtogroup IFXUSB_CIF
*/
/*@{*/
/*!
\struct ifxusb_params
\brief IFXUSB Parameters structure.
This structure is used for both importing from insmod stage and run-time storage.
These parameters define how the IFXUSB controller should be configured.
*/
typedef struct ifxusb_params
{
int32_t dma_burst_size; /*!< The DMA Burst size (applicable only for Internal DMA
Mode). 0(for single), 1(incr), 4(incr4), 8(incr8) 16(incr16)
*/
/* Translate this to GAHBCFG values */
int32_t speed; /*!< Specifies the maximum speed of operation in host and device mode.
The actual speed depends on the speed of the attached device and
the value of phy_type. The actual speed depends on the speed of the
attached device.
0 - High Speed (default)
1 - Full Speed
*/
int32_t data_fifo_size; /*!< Total number of dwords in the data FIFO memory. This
memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
Tx FIFOs.
32 to 32768
*/
#ifdef __IS_DEVICE__
int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in device mode.
16 to 32768
*/
int32_t tx_fifo_size[MAX_EPS_CHANNELS]; /*!< Number of dwords in each of the Tx FIFOs in device mode.
4 to 768
*/
#ifdef __DED_FIFO__
int32_t thr_ctl; /*!< Threshold control on/off */
int32_t tx_thr_length; /*!< Threshold length for Tx */
int32_t rx_thr_length; /*!< Threshold length for Rx*/
#endif
#else //__IS_HOST__
int32_t host_channels; /*!< The number of host channel registers to use.
1 to 16
*/
int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in host mode.
16 to 32768
*/
int32_t nperio_tx_fifo_size;/*!< Number of dwords in the non-periodic Tx FIFO in host mode.
16 to 32768
*/
int32_t perio_tx_fifo_size; /*!< Number of dwords in the host periodic Tx FIFO.
16 to 32768
*/
#endif //__IS_HOST__
int32_t max_transfer_size; /*!< The maximum transfer size supported in bytes.
2047 to 65,535
*/
int32_t max_packet_count; /*!< The maximum number of packets in a transfer.
15 to 511 (default 511)
*/
int32_t phy_utmi_width; /*!< Specifies the UTMI+ Data Width.
8 or 16 bits (default 16)
*/
int32_t turn_around_time_hs; /*!< Specifies the Turn-Around time at HS*/
int32_t turn_around_time_fs; /*!< Specifies the Turn-Around time at FS*/
int32_t timeout_cal_hs; /*!< Specifies the Timeout_Calibration at HS*/
int32_t timeout_cal_fs; /*!< Specifies the Timeout_Calibration at FS*/
} ifxusb_params_t;
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/*!
\struct ifxusb_core_if
\brief The ifx_core_if structure contains information needed to manage
the IFX USB controller acting in either host or device mode. It
represents the programming view of the controller as a whole.
*/
typedef struct ifxusb_core_if
{
ifxusb_params_t params; /*!< Run-time Parameters */
uint8_t core_no; /*!< core number (used as id when multi-core case */
char *core_name; /*!< core name used for registration and informative purpose*/
int irq; /*!< irq number this core is hooked */
/*****************************************************************
* Structures and pointers to physical register interface.
*****************************************************************/
/** Core Global registers starting at offset 000h. */
ifxusb_core_global_regs_t *core_global_regs; /*!< pointer to Core Global Registers, offset at 000h */
/** Host-specific registers */
#ifdef __IS_HOST__
/** Host Global Registers starting at offset 400h.*/
ifxusb_host_global_regs_t *host_global_regs; /*!< pointer to Host Global Registers, offset at 400h */
#define IFXUSB_HOST_GLOBAL_REG_OFFSET 0x400
/** Host Port 0 Control and Status Register */
volatile uint32_t *hprt0; /*!< pointer to HPRT0 Registers, offset at 440h */
#define IFXUSB_HOST_PORT_REGS_OFFSET 0x440
/** Host Channel Specific Registers at offsets 500h-5FCh. */
ifxusb_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; /*!< pointer to Host-Channel n Registers, offset at 500h */
#define IFXUSB_HOST_CHAN_REGS_OFFSET 0x500
#define IFXUSB_CHAN_REGS_OFFSET 0x20
#endif
/** Device-specific registers */
#ifdef __IS_DEVICE__
/** Device Global Registers starting at offset 800h */
ifxusb_device_global_regs_t *dev_global_regs; /*!< pointer to Device Global Registers, offset at 800h */
#define IFXUSB_DEV_GLOBAL_REG_OFFSET 0x800
/** Device Logical IN Endpoint-Specific Registers 900h-AFCh */
ifxusb_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; /*!< pointer to Device IN-EP Registers, offset at 900h */
#define IFXUSB_DEV_IN_EP_REG_OFFSET 0x900
#define IFXUSB_EP_REG_OFFSET 0x20
/** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
ifxusb_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];/*!< pointer to Device OUT-EP Registers, offset at 900h */
#define IFXUSB_DEV_OUT_EP_REG_OFFSET 0xB00
#endif
/** Power and Clock Gating Control Register */
volatile uint32_t *pcgcctl; /*!< pointer to Power and Clock Gating Control Registers, offset at E00h */
#define IFXUSB_PCGCCTL_OFFSET 0xE00
/** Push/pop addresses for endpoints or host channels.*/
uint32_t *data_fifo[MAX_EPS_CHANNELS]; /*!< pointer to FIFO access windows, offset at 1000h */
#define IFXUSB_DATA_FIFO_OFFSET 0x1000
#define IFXUSB_DATA_FIFO_SIZE 0x1000
uint32_t *data_fifo_dbg; /*!< pointer to FIFO debug windows, offset at 1000h */
/** Hardware Configuration -- stored here for convenience.*/
hwcfg1_data_t hwcfg1; /*!< preserved Hardware Configuration 1 */
hwcfg2_data_t hwcfg2; /*!< preserved Hardware Configuration 2 */
hwcfg3_data_t hwcfg3; /*!< preserved Hardware Configuration 3 */
hwcfg4_data_t hwcfg4; /*!< preserved Hardware Configuration 3 */
uint32_t snpsid; /*!< preserved SNPSID */
/*****************************************************************
* Run-time informations.
*****************************************************************/
/* Set to 1 if the core PHY interface bits in USBCFG have been initialized. */
uint8_t phy_init_done; /*!< indicated PHY is initialized. */
#ifdef __IS_HOST__
uint8_t queuing_high_bandwidth; /*!< Host mode, Queueing High Bandwidth. */
#endif
} ifxusb_core_if_t;
/*@}*//*IFXUSB_CIF*/
/*!
\fn void *ifxusb_alloc_buf(size_t size, int clear)
\brief This function is called to allocate buffer of specified size.
The allocated buffer is mapped into DMA accessable address.
\param size Size in BYTE to be allocated
\param clear 0: don't do clear after buffer allocated, other: do clear to zero
\return 0/NULL: Fail; uncached pointer of allocated buffer
\ingroup IFXUSB_CIF
*/
extern void *ifxusb_alloc_buf(size_t size, int clear);
/*!
\fn void ifxusb_free_buf(void *vaddr)
\brief This function is called to free allocated buffer.
\param vaddr the uncached pointer of the buffer
\ingroup IFXUSB_CIF
*/
extern void ifxusb_free_buf(void *vaddr);
/*!
\fn int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
int _irq,
uint32_t _reg_base_addr,
uint32_t _fifo_base_addr,
uint32_t _fifo_dbg_addr)
\brief This function is called to initialize the IFXUSB CSR data
structures. The register addresses in the device and host
structures are initialized from the base address supplied by the
caller. The calling function must make the OS calls to get the
base address of the IFXUSB controller registers.
\param _core_if Pointer of core_if structure
\param _irq irq number
\param _reg_base_addr Base address of IFXUSB core registers
\param _fifo_base_addr Fifo base address
\param _fifo_dbg_addr Fifo debug address
\return 0: success;
\ingroup IFXUSB_CIF
*/
extern int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
int _irq,
uint32_t _reg_base_addr,
uint32_t _fifo_base_addr,
uint32_t _fifo_dbg_addr);
/*!
\fn void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if)
\brief This function free the mapped address in the IFXUSB CSR data structures.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if )
\brief This function enbles the controller's Global Interrupt in the AHB Config register.
\param _core_if Pointer of core_if structure
*/
extern void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if );
/*!
\fn void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if )
\brief This function disables the controller's Global Interrupt in the AHB Config register.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if );
/*!
\fn void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num )
\brief Flush a Tx FIFO.
\param _core_if Pointer of core_if structure
\param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO )
\ingroup IFXUSB_CIF
*/
extern void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num );
/*!
\fn void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if )
\brief Flush Rx FIFO.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if );
/*!
\fn void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if )
\brief Flush ALL Rx and Tx FIFO.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if );
/*!
\fn int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if)
\brief Do core a soft reset of the core. Be careful with this because it
resets all the internal state machines of the core.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if);
/*!
\brief Turn on the USB Core Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_power_on (ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_power_off (ifxusb_core_if_t *_core_if)
\brief Turn off the USB Core Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_power_off (ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if)
\brief Turn on the USB PHY Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if)
\brief Turn off the USB PHY Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_hard_reset(ifxusb_core_if_t *_core_if)
\brief Reset on the USB Core RCU
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_hard_reset(ifxusb_core_if_t *_core_if);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef __IS_HOST__
/*!
\fn void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
\brief This function initializes the IFXUSB controller registers for Host mode.
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
request queues.
\param _core_if Pointer of core_if structure
\param _params parameters to be set
\ingroup IFXUSB_CIF
*/
extern void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params);
/*!
\fn void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if)
\brief This function enables the Host mode interrupts.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if)
\brief This function disables the Host mode interrupts.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if);
#if defined(__IS_TWINPASS__)
extern void ifxusb_enable_afe_oc(void);
#endif
/*!
\fn void ifxusb_vbus_init(ifxusb_core_if_t *_core_if)
\brief This function init the VBUS control.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_vbus_init(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_vbus_free(ifxusb_core_if_t *_core_if)
\brief This function free the VBUS control.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_vbus_free(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_vbus_on(ifxusb_core_if_t *_core_if)
\brief Turn on the USB 5V VBus Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_vbus_on(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_vbus_off(ifxusb_core_if_t *_core_if)
\brief Turn off the USB 5V VBus Power
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_vbus_off(ifxusb_core_if_t *_core_if);
/*!
\fn int ifxusb_vbus(ifxusb_core_if_t *_core_if)
\brief Read Current VBus status
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern int ifxusb_vbus(ifxusb_core_if_t *_core_if);
#if defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
/*!
\fn void ifxusb_oc_int_on(void)
\brief Turn on the OC interrupt
\ingroup IFXUSB_CIF
*/
extern void ifxusb_oc_int_on(void);
/*!
\fn void ifxusb_oc_int_off(void)
\brief Turn off the OC interrupt
\ingroup IFXUSB_CIF
*/
extern void ifxusb_oc_int_off(void);
#endif //defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef __IS_DEVICE__
/*!
\fn void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if)
\brief This function enables the Device mode interrupts.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if);
/*!
\fn uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if)
\brief Gets the current USB frame number. This is the frame number from the last SOF packet.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in)
\brief Set the EP STALL.
\param _core_if Pointer of core_if structure
\param _epno EP number
\param _is_in 1: is IN transfer
\ingroup IFXUSB_CIF
*/
extern void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in);
/*!
\fn void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in)
\brief Set the EP STALL.
\param _core_if Pointer of core_if structure
\param _epno EP number
\param _ep_type EP Type
\ingroup IFXUSB_CIF
*/
extern void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in);
/*!
\fn void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
\brief This function initializes the IFXUSB controller registers for Device mode.
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
request queues.
This function validate the imported parameters and store the result in the CIF structure.
After
\param _core_if Pointer of core_if structure
\param _params structure of inported parameters
\ingroup IFXUSB_CIF
*/
extern void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params);
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#if defined(__GADGET_LED__) || defined(__HOST_LED__)
/*!
\fn void ifxusb_led_init(ifxusb_core_if_t *_core_if)
\brief This function init the LED control.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_led_init(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_led_free(ifxusb_core_if_t *_core_if)
\brief This function free the LED control.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_led_free(ifxusb_core_if_t *_core_if);
/*!
\fn void ifxusb_led(ifxusb_core_if_t *_core_if)
\brief This function trigger the LED access.
\param _core_if Pointer of core_if structure
\ingroup IFXUSB_CIF
*/
extern void ifxusb_led(ifxusb_core_if_t *_core_if);
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/* internal routines for debugging */
extern void ifxusb_dump_msg(const u8 *buf, unsigned int length);
extern void ifxusb_dump_spram(ifxusb_core_if_t *_core_if);
extern void ifxusb_dump_registers(ifxusb_core_if_t *_core_if);
extern void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
static inline uint32_t ifxusb_read_core_intr(ifxusb_core_if_t *_core_if)
{
return (ifxusb_rreg(&_core_if->core_global_regs->gintsts) &
(ifxusb_rreg(&_core_if->core_global_regs->gintmsk)
#ifdef __USE_TIMER_4_SOF__
| IFXUSB_SOF_INTR_MASK
#endif
));
}
static inline uint32_t ifxusb_read_otg_intr (ifxusb_core_if_t *_core_if)
{
return (ifxusb_rreg (&_core_if->core_global_regs->gotgint));
}
static inline uint32_t ifxusb_mode(ifxusb_core_if_t *_core_if)
{
return (ifxusb_rreg( &_core_if->core_global_regs->gintsts ) & 0x1);
}
static inline uint8_t ifxusb_is_device_mode(ifxusb_core_if_t *_core_if)
{
return (ifxusb_mode(_core_if) != 1);
}
static inline uint8_t ifxusb_is_host_mode(ifxusb_core_if_t *_core_if)
{
return (ifxusb_mode(_core_if) == 1);
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef __IS_HOST__
static inline uint32_t ifxusb_read_hprt0(ifxusb_core_if_t *_core_if)
{
hprt0_data_t hprt0;
hprt0.d32 = ifxusb_rreg(_core_if->hprt0);
hprt0.b.prtena = 0;
hprt0.b.prtconndet = 0;
hprt0.b.prtenchng = 0;
hprt0.b.prtovrcurrchng = 0;
return hprt0.d32;
}
static inline uint32_t ifxusb_read_host_all_channels_intr (ifxusb_core_if_t *_core_if)
{
return (ifxusb_rreg (&_core_if->host_global_regs->haint));
}
static inline uint32_t ifxusb_read_host_channel_intr (ifxusb_core_if_t *_core_if, int hc_num)
{
return (ifxusb_rreg (&_core_if->hc_regs[hc_num]->hcint));
}
#endif
#ifdef __IS_DEVICE__
static inline uint32_t ifxusb_read_dev_all_in_ep_intr(ifxusb_core_if_t *_core_if)
{
uint32_t v;
v = ifxusb_rreg(&_core_if->dev_global_regs->daint) &
ifxusb_rreg(&_core_if->dev_global_regs->daintmsk);
return (v & 0xffff);
}
static inline uint32_t ifxusb_read_dev_all_out_ep_intr(ifxusb_core_if_t *_core_if)
{
uint32_t v;
v = ifxusb_rreg(&_core_if->dev_global_regs->daint) &
ifxusb_rreg(&_core_if->dev_global_regs->daintmsk);
return ((v & 0xffff0000) >> 16);
}
static inline uint32_t ifxusb_read_dev_in_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num)
{
uint32_t v;
v = ifxusb_rreg(&_core_if->in_ep_regs[_ep_num]->diepint) &
ifxusb_rreg(&_core_if->dev_global_regs->diepmsk);
return v;
}
static inline uint32_t ifxusb_read_dev_out_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num)
{
uint32_t v;
v = ifxusb_rreg(&_core_if->out_ep_regs[_ep_num]->doepint) &
ifxusb_rreg(&_core_if->dev_global_regs->doepmsk);
return v;
}
#endif
extern void ifxusb_attr_create (void *_dev);
extern void ifxusb_attr_remove (void *_dev);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#endif // !defined(__IFXUSB_CIF_H__)

458
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif_d.c Normal file
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@@ -0,0 +1,458 @@
/*****************************************************************************
** FILE NAME : ifxusb_cif_d.c
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : The Core Interface provides basic services for accessing and
** managing the IFX USB hardware. These services are used by the
** Peripheral Controller Driver only.
*****************************************************************************/
/*!
\file ifxusb_cif_d.c
\ingroup IFXUSB_DRIVER_V3
\brief This file contains the interface to the IFX USB Core.
*/
#include <linux/version.h>
#include "ifxusb_version.h"
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#ifdef __DEBUG__
#include <linux/jiffies.h>
#endif
#include "ifxusb_plat.h"
#include "ifxusb_regs.h"
#include "ifxusb_cif.h"
#include "ifxpcd.h"
/*!
\brief Initializes the DevSpd field of the DCFG register depending on the PHY type
and the enumeration speed of the device.
\param _core_if Pointer of core_if structure
*/
void ifxusb_dev_init_spd(ifxusb_core_if_t *_core_if)
{
uint32_t val;
dcfg_data_t dcfg;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
if (_core_if->params.speed == IFXUSB_PARAM_SPEED_FULL)
/* High speed PHY running at full speed */
val = 0x1;
else
/* High speed PHY running at high speed and full speed*/
val = 0x0;
IFX_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
dcfg.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dcfg);
dcfg.b.devspd = val;
ifxusb_wreg(&_core_if->dev_global_regs->dcfg, dcfg.d32);
}
/*!
\brief This function enables the Device mode interrupts.
\param _core_if Pointer of core_if structure
*/
void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if)
{
gint_data_t intr_mask ={ .d32 = 0};
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__);
/* Clear any pending OTG Interrupts */
ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF);
/* Clear any pending interrupts */
ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF);
/* Enable the interrupts in the GINTMSK.*/
intr_mask.b.modemismatch = 1;
intr_mask.b.conidstschng = 1;
intr_mask.b.wkupintr = 1;
intr_mask.b.disconnect = 1;
intr_mask.b.usbsuspend = 1;
intr_mask.b.usbreset = 1;
intr_mask.b.enumdone = 1;
intr_mask.b.inepintr = 1;
intr_mask.b.outepintr = 1;
intr_mask.b.erlysuspend = 1;
#ifndef __DED_FIFO__
// intr_mask.b.epmismatch = 1;
#endif
ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk));
}
/*!
\brief Gets the current USB frame number. This is the frame number from the last SOF packet.
\param _core_if Pointer of core_if structure
*/
uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if)
{
dsts_data_t dsts;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
dsts.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dsts);
/* read current frame/microfreme number from DSTS register */
return dsts.b.soffn;
}
/*!
\brief Set the EP STALL.
*/
void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in)
{
depctl_data_t depctl;
volatile uint32_t *depctl_addr;
IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT"));
depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)):
(&(_core_if->out_ep_regs[_epno]->doepctl));
depctl.d32 = ifxusb_rreg(depctl_addr);
depctl.b.stall = 1;
if (_is_in && depctl.b.epena)
depctl.b.epdis = 1;
ifxusb_wreg(depctl_addr, depctl.d32);
IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr));
return;
}
/*!
\brief Clear the EP STALL.
*/
void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in)
{
depctl_data_t depctl;
volatile uint32_t *depctl_addr;
IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT"));
depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)):
(&(_core_if->out_ep_regs[_epno]->doepctl));
depctl.d32 = ifxusb_rreg(depctl_addr);
/* clear the stall bits */
depctl.b.stall = 0;
/*
* USB Spec 9.4.5: For endpoints using data toggle, regardless
* of whether an endpoint has the Halt feature set, a
* ClearFeature(ENDPOINT_HALT) request always results in the
* data toggle being reinitialized to DATA0.
*/
if (_ep_type == IFXUSB_EP_TYPE_INTR || _ep_type == IFXUSB_EP_TYPE_BULK)
depctl.b.setd0pid = 1; /* DATA0 */
ifxusb_wreg(depctl_addr, depctl.d32);
IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr));
return;
}
/*!
\brief This function initializes the IFXUSB controller registers for Device mode.
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
request queues.
\param _core_if Pointer of core_if structure
\param _params parameters to be set
*/
void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
{
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
gusbcfg_data_t usbcfg ={.d32 = 0};
gahbcfg_data_t ahbcfg ={.d32 = 0};
dcfg_data_t dcfg ={.d32 = 0};
grstctl_t resetctl ={.d32 = 0};
gotgctl_data_t gotgctl ={.d32 = 0};
uint32_t dir;
int i;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if);
/* Copy Params */
_core_if->params.dma_burst_size = _params->dma_burst_size;
_core_if->params.speed = _params->speed;
if(_params->max_transfer_size < 2048 || _params->max_transfer_size > ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1) )
_core_if->params.max_transfer_size = ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1);
else
_core_if->params.max_transfer_size = _params->max_transfer_size;
if(_params->max_packet_count < 16 || _params->max_packet_count > ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1) )
_core_if->params.max_packet_count= ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
else
_core_if->params.max_packet_count= _params->max_packet_count;
_core_if->params.phy_utmi_width = _params->phy_utmi_width;
_core_if->params.turn_around_time_hs = _params->turn_around_time_hs;
_core_if->params.turn_around_time_fs = _params->turn_around_time_fs;
_core_if->params.timeout_cal_hs = _params->timeout_cal_hs;
_core_if->params.timeout_cal_fs = _params->timeout_cal_fs;
#ifdef __DED_FIFO__
_core_if->params.thr_ctl = _params->thr_ctl;
_core_if->params.tx_thr_length = _params->tx_thr_length;
_core_if->params.rx_thr_length = _params->rx_thr_length;
#endif
/* Reset the Controller */
do
{
while(ifxusb_core_soft_reset( _core_if ))
ifxusb_hard_reset(_core_if);
} while (ifxusb_is_host_mode(_core_if));
usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
#if 0
#if defined(__DED_FIFO__)
usbcfg.b.ForceDevMode = 1;
usbcfg.b.ForceHstMode = 0;
#endif
#endif
usbcfg.b.term_sel_dl_pulse = 0;
ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32);
/* This programming sequence needs to happen in FS mode before any other
* programming occurs */
/* High speed PHY. */
if (!_core_if->phy_init_done)
{
_core_if->phy_init_done = 1;
/* HS PHY parameters. These parameters are preserved
* during soft reset so only program the first time. Do
* a soft reset immediately after setting phyif. */
usbcfg.b.ulpi_utmi_sel = 0; //UTMI+
usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0;
ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
/* Reset after setting the PHY parameters */
ifxusb_core_soft_reset( _core_if );
}
/* Program the GAHBCFG Register.*/
switch (_core_if->params.dma_burst_size)
{
case 0 :
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE;
break;
case 1 :
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR;
break;
case 4 :
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4;
break;
case 8 :
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8;
break;
case 16:
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16;
break;
}
ahbcfg.b.dmaenable = 1;
ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32);
/* Program the GUSBCFG register. */
usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg );
usbcfg.b.hnpcap = 0;
usbcfg.b.srpcap = 0;
ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
/* Restart the Phy Clock */
ifxusb_wreg(_core_if->pcgcctl, 0);
/* Device configuration register */
ifxusb_dev_init_spd(_core_if);
dcfg.d32 = ifxusb_rreg( &_core_if->dev_global_regs->dcfg);
dcfg.b.perfrint = IFXUSB_DCFG_FRAME_INTERVAL_80;
#if defined(__DED_FIFO__)
#if defined(__DESC_DMA__)
dcfg.b.descdma = 1;
#else
dcfg.b.descdma = 0;
#endif
#endif
ifxusb_wreg( &_core_if->dev_global_regs->dcfg, dcfg.d32 );
/* Configure data FIFO sizes */
_core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
_core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz);
IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size);
_core_if->params.tx_fifo_size[0]= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16;
#ifdef __DED_FIFO__
for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
_core_if->params.tx_fifo_size[i] =
ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]) >> 16;
#else
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
_core_if->params.tx_fifo_size[i+1] =
ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
#endif
#ifdef __DEBUG__
#ifdef __DED_FIFO__
for (i=0; i <= _core_if->hwcfg4.b.num_in_eps; i++)
IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i]);
#else
IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.tx_fifo_size[0]);
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i+1]);
#endif
#endif
{
fifosize_data_t txfifosize;
if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size)
_core_if->params.data_fifo_size = _params->data_fifo_size;
if(_params->rx_fifo_size >=0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size)
_core_if->params.rx_fifo_size = _params->rx_fifo_size;
if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size)
_core_if->params.rx_fifo_size = _core_if->params.data_fifo_size;
ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size);
for (i=0; i < MAX_EPS_CHANNELS; i++)
if(_params->tx_fifo_size[i] >=0 && _params->tx_fifo_size[i] < _core_if->params.tx_fifo_size[i])
_core_if->params.tx_fifo_size[i] = _params->tx_fifo_size[i];
txfifosize.b.startaddr = _core_if->params.rx_fifo_size;
#ifdef __DED_FIFO__
if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
_core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
{
if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i] > _core_if->params.data_fifo_size)
_core_if->params.tx_fifo_size[i]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
txfifosize.b.depth=_core_if->params.tx_fifo_size[i];
ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i-1], txfifosize.d32);
txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i];
}
#else
if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
_core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
{
if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i+1] > _core_if->params.data_fifo_size)
_core_if->params.tx_fifo_size[i+1]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
//txfifosize.b.depth=_core_if->params.tx_fifo_size[i+1];
ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i], txfifosize.d32);
txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i+1];
}
#endif
}
#ifdef __DEBUG__
{
fifosize_data_t fifosize;
IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X Sz=0x%06X\n", 0,ifxusb_rreg(&global_regs->grxfsiz));
#ifdef __DED_FIFO__
fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
IFX_DEBUGPL(DBG_CIL, " Tx[00] FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
{
fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]);
IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth);
}
#else
fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
{
fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]);
IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth);
}
#endif
}
#endif
/* Clear Host Set HNP Enable in the OTG Control Register */
gotgctl.b.hstsethnpen = 1;
ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0);
/* Flush the FIFOs */
ifxusb_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */
ifxusb_flush_rx_fifo(_core_if);
/* Flush the Learning Queue. */
resetctl.b.intknqflsh = 1;
ifxusb_wreg( &global_regs->grstctl, resetctl.d32);
/* Clear all pending Device Interrupts */
ifxusb_wreg( &_core_if->dev_global_regs->diepmsk , 0 );
ifxusb_wreg( &_core_if->dev_global_regs->doepmsk , 0 );
ifxusb_wreg( &_core_if->dev_global_regs->daint , 0xFFFFFFFF );
ifxusb_wreg( &_core_if->dev_global_regs->daintmsk, 0 );
dir=_core_if->hwcfg1.d32;
for (i=0; i <= _core_if->hwcfg2.b.num_dev_ep ; i++,dir>>=2)
{
depctl_data_t depctl;
if((dir&0x03)==0 || (dir&0x03) ==1)
{
depctl.d32 = ifxusb_rreg(&_core_if->in_ep_regs[i]->diepctl);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
depctl.d32 = 0;
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepctl, depctl.d32);
#ifndef __DESC_DMA__
ifxusb_wreg( &_core_if->in_ep_regs[i]->dieptsiz, 0);
#endif
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepdma, 0);
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepint, 0xFF);
}
if((dir&0x03)==0 || (dir&0x03) ==2)
{
depctl.d32 = ifxusb_rreg(&_core_if->out_ep_regs[i]->doepctl);
if (depctl.b.epena)
{
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
else
depctl.d32 = 0;
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepctl, depctl.d32);
#ifndef __DESC_DMA__
ifxusb_wreg( &_core_if->out_ep_regs[i]->doeptsiz, 0);
#endif
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepdma, 0);
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepint, 0xFF);
}
}
}

846
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif_h.c Normal file
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/*****************************************************************************
** FILE NAME : ifxusb_cif_h.c
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : The Core Interface provides basic services for accessing and
** managing the IFX USB hardware. These services are used by the
** Host Controller Driver only.
*****************************************************************************/
/*!
\file ifxusb_cif_h.c
\ingroup IFXUSB_DRIVER_V3
\brief This file contains the interface to the IFX USB Core.
*/
#include <linux/version.h>
#include "ifxusb_version.h"
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#ifdef __DEBUG__
#include <linux/jiffies.h>
#endif
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#if defined(__UEIP__)
// #include <asm/ifx/ifx_board.h>
#endif
//#include <asm/ifx/ifx_gpio.h>
#if defined(__UEIP__)
// #include <asm/ifx/ifx_led.h>
#endif
#include "ifxusb_plat.h"
#include "ifxusb_regs.h"
#include "ifxusb_cif.h"
#include "ifxhcd.h"
#if !defined(__UEIP__)
#undef __USING_LED_AS_GPIO__
#endif
/*!
\brief This function enables the Host mode interrupts.
\param _core_if Pointer of core_if structure
*/
void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if)
{
gint_data_t intr_mask ={ .d32 = 0};
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__);
/* Clear any pending OTG Interrupts */
ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF);
/* Clear any pending interrupts */
ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF);
/* Enable the interrupts in the GINTMSK.*/
/* Common interrupts */
intr_mask.b.modemismatch = 1;
intr_mask.b.conidstschng = 1;
intr_mask.b.wkupintr = 1;
intr_mask.b.disconnect = 1;
intr_mask.b.usbsuspend = 1;
/* Host interrupts */
intr_mask.b.sofintr = 1;
intr_mask.b.portintr = 1;
intr_mask.b.hcintr = 1;
ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk));
}
/*!
\brief This function disables the Host mode interrupts.
\param _core_if Pointer of core_if structure
*/
void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if)
{
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
IFX_DEBUGPL(DBG_CILV, "%s()\n", __func__);
#if 1
ifxusb_wreg( &global_regs->gintmsk, 0);
#else
/* Common interrupts */
{
gint_data_t intr_mask ={.d32 = 0};
intr_mask.b.modemismatch = 1;
intr_mask.b.rxstsqlvl = 1;
intr_mask.b.conidstschng = 1;
intr_mask.b.wkupintr = 1;
intr_mask.b.disconnect = 1;
intr_mask.b.usbsuspend = 1;
/* Host interrupts */
intr_mask.b.sofintr = 1;
intr_mask.b.portintr = 1;
intr_mask.b.hcintr = 1;
intr_mask.b.ptxfempty = 1;
intr_mask.b.nptxfempty = 1;
ifxusb_mreg(&global_regs->gintmsk, intr_mask.d32, 0);
}
#endif
}
/*!
\brief This function initializes the IFXUSB controller registers for Host mode.
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
request queues.
\param _core_if Pointer of core_if structure
\param _params parameters to be set
*/
void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
{
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
gusbcfg_data_t usbcfg ={.d32 = 0};
gahbcfg_data_t ahbcfg ={.d32 = 0};
gotgctl_data_t gotgctl ={.d32 = 0};
int i;
IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if);
/* Copy Params */
_core_if->params.dma_burst_size = _params->dma_burst_size;
_core_if->params.speed = _params->speed;
_core_if->params.max_transfer_size = _params->max_transfer_size;
_core_if->params.max_packet_count = _params->max_packet_count;
_core_if->params.phy_utmi_width = _params->phy_utmi_width;
_core_if->params.turn_around_time_hs = _params->turn_around_time_hs;
_core_if->params.turn_around_time_fs = _params->turn_around_time_fs;
_core_if->params.timeout_cal_hs = _params->timeout_cal_hs;
_core_if->params.timeout_cal_fs = _params->timeout_cal_fs;
/* Reset the Controller */
do
{
while(ifxusb_core_soft_reset( _core_if ))
ifxusb_hard_reset(_core_if);
} while (ifxusb_is_device_mode(_core_if));
usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
// usbcfg.b.ulpi_ext_vbus_drv = 1;
usbcfg.b.term_sel_dl_pulse = 0;
ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32);
/* This programming sequence needs to happen in FS mode before any other
* programming occurs */
/* High speed PHY. */
if (!_core_if->phy_init_done)
{
_core_if->phy_init_done = 1;
/* HS PHY parameters. These parameters are preserved
* during soft reset so only program the first time. Do
* a soft reset immediately after setting phyif. */
usbcfg.b.ulpi_utmi_sel = 0; //UTMI+
usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0;
ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
/* Reset after setting the PHY parameters */
ifxusb_core_soft_reset( _core_if );
}
usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
// usbcfg.b.ulpi_fsls = 0;
// usbcfg.b.ulpi_clk_sus_m = 0;
ifxusb_wreg(&global_regs->gusbcfg, usbcfg.d32);
/* Program the GAHBCFG Register.*/
switch (_core_if->params.dma_burst_size)
{
case 0 :
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE;
break;
case 1 :
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR;
break;
case 4 :
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4;
break;
case 8 :
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8;
break;
case 16:
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16;
break;
}
ahbcfg.b.dmaenable = 1;
ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32);
/* Program the GUSBCFG register. */
usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg );
usbcfg.b.hnpcap = 0;
usbcfg.b.srpcap = 0;
ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
/* Restart the Phy Clock */
ifxusb_wreg(_core_if->pcgcctl, 0);
/* Initialize Host Configuration Register */
{
hcfg_data_t hcfg;
hcfg.d32 = ifxusb_rreg(&_core_if->host_global_regs->hcfg);
hcfg.b.fslspclksel = IFXUSB_HCFG_30_60_MHZ;
if (_params->speed == IFXUSB_PARAM_SPEED_FULL)
hcfg.b.fslssupp = 1;
ifxusb_wreg(&_core_if->host_global_regs->hcfg, hcfg.d32);
}
_core_if->params.host_channels=(_core_if->hwcfg2.b.num_host_chan + 1);
if(_params->host_channels>0 && _params->host_channels < _core_if->params.host_channels)
_core_if->params.host_channels = _params->host_channels;
/* Configure data FIFO sizes */
_core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
_core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz);
_core_if->params.nperio_tx_fifo_size= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16;
_core_if->params.perio_tx_fifo_size = ifxusb_rreg(&global_regs->hptxfsiz) >> 16;
IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size);
IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.nperio_tx_fifo_size);
IFX_DEBUGPL(DBG_CIL, " PTx FIFO Size=0x%06X\n", _core_if->params.perio_tx_fifo_size);
{
fifosize_data_t txfifosize;
if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size)
_core_if->params.data_fifo_size = _params->data_fifo_size;
if( _params->rx_fifo_size >= 0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size)
_core_if->params.rx_fifo_size = _params->rx_fifo_size;
if( _params->nperio_tx_fifo_size >=0 && _params->nperio_tx_fifo_size < _core_if->params.nperio_tx_fifo_size)
_core_if->params.nperio_tx_fifo_size = _params->nperio_tx_fifo_size;
if( _params->perio_tx_fifo_size >=0 && _params->perio_tx_fifo_size < _core_if->params.perio_tx_fifo_size)
_core_if->params.perio_tx_fifo_size = _params->perio_tx_fifo_size;
if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size)
_core_if->params.rx_fifo_size = _core_if->params.data_fifo_size;
ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size);
txfifosize.b.startaddr = _core_if->params.rx_fifo_size;
if(txfifosize.b.startaddr + _core_if->params.nperio_tx_fifo_size > _core_if->params.data_fifo_size)
_core_if->params.nperio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr;
txfifosize.b.depth=_core_if->params.nperio_tx_fifo_size;
ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
txfifosize.b.startaddr += _core_if->params.nperio_tx_fifo_size;
if(txfifosize.b.startaddr + _core_if->params.perio_tx_fifo_size > _core_if->params.data_fifo_size)
_core_if->params.perio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr;
txfifosize.b.depth=_core_if->params.perio_tx_fifo_size;
ifxusb_wreg( &global_regs->hptxfsiz, txfifosize.d32);
txfifosize.b.startaddr += _core_if->params.perio_tx_fifo_size;
}
#ifdef __DEBUG__
{
fifosize_data_t fifosize;
IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
fifosize.d32=ifxusb_rreg(&global_regs->grxfsiz);
IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
fifosize.d32=ifxusb_rreg(&global_regs->hptxfsiz);
IFX_DEBUGPL(DBG_CIL, " PTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
}
#endif
/* Clear Host Set HNP Enable in the OTG Control Register */
gotgctl.b.hstsethnpen = 1;
ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0);
/* Flush the FIFOs */
ifxusb_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */
ifxusb_flush_rx_fifo(_core_if);
for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++)
{
hcchar_data_t hcchar;
hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
hcchar.b.chen = 0;
hcchar.b.chdis = 1;
hcchar.b.epdir = 0;
ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32);
}
/* Halt all channels to put them into a known state. */
for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++)
{
hcchar_data_t hcchar;
int count = 0;
hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
hcchar.b.chen = 1;
hcchar.b.chdis = 1;
hcchar.b.epdir = 0;
ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32);
IFX_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
do{
hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
if (++count > 1000)
{
IFX_ERROR("%s: Unable to clear halt on channel %d\n", __func__, i);
break;
}
} while (hcchar.b.chen);
}
}
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#if defined(__UEIP__)
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
int ifxusb_vbus_status =-1;
#endif
#if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
int ifxusb_vbus1_status =-1;
#endif
#if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
int ifxusb_vbus2_status =-1;
#endif
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
static void *g_usb_vbus_trigger = NULL;
#endif
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
static void *g_usb_vbus1_trigger = NULL;
#endif
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
static void *g_usb_vbus2_trigger = NULL;
#endif
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
int ifxusb_vbus_gpio_inited=0;
#endif
#else //defined(__UEIP__)
int ifxusb_vbus_gpio_inited=0;
#endif
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
void ifxusb_vbus_init(ifxusb_core_if_t *_core_if)
{
#if defined(__UEIP__)
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
if ( !g_usb_vbus_trigger )
{
ifx_led_trigger_register("USB_VBUS", &g_usb_vbus_trigger);
if ( g_usb_vbus_trigger != NULL )
{
struct ifx_led_trigger_attrib attrib = {0};
attrib.delay_on = 0;
attrib.delay_off = 0;
attrib.timeout = 0;
attrib.def_value = 0;
attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
IFX_DEBUGP("Reg USB power!!\n");
ifx_led_trigger_set_attrib(g_usb_vbus_trigger, &attrib);
ifxusb_vbus_status =0;
}
}
#endif
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
if(_core_if->core_no==0 && !g_usb_vbus1_trigger )
{
ifx_led_trigger_register("USB_VBUS1", &g_usb_vbus1_trigger);
if ( g_usb_vbus1_trigger != NULL )
{
struct ifx_led_trigger_attrib attrib = {0};
attrib.delay_on = 0;
attrib.delay_off = 0;
attrib.timeout = 0;
attrib.def_value = 0;
attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
IFX_DEBUGP("Reg USB1 power!!\n");
ifx_led_trigger_set_attrib(g_usb_vbus1_trigger, &attrib);
ifxusb_vbus1_status =0;
}
}
#endif
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
if(_core_if->core_no==1 && !g_usb_vbus2_trigger )
{
ifx_led_trigger_register("USB_VBUS2", &g_usb_vbus2_trigger);
if ( g_usb_vbus2_trigger != NULL )
{
struct ifx_led_trigger_attrib attrib = {0};
attrib.delay_on = 0;
attrib.delay_off = 0;
attrib.timeout = 0;
attrib.def_value = 0;
attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
IFX_DEBUGP("Reg USB2 power!!\n");
ifx_led_trigger_set_attrib(g_usb_vbus2_trigger, &attrib);
ifxusb_vbus2_status =0;
}
}
#endif
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
/* == 20100712 AVM/WK use gpio_inited as bitmask == */
if(ifxusb_vbus_gpio_inited == 0)
{
if(!ifx_gpio_register(IFX_GPIO_MODULE_USB))
{
IFX_DEBUGP("Register USB VBus through GPIO OK!!\n");
#ifdef IFX_GPIO_USB_VBUS
ifxusb_vbus_status =0;
#endif //IFX_GPIO_USB_VBUS
#ifdef IFX_GPIO_USB_VBUS1
ifxusb_vbus1_status=0;
#endif //IFX_GPIO_USB_VBUS1
#ifdef IFX_GPIO_USB_VBUS2
ifxusb_vbus2_status=0;
#endif //IFX_GPIO_USB_VBUS2
ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no);
}
else
IFX_PRINT("Register USB VBus Failed!!\n");
} else {
ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no);
}
#endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
#endif //defined(__UEIP__)
}
void ifxusb_vbus_free(ifxusb_core_if_t *_core_if)
{
#if defined(__UEIP__)
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
if ( g_usb_vbus_trigger )
{
ifx_led_trigger_deregister(g_usb_vbus_trigger);
g_usb_vbus_trigger = NULL;
ifxusb_vbus_status =-1;
}
#endif
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
if(_core_if->core_no==0 && g_usb_vbus1_trigger )
{
ifx_led_trigger_deregister(g_usb_vbus1_trigger);
g_usb_vbus1_trigger = NULL;
ifxusb_vbus1_status =-1;
}
#endif
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
if(_core_if->core_no==1 && g_usb_vbus2_trigger )
{
ifx_led_trigger_deregister(g_usb_vbus2_trigger);
g_usb_vbus2_trigger = NULL;
ifxusb_vbus2_status =-1;
}
#endif
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
/* == 20100712 AVM/WK use gpio_inited as bitmask == */
if((ifxusb_vbus_gpio_inited & (1<<_core_if->core_no)) == ifxusb_vbus_gpio_inited)
{
ifx_gpio_deregister(IFX_GPIO_MODULE_USB);
#ifdef IFX_GPIO_USB_VBUS
ifxusb_vbus_status =-1;
#endif //IFX_GPIO_USB_VBUS
#ifdef IFX_GPIO_USB_VBUS1
ifxusb_vbus1_status=-1;
#endif //IFX_GPIO_USB_VBUS1
#ifdef IFX_GPIO_USB_VBUS2
ifxusb_vbus2_status=-1;
#endif //IFX_GPIO_USB_VBUS2
}
ifxusb_vbus_gpio_inited &= ~(1<<_core_if->core_no);
#endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
#endif //defined(__UEIP__)
}
/*!
\brief Turn on the USB 5V VBus Power
\param _core_if Pointer of core_if structure
*/
void ifxusb_vbus_on(ifxusb_core_if_t *_core_if)
{
IFX_DEBUGP("SENDING VBus POWER UP\n");
#if defined(__UEIP__)
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
if ( g_usb_vbus_trigger && ifxusb_vbus_status==0)
{
ifx_led_trigger_activate(g_usb_vbus_trigger);
IFX_DEBUGP("Enable USB power!!\n");
ifxusb_vbus_status=1;
}
#endif
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==0)
{
ifx_led_trigger_activate(g_usb_vbus1_trigger);
IFX_DEBUGP("Enable USB1 power!!\n");
ifxusb_vbus1_status=1;
}
#endif
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==0)
{
ifx_led_trigger_activate(g_usb_vbus2_trigger);
IFX_DEBUGP("Enable USB2 power!!\n");
ifxusb_vbus2_status=1;
}
#endif
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
if(ifxusb_vbus_gpio_inited)
{
#if defined(IFX_GPIO_USB_VBUS)
if(ifxusb_vbus_status==0)
{
ifx_gpio_output_set(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB);
ifxusb_vbus_status=1;
}
#endif
#if defined(IFX_GPIO_USB_VBUS1)
if(_core_if->core_no==0 && ifxusb_vbus1_status==0)
{
ifx_gpio_output_set(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB);
ifxusb_vbus1_status=1;
}
#endif
#if defined(IFX_GPIO_USB_VBUS2)
if(_core_if->core_no==1 && ifxusb_vbus2_status==0)
{
ifx_gpio_output_set(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB);
ifxusb_vbus2_status=1;
}
#endif
}
#endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
#else
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
ifxusb_vbus_status=1;
//usb_set_vbus_on();
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
#if defined(__IS_AMAZON_SE__)
set_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT);
ifxusb_vbus_status=1;
#endif //defined(__IS_AMAZON_SE__)
#if defined(__IS_AR9__)
if(_core_if->core_no==0)
{
if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0)
{
IFX_PRINT("Can't enable USB1 5.5V power!!\n");
return;
}
bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB);
bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB);
bsp_port_set_dir_out(1, 13, PORT_MODULE_USB);
bsp_port_set_pudsel(1, 13, PORT_MODULE_USB);
bsp_port_set_puden(1, 13, PORT_MODULE_USB);
bsp_port_set_output(1, 13, PORT_MODULE_USB);
IFX_DEBUGP("Enable USB1 power!!\n");
ifxusb_vbus1_status=1;
}
else
{
if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0)
{
IFX_PRINT("Can't enable USB2 5.5V power!!\n");
return;
}
bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB);
bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB);
bsp_port_set_dir_out(3, 4, PORT_MODULE_USB);
bsp_port_set_pudsel(3, 4, PORT_MODULE_USB);
bsp_port_set_puden(3, 4, PORT_MODULE_USB);
bsp_port_set_output(3, 4, PORT_MODULE_USB);
IFX_DEBUGP("Enable USB2 power!!\n");
ifxusb_vbus2_status=1;
}
#endif //defined(__IS_AR9__)
#if defined(__IS_VR9__)
if(_core_if->core_no==0)
{
ifxusb_vbus1_status=1;
}
else
{
ifxusb_vbus2_status=1;
}
#endif //defined(__IS_VR9__)
#endif //defined(__UEIP__)
}
/*!
\brief Turn off the USB 5V VBus Power
\param _core_if Pointer of core_if structure
*/
void ifxusb_vbus_off(ifxusb_core_if_t *_core_if)
{
IFX_DEBUGP("SENDING VBus POWER OFF\n");
#if defined(__UEIP__)
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
if ( g_usb_vbus_trigger && ifxusb_vbus_status==1)
{
ifx_led_trigger_deactivate(g_usb_vbus_trigger);
IFX_DEBUGP("Disable USB power!!\n");
ifxusb_vbus_status=0;
}
#endif
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==1)
{
ifx_led_trigger_deactivate(g_usb_vbus1_trigger);
IFX_DEBUGP("Disable USB1 power!!\n");
ifxusb_vbus1_status=0;
}
#endif
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==1)
{
ifx_led_trigger_deactivate(g_usb_vbus2_trigger);
IFX_DEBUGP("Disable USB2 power!!\n");
ifxusb_vbus2_status=0;
}
#endif
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
if(ifxusb_vbus_gpio_inited)
{
#if defined(IFX_GPIO_USB_VBUS)
if(ifxusb_vbus_status==1)
{
ifx_gpio_output_clear(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB);
ifxusb_vbus_status=0;
}
#endif
#if defined(IFX_GPIO_USB_VBUS1)
if(_core_if->core_no==0 && ifxusb_vbus1_status==1)
{
ifx_gpio_output_clear(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB);
ifxusb_vbus1_status=0;
}
#endif
#if defined(IFX_GPIO_USB_VBUS2)
if(_core_if->core_no==1 && ifxusb_vbus2_status==1)
{
ifx_gpio_output_clear(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB);
ifxusb_vbus2_status=0;
}
#endif
}
#endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
#else
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
ifxusb_vbus_status=0;
//usb_set_vbus_on();
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
#if defined(__IS_AMAZON_SE__)
clear_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT);
ifxusb_vbus_status=0;
#endif //defined(__IS_AMAZON_SE__)
#if defined(__IS_AR9__)
if(_core_if->core_no==0)
{
if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) {
IFX_PRINT("Can't Disable USB1 5.5V power!!\n");
return;
}
bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB);
bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB);
bsp_port_set_dir_out(1, 13, PORT_MODULE_USB);
bsp_port_set_pudsel(1, 13, PORT_MODULE_USB);
bsp_port_set_puden(1, 13, PORT_MODULE_USB);
bsp_port_clear_output(1, 13, PORT_MODULE_USB);
IFX_DEBUGP("Disable USB1 power!!\n");
ifxusb_vbus1_status=0;
}
else
{
if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) {
IFX_PRINT("Can't Disable USB2 5.5V power!!\n");
return;
}
bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB);
bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB);
bsp_port_set_dir_out(3, 4, PORT_MODULE_USB);
bsp_port_set_pudsel(3, 4, PORT_MODULE_USB);
bsp_port_set_puden(3, 4, PORT_MODULE_USB);
bsp_port_clear_output(3, 4, PORT_MODULE_USB);
IFX_DEBUGP("Disable USB2 power!!\n");
ifxusb_vbus2_status=0;
}
#endif //defined(__IS_AR9__)
#if defined(__IS_VR9__)
if(_core_if->core_no==0)
{
ifxusb_vbus1_status=0;
}
else
{
ifxusb_vbus2_status=0;
}
#endif //defined(__IS_VR9__)
#endif //defined(__UEIP__)
}
/*!
\brief Read Current VBus status
\param _core_if Pointer of core_if structure
*/
int ifxusb_vbus(ifxusb_core_if_t *_core_if)
{
#if defined(__UEIP__)
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
return (ifxusb_vbus_status);
#endif
#if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
if(_core_if->core_no==0)
return (ifxusb_vbus1_status);
#endif
#if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
if(_core_if->core_no==1)
return (ifxusb_vbus2_status);
#endif
#else //defined(__UEIP__)
#endif
return -1;
}
#if defined(__UEIP__)
#else
#if defined(__IS_TWINPASS__)
#define ADSL_BASE 0x20000
#define CRI_BASE 0x31F00
#define CRI_CCR0 CRI_BASE + 0x00
#define CRI_CCR1 CRI_BASE + 0x01*4
#define CRI_CDC0 CRI_BASE + 0x02*4
#define CRI_CDC1 CRI_BASE + 0x03*4
#define CRI_RST CRI_BASE + 0x04*4
#define CRI_MASK0 CRI_BASE + 0x05*4
#define CRI_MASK1 CRI_BASE + 0x06*4
#define CRI_MASK2 CRI_BASE + 0x07*4
#define CRI_STATUS0 CRI_BASE + 0x08*4
#define CRI_STATUS1 CRI_BASE + 0x09*4
#define CRI_STATUS2 CRI_BASE + 0x0A*4
#define CRI_AMASK0 CRI_BASE + 0x0B*4
#define CRI_AMASK1 CRI_BASE + 0x0C*4
#define CRI_UPDCTL CRI_BASE + 0x0D*4
#define CRI_MADST CRI_BASE + 0x0E*4
// 0x0f is missing
#define CRI_EVENT0 CRI_BASE + 0x10*4
#define CRI_EVENT1 CRI_BASE + 0x11*4
#define CRI_EVENT2 CRI_BASE + 0x12*4
#define IRI_I_ENABLE 0x32000
#define STY_SMODE 0x3c004
#define AFE_TCR_0 0x3c0dc
#define AFE_ADDR_ADDR 0x3c0e8
#define AFE_RDATA_ADDR 0x3c0ec
#define AFE_WDATA_ADDR 0x3c0f0
#define AFE_CONFIG 0x3c0f4
#define AFE_SERIAL_CFG 0x3c0fc
#define DFE_BASE_ADDR 0xBE116000
//#define DFE_BASE_ADDR 0x9E116000
#define MEI_FR_ARCINT_C (DFE_BASE_ADDR + 0x0000001C)
#define MEI_DBG_WADDR_C (DFE_BASE_ADDR + 0x00000024)
#define MEI_DBG_RADDR_C (DFE_BASE_ADDR + 0x00000028)
#define MEI_DBG_DATA_C (DFE_BASE_ADDR + 0x0000002C)
#define MEI_DBG_DECO_C (DFE_BASE_ADDR + 0x00000030)
#define MEI_DBG_MASTER_C (DFE_BASE_ADDR + 0x0000003C)
static void WriteARCmem(uint32_t addr, uint32_t data)
{
writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C );
writel(addr ,(volatile uint32_t *)MEI_DBG_WADDR_C );
writel(data ,(volatile uint32_t *)MEI_DBG_DATA_C );
while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){};
writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
IFX_DEBUGP("WriteARCmem %08x %08x\n",addr,data);
};
static uint32_t ReadARCmem(uint32_t addr)
{
u32 data;
writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C );
writel(addr ,(volatile uint32_t *)MEI_DBG_RADDR_C );
while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){};
data = ifxusb_rreg((volatile uint32_t *)MEI_DBG_DATA_C );
writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
IFX_DEBUGP("ReadARCmem %08x %08x\n",addr,data);
return data;
};
void ifxusb_enable_afe_oc(void)
{
/* Start the clock */
WriteARCmem(CRI_UPDCTL ,0x00000008);
WriteARCmem(CRI_CCR0 ,0x00000014);
WriteARCmem(CRI_CCR1 ,0x00000500);
WriteARCmem(AFE_CONFIG ,0x000001c8);
WriteARCmem(AFE_SERIAL_CFG,0x00000016); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge
WriteARCmem(AFE_TCR_0 ,0x00000002);
//Take afe out of reset
WriteARCmem(AFE_CONFIG ,0x000000c0);
WriteARCmem(IRI_I_ENABLE ,0x00000101);
WriteARCmem(STY_SMODE ,0x00001980);
ReadARCmem(CRI_UPDCTL );
ReadARCmem(CRI_CCR0 );
ReadARCmem(CRI_CCR1 );
ReadARCmem(AFE_CONFIG );
ReadARCmem(AFE_SERIAL_CFG); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge
ReadARCmem(AFE_TCR_0 );
ReadARCmem(AFE_CONFIG );
ReadARCmem(IRI_I_ENABLE );
ReadARCmem(STY_SMODE );
}
#endif //defined(__IS_TWINPASS__)
#endif //defined(__UEIP__)

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target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_ctl.c Normal file
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target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_driver.c Normal file
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/*****************************************************************************
** FILE NAME : ifxusb_driver.c
** PROJECT : IFX USB sub-system V3
** MODULES : IFX USB sub-system Host and Device driver
** SRC VERSION : 1.0
** DATE : 1/Jan/2009
** AUTHOR : Chen, Howard
** DESCRIPTION : The provides the initialization and cleanup entry
** points for the IFX USB driver. This module can be
** dynamically loaded with insmod command or built-in
** with kernel. When loaded or executed the ifxusb_driver_init
** function is called. When the module is removed (using rmmod),
** the ifxusb_driver_cleanup function is called.
*****************************************************************************/
/*!
\file ifxusb_driver.c
\brief This file contains the loading/unloading interface to the Linux driver.
*/
#include <linux/version.h>
#include "ifxusb_version.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/stat.h> /* permission constants */
#include <linux/gpio.h>
#include <lantiq_soc.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
#include <linux/irq.h>
#endif
#include <asm/io.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
#include <asm/irq.h>
#endif
#include "ifxusb_plat.h"
#include "ifxusb_cif.h"
#ifdef __IS_HOST__
#include "ifxhcd.h"
#define USB_DRIVER_DESC "IFX USB HCD driver"
const char ifxusb_driver_name[] = "ifxusb_hcd";
#ifdef __IS_DUAL__
ifxhcd_hcd_t ifxusb_hcd_1;
ifxhcd_hcd_t ifxusb_hcd_2;
const char ifxusb_hcd_name_1[] = "ifxusb_hcd_1";
const char ifxusb_hcd_name_2[] = "ifxusb_hcd_2";
#else
ifxhcd_hcd_t ifxusb_hcd;
const char ifxusb_hcd_name[] = "ifxusb_hcd";
#endif
#if defined(__DO_OC_INT__)
static unsigned int oc_int_installed=0;
static ifxhcd_hcd_t *oc_int_id=NULL;
#endif
#endif
#ifdef __IS_DEVICE__
#include "ifxpcd.h"
#define USB_DRIVER_DESC "IFX USB PCD driver"
const char ifxusb_driver_name[] = "ifxusb_pcd";
ifxpcd_pcd_t ifxusb_pcd;
const char ifxusb_pcd_name[] = "ifxusb_pcd";
#endif
/* Global Debug Level Mask. */
#ifdef __IS_HOST__
uint32_t h_dbg_lvl = 0x00;
#endif
#ifdef __IS_DEVICE__
uint32_t d_dbg_lvl = 0x00;
#endif
ifxusb_params_t ifxusb_module_params;
static void parse_parms(void);
#include <lantiq_irq.h>
#define IFX_USB0_IR (INT_NUM_IM1_IRL0 + 22)
#define IFX_USB1_IR (INT_NUM_IM2_IRL0 + 19)
/*!
\brief This function is called when a driver is unregistered. This happens when
the rmmod command is executed. The device may or may not be electrically
present. If it is present, the driver stops device processing. Any resources
used on behalf of this device are freed.
*/
static int ifxusb_driver_remove(struct platform_device *_dev)
{
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
#ifdef __IS_HOST__
#if defined(__DO_OC_INT__)
#if defined(__DO_OC_INT_ENABLE__)
ifxusb_oc_int_off();
#endif
if(oc_int_installed && oc_int_id)
free_irq((unsigned int)IFXUSB_OC_IRQ, oc_int_id );
oc_int_installed=0;
oc_int_id=NULL;
#endif
#if defined(__IS_DUAL__)
ifxhcd_remove(&ifxusb_hcd_1);
ifxusb_core_if_remove(&ifxusb_hcd_1.core_if );
ifxhcd_remove(&ifxusb_hcd_2);
ifxusb_core_if_remove(&ifxusb_hcd_2.core_if );
#else
ifxhcd_remove(&ifxusb_hcd);
ifxusb_core_if_remove(&ifxusb_hcd.core_if );
#endif
#endif
#ifdef __IS_DEVICE__
ifxpcd_remove();
ifxusb_core_if_remove(&ifxusb_pcd.core_if );
#endif
/* Remove the device attributes */
ifxusb_attr_remove(&_dev->dev);
return 0;
}
/* Function to setup the structures to control one usb core running as host*/
#ifdef __IS_HOST__
/*!
\brief inlined by ifxusb_driver_probe(), handling host mode probing. Run at each host core.
*/
static inline int ifxusb_driver_probe_h(ifxhcd_hcd_t *_hcd,
int _irq,
uint32_t _iobase,
uint32_t _fifomem,
uint32_t _fifodbg
)
{
int retval = 0;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
#ifdef __DEV_NEW__
ifxusb_power_off (&_hcd->core_if);
ifxusb_phy_power_off (&_hcd->core_if); // Test
mdelay(500);
#endif //__DEV_NEW__
ifxusb_power_on (&_hcd->core_if);
mdelay(50);
ifxusb_phy_power_on (&_hcd->core_if); // Test
mdelay(50);
ifxusb_hard_reset(&_hcd->core_if);
retval =ifxusb_core_if_init(&_hcd->core_if,
_irq,
_iobase,
_fifomem,
_fifodbg);
if(retval)
return retval;
ifxusb_host_core_init(&_hcd->core_if,&ifxusb_module_params);
ifxusb_disable_global_interrupts( &_hcd->core_if);
/* The driver is now initialized and need to be registered into Linux USB sub-system */
retval = ifxhcd_init(_hcd); // hook the hcd into usb ss
if (retval != 0)
{
IFX_ERROR("_hcd_init failed\n");
return retval;
}
//ifxusb_enable_global_interrupts( _hcd->core_if ); // this should be done at hcd_start , including hcd_interrupt
return 0;
}
#endif //__IS_HOST__
#ifdef __IS_DEVICE__
/*!
\brief inlined by ifxusb_driver_probe(), handling device mode probing.
*/
static inline int ifxusb_driver_probe_d(ifxpcd_pcd_t *_pcd,
int _irq,
uint32_t _iobase,
uint32_t _fifomem,
uint32_t _fifodbg
)
{
int retval = 0;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
#ifdef __DEV_NEW__
ifxusb_power_off (&_pcd->core_if);
ifxusb_phy_power_off (&_pcd->core_if); // Test
mdelay(500);
#endif // __DEV_NEW__
ifxusb_power_on (&_pcd->core_if);
mdelay(50);
ifxusb_phy_power_on (&_pcd->core_if); // Test
mdelay(50);
ifxusb_hard_reset(&_pcd->core_if);
retval =ifxusb_core_if_init(&_pcd->core_if,
_irq,
_iobase,
_fifomem,
_fifodbg);
if(retval)
return retval;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
ifxusb_dev_core_init(&_pcd->core_if,&ifxusb_module_params);
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
ifxusb_disable_global_interrupts( &_pcd->core_if);
/* The driver is now initialized and need to be registered into
Linux USB Gadget sub-system
*/
retval = ifxpcd_init();
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
if (retval != 0)
{
IFX_ERROR("_pcd_init failed\n");
return retval;
}
//ifxusb_enable_global_interrupts( _pcd->core_if ); // this should be done at gadget bind or start
return 0;
}
#endif //__IS_DEVICE__
/*!
\brief This function is called by module management in 2.6 kernel or by ifxusb_driver_init with 2.4 kernel
It is to probe and setup IFXUSB core(s).
*/
static int ifxusb_driver_probe(struct platform_device *_dev)
{
int retval = 0;
int *pins = _dev->dev.platform_data;
if (ltq_is_vr9()) {
gpio_request(6, "id1");
gpio_request(9, "id2");
gpio_direction_input(6);
gpio_direction_input(9);
}
if (pins) {
if (pins[0]) {
gpio_request(pins[0], "vbus1");
gpio_direction_output(pins[0], 1);
}
if (pins[1] && ltq_is_vr9()) {
gpio_request(pins[1], "vbus2");
gpio_direction_output(pins[1], 1);
}
}
// Parsing and store the parameters
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
parse_parms();
#ifdef __IS_HOST__
#if defined(__IS_DUAL__)
memset(&ifxusb_hcd_1, 0, sizeof(ifxhcd_hcd_t));
memset(&ifxusb_hcd_2, 0, sizeof(ifxhcd_hcd_t));
ifxusb_hcd_1.core_if.core_no=0;
ifxusb_hcd_2.core_if.core_no=1;
ifxusb_hcd_1.core_if.core_name=(char *)ifxusb_hcd_name_1;
ifxusb_hcd_2.core_if.core_name=(char *)ifxusb_hcd_name_2;
ifxusb_hcd_1.dev=&_dev->dev;
ifxusb_hcd_2.dev=&_dev->dev;
retval = ifxusb_driver_probe_h(&ifxusb_hcd_1,
IFX_USB0_IR,
IFXUSB1_IOMEM_BASE,
IFXUSB1_FIFOMEM_BASE,
IFXUSB1_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
retval = ifxusb_driver_probe_h(&ifxusb_hcd_2,
IFX_USB1_IR,
IFXUSB2_IOMEM_BASE,
IFXUSB2_FIFOMEM_BASE,
IFXUSB2_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
#elif defined(__IS_FIRST__)
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
ifxusb_hcd.core_if.core_no=0;
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
ifxusb_hcd.dev=&_dev->dev;
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
IFX_USB0_IR,
IFXUSB1_IOMEM_BASE,
IFXUSB1_FIFOMEM_BASE,
IFXUSB1_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
#elif defined(__IS_SECOND__)
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
ifxusb_hcd.core_if.core_no=1;
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
ifxusb_hcd.dev=&_dev->dev;
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
IFX_USB1_IR,
IFXUSB2_IOMEM_BASE,
IFXUSB2_FIFOMEM_BASE,
IFXUSB2_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
#else
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
ifxusb_hcd.core_if.core_no=0;
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
ifxusb_hcd.dev=&_dev->dev;
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
IFXUSB_IRQ,
IFXUSB_IOMEM_BASE,
IFXUSB_FIFOMEM_BASE,
IFXUSB_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
#endif
#if defined(__DO_OC_INT__)
IFXUSB_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for irq%d\n", IFXUSB_OC_IRQ);
#if defined(__IS_DUAL__)
request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq,
// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd_1);
IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd_1);
oc_int_id=&ifxusb_hcd_1;
#else
request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq,
// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd);
IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd);
oc_int_id=&ifxusb_hcd;
#endif
oc_int_installed=1;
#if defined(__DO_OC_INT_ENABLE__)
ifxusb_oc_int_on();
#endif
#endif
#endif
#ifdef __IS_DEVICE__
memset(&ifxusb_pcd, 0, sizeof(ifxpcd_pcd_t));
ifxusb_pcd.core_if.core_name=(char *)&ifxusb_pcd_name[0];
ifxusb_pcd.dev=&_dev->dev;
#if defined(__IS_FIRST__)
ifxusb_pcd.core_if.core_no=0;
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
IFXUSB1_IRQ,
IFXUSB1_IOMEM_BASE,
IFXUSB1_FIFOMEM_BASE,
IFXUSB1_FIFODBG_BASE
);
#elif defined(__IS_SECOND__)
ifxusb_pcd.core_if.core_no=1;
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
IFXUSB2_IRQ,
IFXUSB2_IOMEM_BASE,
IFXUSB2_FIFOMEM_BASE,
IFXUSB2_FIFODBG_BASE
);
#else
ifxusb_pcd.core_if.core_no=0;
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
IFXUSB_IRQ,
IFXUSB_IOMEM_BASE,
IFXUSB_FIFOMEM_BASE,
IFXUSB_FIFODBG_BASE
);
#endif
if(retval)
goto ifxusb_driver_probe_fail;
#endif
ifxusb_attr_create(&_dev->dev);
return 0;
ifxusb_driver_probe_fail:
ifxusb_driver_remove(_dev);
return retval;
}
/*!
\brief This function is called when the ifxusb_driver is installed with the insmod command.
*/
static struct platform_driver ifxusb_driver = {
.driver = {
.name = ifxusb_driver_name,
.owner = THIS_MODULE,
},
.probe = ifxusb_driver_probe,
.remove = ifxusb_driver_remove,
};
int __init ifxusb_driver_init(void)
{
int retval = 0;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION);
retval = platform_driver_register(&ifxusb_driver);
if (retval < 0) {
IFX_ERROR("%s retval=%d\n", __func__, retval);
return retval;
}
return retval;
}
#if 0 // 2.4
int __init ifxusb_driver_init(void)
{
int retval = 0;
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION);
retval = ifxusb_driver_probe();
if (retval < 0) {
IFX_ERROR("%s retval=%d\n", __func__, retval);
return retval;
}
return retval;
}
#endif
module_init(ifxusb_driver_init);
/*!
\brief This function is called when the driver is removed from the kernel
with the rmmod command. The driver unregisters itself with its bus
driver.
*/
void __exit ifxusb_driver_cleanup(void)
{
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
platform_driver_unregister(&ifxusb_driver);
IFX_PRINT("%s module removed\n", ifxusb_driver_name);
}
#if 0
void __exit ifxusb_driver_cleanup(void)
{
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
ifxusb_driver_remove();
IFX_PRINT("%s module removed\n", ifxusb_driver_name);
}
#endif
module_exit(ifxusb_driver_cleanup);
MODULE_DESCRIPTION(USB_DRIVER_DESC);
MODULE_AUTHOR("Infineon");
MODULE_LICENSE("GPL");
// Parameters set when loaded
//static long dbg_lvl =0xFFFFFFFF;
static long dbg_lvl =0;
static short dma_burst_size =-1;
static short speed =-1;
static long data_fifo_size =-1;
#ifdef __IS_DEVICE__
static long rx_fifo_size =-1;
#ifdef __DED_FIFO__
static long tx_fifo_size_00 =-1;
static long tx_fifo_size_01 =-1;
static long tx_fifo_size_02 =-1;
static long tx_fifo_size_03 =-1;
static long tx_fifo_size_04 =-1;
static long tx_fifo_size_05 =-1;
static long tx_fifo_size_06 =-1;
static long tx_fifo_size_07 =-1;
static long tx_fifo_size_08 =-1;
static long tx_fifo_size_09 =-1;
static long tx_fifo_size_10 =-1;
static long tx_fifo_size_11 =-1;
static long tx_fifo_size_12 =-1;
static long tx_fifo_size_13 =-1;
static long tx_fifo_size_14 =-1;
static long tx_fifo_size_15 =-1;
static short thr_ctl=-1;
static long tx_thr_length =-1;
static long rx_thr_length =-1;
#else
static long nperio_tx_fifo_size =-1;
static long perio_tx_fifo_size_01 =-1;
static long perio_tx_fifo_size_02 =-1;
static long perio_tx_fifo_size_03 =-1;
static long perio_tx_fifo_size_04 =-1;
static long perio_tx_fifo_size_05 =-1;
static long perio_tx_fifo_size_06 =-1;
static long perio_tx_fifo_size_07 =-1;
static long perio_tx_fifo_size_08 =-1;
static long perio_tx_fifo_size_09 =-1;
static long perio_tx_fifo_size_10 =-1;
static long perio_tx_fifo_size_11 =-1;
static long perio_tx_fifo_size_12 =-1;
static long perio_tx_fifo_size_13 =-1;
static long perio_tx_fifo_size_14 =-1;
static long perio_tx_fifo_size_15 =-1;
#endif
static short dev_endpoints =-1;
#endif
#ifdef __IS_HOST__
static long rx_fifo_size =-1;
static long nperio_tx_fifo_size =-1;
static long perio_tx_fifo_size =-1;
static short host_channels =-1;
#endif
static long max_transfer_size =-1;
static long max_packet_count =-1;
static long phy_utmi_width =-1;
static long turn_around_time_hs =-1;
static long turn_around_time_fs =-1;
static long timeout_cal_hs =-1;
static long timeout_cal_fs =-1;
/*!
\brief Parsing the parameters taken when module load
*/
static void parse_parms(void)
{
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
#ifdef __IS_HOST__
h_dbg_lvl=dbg_lvl;
#endif
#ifdef __IS_DEVICE__
d_dbg_lvl=dbg_lvl;
#endif
switch(dma_burst_size)
{
case 0:
case 1:
case 4:
case 8:
case 16:
ifxusb_module_params.dma_burst_size=dma_burst_size;
break;
default:
ifxusb_module_params.dma_burst_size=default_param_dma_burst_size;
}
if(speed==0 || speed==1)
ifxusb_module_params.speed=speed;
else
ifxusb_module_params.speed=default_param_speed;
if(max_transfer_size>=2048 && max_transfer_size<=65535)
ifxusb_module_params.max_transfer_size=max_transfer_size;
else
ifxusb_module_params.max_transfer_size=default_param_max_transfer_size;
if(max_packet_count>=15 && max_packet_count<=511)
ifxusb_module_params.max_packet_count=max_packet_count;
else
ifxusb_module_params.max_packet_count=default_param_max_packet_count;
switch(phy_utmi_width)
{
case 8:
case 16:
ifxusb_module_params.phy_utmi_width=phy_utmi_width;
break;
default:
ifxusb_module_params.phy_utmi_width=default_param_phy_utmi_width;
}
if(turn_around_time_hs>=0 && turn_around_time_hs<=7)
ifxusb_module_params.turn_around_time_hs=turn_around_time_hs;
else
ifxusb_module_params.turn_around_time_hs=default_param_turn_around_time_hs;
if(turn_around_time_fs>=0 && turn_around_time_fs<=7)
ifxusb_module_params.turn_around_time_fs=turn_around_time_fs;
else
ifxusb_module_params.turn_around_time_fs=default_param_turn_around_time_fs;
if(timeout_cal_hs>=0 && timeout_cal_hs<=7)
ifxusb_module_params.timeout_cal_hs=timeout_cal_hs;
else
ifxusb_module_params.timeout_cal_hs=default_param_timeout_cal_hs;
if(timeout_cal_fs>=0 && timeout_cal_fs<=7)
ifxusb_module_params.timeout_cal_fs=timeout_cal_fs;
else
ifxusb_module_params.timeout_cal_fs=default_param_timeout_cal_fs;
if(data_fifo_size>=32 && data_fifo_size<=32768)
ifxusb_module_params.data_fifo_size=data_fifo_size;
else
ifxusb_module_params.data_fifo_size=default_param_data_fifo_size;
#ifdef __IS_HOST__
if(host_channels>=1 && host_channels<=16)
ifxusb_module_params.host_channels=host_channels;
else
ifxusb_module_params.host_channels=default_param_host_channels;
if(rx_fifo_size>=16 && rx_fifo_size<=32768)
ifxusb_module_params.rx_fifo_size=rx_fifo_size;
else
ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size;
if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768)
ifxusb_module_params.nperio_tx_fifo_size=nperio_tx_fifo_size;
else
ifxusb_module_params.nperio_tx_fifo_size=default_param_nperio_tx_fifo_size;
if(perio_tx_fifo_size>=16 && perio_tx_fifo_size<=32768)
ifxusb_module_params.perio_tx_fifo_size=perio_tx_fifo_size;
else
ifxusb_module_params.perio_tx_fifo_size=default_param_perio_tx_fifo_size;
#endif //__IS_HOST__
#ifdef __IS_DEVICE__
if(rx_fifo_size>=16 && rx_fifo_size<=32768)
ifxusb_module_params.rx_fifo_size=rx_fifo_size;
else
ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size;
#ifdef __DED_FIFO__
if(tx_fifo_size_00>=16 && tx_fifo_size_00<=32768)
ifxusb_module_params.tx_fifo_size[ 0]=tx_fifo_size_00;
else
ifxusb_module_params.tx_fifo_size[ 0]=default_param_tx_fifo_size_00;
if(tx_fifo_size_01>=0 && tx_fifo_size_01<=32768)
ifxusb_module_params.tx_fifo_size[ 1]=tx_fifo_size_01;
else
ifxusb_module_params.tx_fifo_size[ 1]=default_param_tx_fifo_size_01;
if(tx_fifo_size_02>=0 && tx_fifo_size_02<=32768)
ifxusb_module_params.tx_fifo_size[ 2]=tx_fifo_size_02;
else
ifxusb_module_params.tx_fifo_size[ 2]=default_param_tx_fifo_size_02;
if(tx_fifo_size_03>=0 && tx_fifo_size_03<=32768)
ifxusb_module_params.tx_fifo_size[ 3]=tx_fifo_size_03;
else
ifxusb_module_params.tx_fifo_size[ 3]=default_param_tx_fifo_size_03;
if(tx_fifo_size_04>=0 && tx_fifo_size_04<=32768)
ifxusb_module_params.tx_fifo_size[ 4]=tx_fifo_size_04;
else
ifxusb_module_params.tx_fifo_size[ 4]=default_param_tx_fifo_size_04;
if(tx_fifo_size_05>=0 && tx_fifo_size_05<=32768)
ifxusb_module_params.tx_fifo_size[ 5]=tx_fifo_size_05;
else
ifxusb_module_params.tx_fifo_size[ 5]=default_param_tx_fifo_size_05;
if(tx_fifo_size_06>=0 && tx_fifo_size_06<=32768)
ifxusb_module_params.tx_fifo_size[ 6]=tx_fifo_size_06;
else
ifxusb_module_params.tx_fifo_size[ 6]=default_param_tx_fifo_size_06;
if(tx_fifo_size_07>=0 && tx_fifo_size_07<=32768)
ifxusb_module_params.tx_fifo_size[ 7]=tx_fifo_size_07;
else
ifxusb_module_params.tx_fifo_size[ 7]=default_param_tx_fifo_size_07;
if(tx_fifo_size_08>=0 && tx_fifo_size_08<=32768)
ifxusb_module_params.tx_fifo_size[ 8]=tx_fifo_size_08;
else
ifxusb_module_params.tx_fifo_size[ 8]=default_param_tx_fifo_size_08;
if(tx_fifo_size_09>=0 && tx_fifo_size_09<=32768)
ifxusb_module_params.tx_fifo_size[ 9]=tx_fifo_size_09;
else
ifxusb_module_params.tx_fifo_size[ 9]=default_param_tx_fifo_size_09;
if(tx_fifo_size_10>=0 && tx_fifo_size_10<=32768)
ifxusb_module_params.tx_fifo_size[10]=tx_fifo_size_10;
else
ifxusb_module_params.tx_fifo_size[10]=default_param_tx_fifo_size_10;
if(tx_fifo_size_11>=0 && tx_fifo_size_11<=32768)
ifxusb_module_params.tx_fifo_size[11]=tx_fifo_size_11;
else
ifxusb_module_params.tx_fifo_size[11]=default_param_tx_fifo_size_11;
if(tx_fifo_size_12>=0 && tx_fifo_size_12<=32768)
ifxusb_module_params.tx_fifo_size[12]=tx_fifo_size_12;
else
ifxusb_module_params.tx_fifo_size[12]=default_param_tx_fifo_size_12;
if(tx_fifo_size_13>=0 && tx_fifo_size_13<=32768)
ifxusb_module_params.tx_fifo_size[13]=tx_fifo_size_13;
else
ifxusb_module_params.tx_fifo_size[13]=default_param_tx_fifo_size_13;
if(tx_fifo_size_14>=0 && tx_fifo_size_14<=32768)
ifxusb_module_params.tx_fifo_size[14]=tx_fifo_size_14;
else
ifxusb_module_params.tx_fifo_size[14]=default_param_tx_fifo_size_14;
if(tx_fifo_size_15>=0 && tx_fifo_size_15<=32768)
ifxusb_module_params.tx_fifo_size[15]=tx_fifo_size_15;
else
ifxusb_module_params.tx_fifo_size[15]=default_param_tx_fifo_size_15;
if(thr_ctl==0 || thr_ctl==1)
ifxusb_module_params.thr_ctl=thr_ctl;
else
ifxusb_module_params.thr_ctl=default_param_thr_ctl;
if(tx_thr_length>=16 && tx_thr_length<=511)
ifxusb_module_params.tx_thr_length=tx_thr_length;
else
ifxusb_module_params.tx_thr_length=default_param_tx_thr_length;
if(rx_thr_length>=16 && rx_thr_length<=511)
ifxusb_module_params.rx_thr_length=rx_thr_length;
else
ifxusb_module_params.rx_thr_length=default_param_rx_thr_length;
#else //__DED_FIFO__
if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768)
ifxusb_module_params.tx_fifo_size[ 0]=nperio_tx_fifo_size;
else
ifxusb_module_params.tx_fifo_size[ 0]=default_param_nperio_tx_fifo_size;
if(perio_tx_fifo_size_01>=0 && perio_tx_fifo_size_01<=32768)
ifxusb_module_params.tx_fifo_size[ 1]=perio_tx_fifo_size_01;
else
ifxusb_module_params.tx_fifo_size[ 1]=default_param_perio_tx_fifo_size_01;
if(perio_tx_fifo_size_02>=0 && perio_tx_fifo_size_02<=32768)
ifxusb_module_params.tx_fifo_size[ 2]=perio_tx_fifo_size_02;
else
ifxusb_module_params.tx_fifo_size[ 2]=default_param_perio_tx_fifo_size_02;
if(perio_tx_fifo_size_03>=0 && perio_tx_fifo_size_03<=32768)
ifxusb_module_params.tx_fifo_size[ 3]=perio_tx_fifo_size_03;
else
ifxusb_module_params.tx_fifo_size[ 3]=default_param_perio_tx_fifo_size_03;
if(perio_tx_fifo_size_04>=0 && perio_tx_fifo_size_04<=32768)
ifxusb_module_params.tx_fifo_size[ 4]=perio_tx_fifo_size_04;
else
ifxusb_module_params.tx_fifo_size[ 4]=default_param_perio_tx_fifo_size_04;
if(perio_tx_fifo_size_05>=0 && perio_tx_fifo_size_05<=32768)
ifxusb_module_params.tx_fifo_size[ 5]=perio_tx_fifo_size_05;
else
ifxusb_module_params.tx_fifo_size[ 5]=default_param_perio_tx_fifo_size_05;
if(perio_tx_fifo_size_06>=0 && perio_tx_fifo_size_06<=32768)
ifxusb_module_params.tx_fifo_size[ 6]=perio_tx_fifo_size_06;
else
ifxusb_module_params.tx_fifo_size[ 6]=default_param_perio_tx_fifo_size_06;
if(perio_tx_fifo_size_07>=0 && perio_tx_fifo_size_07<=32768)
ifxusb_module_params.tx_fifo_size[ 7]=perio_tx_fifo_size_07;
else
ifxusb_module_params.tx_fifo_size[ 7]=default_param_perio_tx_fifo_size_07;
if(perio_tx_fifo_size_08>=0 && perio_tx_fifo_size_08<=32768)
ifxusb_module_params.tx_fifo_size[ 8]=perio_tx_fifo_size_08;
else
ifxusb_module_params.tx_fifo_size[ 8]=default_param_perio_tx_fifo_size_08;
if(perio_tx_fifo_size_09>=0 && perio_tx_fifo_size_09<=32768)
ifxusb_module_params.tx_fifo_size[ 9]=perio_tx_fifo_size_09;
else
ifxusb_module_params.tx_fifo_size[ 9]=default_param_perio_tx_fifo_size_09;
if(perio_tx_fifo_size_10>=0 && perio_tx_fifo_size_10<=32768)
ifxusb_module_params.tx_fifo_size[10]=perio_tx_fifo_size_10;
else
ifxusb_module_params.tx_fifo_size[10]=default_param_perio_tx_fifo_size_10;
if(perio_tx_fifo_size_11>=0 && perio_tx_fifo_size_11<=32768)
ifxusb_module_params.tx_fifo_size[11]=perio_tx_fifo_size_11;
else
ifxusb_module_params.tx_fifo_size[11]=default_param_perio_tx_fifo_size_11;
if(perio_tx_fifo_size_12>=0 && perio_tx_fifo_size_12<=32768)
ifxusb_module_params.tx_fifo_size[12]=perio_tx_fifo_size_12;
else
ifxusb_module_params.tx_fifo_size[12]=default_param_perio_tx_fifo_size_12;
if(perio_tx_fifo_size_13>=0 && perio_tx_fifo_size_13<=32768)
ifxusb_module_params.tx_fifo_size[13]=perio_tx_fifo_size_13;
else
ifxusb_module_params.tx_fifo_size[13]=default_param_perio_tx_fifo_size_13;
if(perio_tx_fifo_size_14>=0 && perio_tx_fifo_size_14<=32768)
ifxusb_module_params.tx_fifo_size[14]=perio_tx_fifo_size_14;
else
ifxusb_module_params.tx_fifo_size[14]=default_param_perio_tx_fifo_size_14;
if(perio_tx_fifo_size_15>=0 && perio_tx_fifo_size_15<=32768)
ifxusb_module_params.tx_fifo_size[15]=perio_tx_fifo_size_15;
else
ifxusb_module_params.tx_fifo_size[15]=default_param_perio_tx_fifo_size_15;
#endif //__DED_FIFO__
#endif //__IS_DEVICE__
}
module_param(dbg_lvl, long, 0444);
MODULE_PARM_DESC(dbg_lvl, "Debug level.");
module_param(dma_burst_size, short, 0444);
MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 0, 1, 4, 8, 16");
module_param(speed, short, 0444);
MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
module_param(data_fifo_size, long, 0444);
MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
#ifdef __IS_DEVICE__
module_param(rx_fifo_size, long, 0444);
MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
#ifdef __DED_FIFO__
module_param(tx_fifo_size_00, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_00, "Number of words in the Tx FIFO #00 16-32768");
module_param(tx_fifo_size_01, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_01, "Number of words in the Tx FIFO #01 0-32768");
module_param(tx_fifo_size_02, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_02, "Number of words in the Tx FIFO #02 0-32768");
module_param(tx_fifo_size_03, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_03, "Number of words in the Tx FIFO #03 0-32768");
module_param(tx_fifo_size_04, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_04, "Number of words in the Tx FIFO #04 0-32768");
module_param(tx_fifo_size_05, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_05, "Number of words in the Tx FIFO #05 0-32768");
module_param(tx_fifo_size_06, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_06, "Number of words in the Tx FIFO #06 0-32768");
module_param(tx_fifo_size_07, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_07, "Number of words in the Tx FIFO #07 0-32768");
module_param(tx_fifo_size_08, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_08, "Number of words in the Tx FIFO #08 0-32768");
module_param(tx_fifo_size_09, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_09, "Number of words in the Tx FIFO #09 0-32768");
module_param(tx_fifo_size_10, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_10, "Number of words in the Tx FIFO #10 0-32768");
module_param(tx_fifo_size_11, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_11, "Number of words in the Tx FIFO #11 0-32768");
module_param(tx_fifo_size_12, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_12, "Number of words in the Tx FIFO #12 0-32768");
module_param(tx_fifo_size_13, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_13, "Number of words in the Tx FIFO #13 0-32768");
module_param(tx_fifo_size_14, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_14, "Number of words in the Tx FIFO #14 0-32768");
module_param(tx_fifo_size_15, long, 0444);
MODULE_PARM_DESC(tx_fifo_size_15, "Number of words in the Tx FIFO #15 0-32768");
module_param(thr_ctl, short, 0444);
MODULE_PARM_DESC(thr_ctl, "0=Without 1=With Theshold Ctrl");
module_param(tx_thr_length, long, 0444);
MODULE_PARM_DESC(tx_thr_length, "TX Threshold length");
module_param(rx_thr_length, long, 0444);
MODULE_PARM_DESC(rx_thr_length, "RX Threshold length");
#else
module_param(nperio_tx_fifo_size, long, 0444);
MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
module_param(perio_tx_fifo_size_01, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_01, "Number of words in the periodic Tx FIFO #01 0-32768");
module_param(perio_tx_fifo_size_02, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_02, "Number of words in the periodic Tx FIFO #02 0-32768");
module_param(perio_tx_fifo_size_03, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_03, "Number of words in the periodic Tx FIFO #03 0-32768");
module_param(perio_tx_fifo_size_04, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_04, "Number of words in the periodic Tx FIFO #04 0-32768");
module_param(perio_tx_fifo_size_05, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_05, "Number of words in the periodic Tx FIFO #05 0-32768");
module_param(perio_tx_fifo_size_06, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_06, "Number of words in the periodic Tx FIFO #06 0-32768");
module_param(perio_tx_fifo_size_07, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_07, "Number of words in the periodic Tx FIFO #07 0-32768");
module_param(perio_tx_fifo_size_08, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_08, "Number of words in the periodic Tx FIFO #08 0-32768");
module_param(perio_tx_fifo_size_09, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_09, "Number of words in the periodic Tx FIFO #09 0-32768");
module_param(perio_tx_fifo_size_10, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO #10 0-32768");
module_param(perio_tx_fifo_size_11, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO #11 0-32768");
module_param(perio_tx_fifo_size_12, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO #12 0-32768");
module_param(perio_tx_fifo_size_13, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO #13 0-32768");
module_param(perio_tx_fifo_size_14, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO #14 0-32768");
module_param(perio_tx_fifo_size_15, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO #15 0-32768");
#endif//__DED_FIFO__
module_param(dev_endpoints, short, 0444);
MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
#endif
#ifdef __IS_HOST__
module_param(rx_fifo_size, long, 0444);
MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
module_param(nperio_tx_fifo_size, long, 0444);
MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
module_param(perio_tx_fifo_size, long, 0444);
MODULE_PARM_DESC(perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
module_param(host_channels, short, 0444);
MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
#endif
module_param(max_transfer_size, long, 0444);
MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
module_param(max_packet_count, long, 0444);
MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
module_param(phy_utmi_width, long, 0444);
MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
module_param(turn_around_time_hs, long, 0444);
MODULE_PARM_DESC(turn_around_time_hs, "Turn-Around time for HS");
module_param(turn_around_time_fs, long, 0444);
MODULE_PARM_DESC(turn_around_time_fs, "Turn-Around time for FS");
module_param(timeout_cal_hs, long, 0444);
MODULE_PARM_DESC(timeout_cal_hs, "Timeout Cal for HS");
module_param(timeout_cal_fs, long, 0444);
MODULE_PARM_DESC(timeout_cal_fs, "Timeout Cal for FS");

1018
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_plat.h Normal file
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1420
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_regs.h Normal file
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5
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_version.h Normal file
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@@ -0,0 +1,5 @@
#ifndef IFXUSB_VERSION
#define IFXUSB_VERSION "3.0alpha B100312"
#endif