qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00
Code Activity

[lantiq] move files/ -> files-3.3/

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34060 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2012-11-02 20:07:02 +00:00
parent 961508b717
commit 1048c7b452
135 changed files with 0 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/Kconfig Normal file
View File

@@ -0,0 +1,37 @@
config DWC_OTG
tristate "Synopsis DWC_OTG support"
depends on USB
help
This driver supports Synopsis DWC_OTG IP core
embebbed on many SOCs (ralink, infineon, etc)
choice
prompt "USB Operation Mode"
depends on DWC_OTG
default DWC_OTG_HOST_ONLY
config DWC_OTG_HOST_ONLY
bool "HOST ONLY MODE"
depends on DWC_OTG
#config DWC_OTG_DEVICE_ONLY
# bool "DEVICE ONLY MODE"
# depends on DWC_OTG
endchoice
choice
prompt "Platform"
depends on DWC_OTG
default DWC_OTG_LANTIQ
config DWC_OTG_LANTIQ
bool "Lantiq"
depends on LANTIQ
help
Danube USB Host Controller
platform support
endchoice
config DWC_OTG_DEBUG
bool "Enable debug mode"
depends on DWC_OTG

39
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/Makefile Normal file
View File

@@ -0,0 +1,39 @@
#
# Makefile for DWC_otg Highspeed USB controller driver
#
ifeq ($(CONFIG_DWC_OTG_DEBUG),y)
EXTRA_CFLAGS += -DDEBUG
endif
# Use one of the following flags to compile the software in host-only or
# device-only mode based on the configuration selected by the user
ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
EXTRA_CFLAGS += -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY
EXTRA_CFLAGS += -DDWC_OTG_EN_ISOC -DDWC_EN_ISOC
else ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y)
EXTRA_CFLAGS += -DDWC_OTG_DEVICE_ONLY
else
EXTRA_CFLAGS += -DDWC_OTG_MODE
endif
# EXTRA_CFLAGS += -DDWC_HS_ELECT_TST
# EXTRA_CFLAGS += -DDWC_OTG_EXT_CHG_PUMP
ifeq ($(CONFIG_DWC_OTG_LANTIQ),y)
EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -D__KERNEL__
endif
ifeq ($(CONFIG_DWC_OTG_LANTIQ),m)
EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_HOST_ONLY -DMODULE -D__KERNEL__ -DDEBUG
endif
obj-$(CONFIG_DWC_OTG) := dwc_otg.o
dwc_otg-objs := dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
#dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
dwc_otg-objs += dwc_otg_attr.o
dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
dwc_otg-objs += dwc_otg_ifx.o
dwc_otg-objs += dwc_otg_driver.o
#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o
#dwc_otg_ifx-objs := dwc_otg_ifx.o

802
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_attr.c Normal file
View File

@@ -0,0 +1,802 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
/** @file
*
* The diagnostic interface will provide access to the controller for
* bringing up the hardware and testing. The Linux driver attributes
* feature will be used to provide the Linux Diagnostic
* Interface. These attributes are accessed through sysfs.
*/
/** @page "Linux Module Attributes"
*
* The Linux module attributes feature is used to provide the Linux
* Diagnostic Interface. These attributes are accessed through sysfs.
* The diagnostic interface will provide access to the controller for
* bringing up the hardware and testing.
The following table shows the attributes.
<table>
<tr>
<td><b> Name</b></td>
<td><b> Description</b></td>
<td><b> Access</b></td>
</tr>
<tr>
<td> mode </td>
<td> Returns the current mode: 0 for device mode, 1 for host mode</td>
<td> Read</td>
</tr>
<tr>
<td> hnpcapable </td>
<td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
Read returns the current value.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> srpcapable </td>
<td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
Read returns the current value.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> hnp </td>
<td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> srp </td>
<td> Initiates the Session Request Protocol. Read returns the status.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> buspower </td>
<td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
<td> Read/Write</td>
</tr>
<tr>
<td> bussuspend </td>
<td> Suspends the USB bus.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> busconnected </td>
<td> Gets the connection status of the bus</td>
<td> Read</td>
</tr>
<tr>
<td> gotgctl </td>
<td> Gets or sets the Core Control Status Register.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gusbcfg </td>
<td> Gets or sets the Core USB Configuration Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> grxfsiz </td>
<td> Gets or sets the Receive FIFO Size Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gnptxfsiz </td>
<td> Gets or sets the non-periodic Transmit Size Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gpvndctl </td>
<td> Gets or sets the PHY Vendor Control Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> ggpio </td>
<td> Gets the value in the lower 16-bits of the General Purpose IO Register
or sets the upper 16 bits.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> guid </td>
<td> Gets or sets the value of the User ID Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> gsnpsid </td>
<td> Gets the value of the Synopsys ID Regester</td>
<td> Read</td>
</tr>
<tr>
<td> devspeed </td>
<td> Gets or sets the device speed setting in the DCFG register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> enumspeed </td>
<td> Gets the device enumeration Speed.</td>
<td> Read</td>
</tr>
<tr>
<td> hptxfsiz </td>
<td> Gets the value of the Host Periodic Transmit FIFO</td>
<td> Read</td>
</tr>
<tr>
<td> hprt0 </td>
<td> Gets or sets the value in the Host Port Control and Status Register</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regoffset </td>
<td> Sets the register offset for the next Register Access</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regvalue </td>
<td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> remote_wakeup </td>
<td> On read, shows the status of Remote Wakeup. On write, initiates a remote
wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
Wakeup signalling bit in the Device Control Register is set for 1
milli-second.</td>
<td> Read/Write</td>
</tr>
<tr>
<td> regdump </td>
<td> Dumps the contents of core registers.</td>
<td> Read</td>
</tr>
<tr>
<td> hcddump </td>
<td> Dumps the current HCD state.</td>
<td> Read</td>
</tr>
<tr>
<td> hcd_frrem </td>
<td> Shows the average value of the Frame Remaining
field in the Host Frame Number/Frame Remaining register when an SOF interrupt
occurs. This can be used to determine the average interrupt latency. Also
shows the average Frame Remaining value for start_transfer and the "a" and
"b" sample points. The "a" and "b" sample points may be used during debugging
bto determine how long it takes to execute a section of the HCD code.</td>
<td> Read</td>
</tr>
<tr>
<td> rd_reg_test </td>
<td> Displays the time required to read the GNPTXFSIZ register many times
(the output shows the number of times the register is read).
<td> Read</td>
</tr>
<tr>
<td> wr_reg_test </td>
<td> Displays the time required to write the GNPTXFSIZ register many times
(the output shows the number of times the register is written).
<td> Read</td>
</tr>
</table>
Example usage:
To get the current mode:
cat /sys/devices/lm0/mode
To power down the USB:
echo 0 > /sys/devices/lm0/buspower
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/stat.h> /* permission constants */
#include <asm/io.h>
#include "dwc_otg_plat.h"
#include "dwc_otg_attr.h"
#include "dwc_otg_driver.h"
// #include "dwc_otg_pcd.h"
#include "dwc_otg_hcd.h"
// 20070316, winder added.
#ifndef SZ_256K
#define SZ_256K 0x00040000
#endif
/*
* MACROs for defining sysfs attribute
*/
#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val; \
val = dwc_read_reg32 (_addr_); \
val = (val & (_mask_)) >> _shift_; \
return sprintf (buf, "%s = 0x%x\n", _string_, val); \
}
#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t set = simple_strtoul(buf, NULL, 16); \
uint32_t clear = set; \
clear = ((~clear) << _shift_) & _mask_; \
set = (set << _shift_) & _mask_; \
dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
dwc_modify_reg32(_addr_, clear, set); \
return count; \
}
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
/*
* MACROs for defining sysfs attribute for 32-bit registers
*/
#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val; \
val = dwc_read_reg32 (_addr_); \
return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
}
#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
{ \
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
uint32_t val = simple_strtoul(buf, NULL, 16); \
dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
dwc_write_reg32(_addr_, val); \
return count; \
}
#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
/** @name Functions for Show/Store of Attributes */
/**@{*/
/**
* Show the register offset of the Register Access.
*/
static ssize_t regoffset_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
}
/**
* Set the register offset for the next Register Access Read/Write
*/
static ssize_t regoffset_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t offset = simple_strtoul(buf, NULL, 16);
//dev_dbg(_dev, "Offset=0x%08x\n", offset);
if (offset < SZ_256K ) {
otg_dev->reg_offset = offset;
}
else {
dev_err( _dev, "invalid offset\n" );
}
return count;
}
DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, regoffset_show, regoffset_store);
/**
* Show the value of the register at the offset in the reg_offset
* attribute.
*/
static ssize_t regvalue_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t val;
volatile uint32_t *addr;
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t*)(otg_dev->reg_offset +
(uint8_t*)otg_dev->base);
//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
val = dwc_read_reg32( addr );
return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
"Reg@0x%06x = 0x%08x\n",
otg_dev->reg_offset, val);
}
else {
dev_err(_dev, "Invalid offset (0x%0x)\n",
otg_dev->reg_offset);
return sprintf(buf, "invalid offset\n" );
}
}
/**
* Store the value in the register at the offset in the reg_offset
* attribute.
*
*/
static ssize_t regvalue_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
volatile uint32_t * addr;
uint32_t val = simple_strtoul(buf, NULL, 16);
//dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t*)(otg_dev->reg_offset +
(uint8_t*)otg_dev->base);
//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
dwc_write_reg32( addr, val );
}
else {
dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
otg_dev->reg_offset);
}
return count;
}
DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
/*
* Attributes
*/
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
/**
* @todo Add code to initiate the HNP.
*/
/**
* Show the HNP status bit
*/
static ssize_t hnp_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
gotgctl_data_t val;
val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
}
/**
* Set the HNP Request bit
*/
static ssize_t hnp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t in = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
gotgctl_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.hnpreq = in;
dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
/**
* @todo Add code to initiate the SRP.
*/
/**
* Show the SRP status bit
*/
static ssize_t srp_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
gotgctl_data_t val;
val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
#else
return sprintf(buf, "Host Only Mode!\n");
#endif
}
/**
* Set the SRP Request bit
*/
static ssize_t srp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_pcd_initiate_srp(otg_dev->pcd);
#endif
return count;
}
DEVICE_ATTR(srp, 0644, srp_show, srp_store);
/**
* @todo Need to do more for power on/off?
*/
/**
* Show the Bus Power status
*/
static ssize_t buspower_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
hprt0_data_t val;
val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
}
/**
* Set the Bus Power status
*/
static ssize_t buspower_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t on = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
hprt0_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.prtpwr = on;
//dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
/**
* @todo Need to do more for suspend?
*/
/**
* Show the Bus Suspend status
*/
static ssize_t bussuspend_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
hprt0_data_t val;
val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
}
/**
* Set the Bus Suspend status
*/
static ssize_t bussuspend_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t in = simple_strtoul(buf, NULL, 16);
uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
hprt0_data_t mem;
mem.d32 = dwc_read_reg32(addr);
mem.b.prtsusp = in;
dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
dwc_write_reg32(addr, mem.d32);
return count;
}
DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
/**
* Show the status of Remote Wakeup.
*/
static ssize_t remote_wakeup_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dctl_data_t val;
val.d32 = dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
#else
return sprintf(buf, "Host Only Mode!\n");
#endif
}
/**
* Initiate a remote wakeup of the host. The Device control register
* Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
* flag is set.
*
*/
static ssize_t remote_wakeup_store( struct device *_dev, struct device_attribute *attr, const char *buf,
size_t count )
{
#ifndef DWC_HOST_ONLY
uint32_t val = simple_strtoul(buf, NULL, 16);
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
if (val&1) {
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
}
else {
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
}
#endif
return count;
}
DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
remote_wakeup_store);
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifdef DEBUG
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev);
dwc_otg_dump_global_registers( otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if)) {
dwc_otg_dump_host_registers( otg_dev->core_if);
} else {
dwc_otg_dump_dev_registers( otg_dev->core_if);
}
#endif
return sprintf( buf, "Register Dump\n" );
}
DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
/**
* Dump the current hcd state.
*/
static ssize_t hcddump_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_hcd_dump_state(otg_dev->hcd);
#endif
return sprintf( buf, "HCD Dump\n" );
}
DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
*/
static ssize_t hcd_frrem_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
dwc_otg_hcd_dump_frrem(otg_dev->hcd);
#endif
return sprintf( buf, "HCD Dump Frame Remaining\n" );
}
DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
/**
* Displays the time required to read the GNPTXFSIZ register many times (the
* output shows the number of times the register is read).
*/
#define RW_REG_COUNT 10000000
#define MSEC_PER_JIFFIE 1000/HZ
static ssize_t rd_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
int i;
int time;
int start_jiffies;
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++) {
dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
}
time = jiffies - start_jiffies;
return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
}
DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
/**
* Displays the time required to write the GNPTXFSIZ register many times (the
* output shows the number of times the register is written).
*/
static ssize_t wr_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
{
int i;
int time;
int start_jiffies;
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
uint32_t reg_val;
printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++) {
dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
}
time = jiffies - start_jiffies;
return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
}
DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
/**@}*/
/**
* Create the device files
*/
void dwc_otg_attr_create (struct device *_dev)
{
int retval;
retval = device_create_file(_dev, &dev_attr_regoffset);
retval += device_create_file(_dev, &dev_attr_regvalue);
retval += device_create_file(_dev, &dev_attr_mode);
retval += device_create_file(_dev, &dev_attr_hnpcapable);
retval += device_create_file(_dev, &dev_attr_srpcapable);
retval += device_create_file(_dev, &dev_attr_hnp);
retval += device_create_file(_dev, &dev_attr_srp);
retval += device_create_file(_dev, &dev_attr_buspower);
retval += device_create_file(_dev, &dev_attr_bussuspend);
retval += device_create_file(_dev, &dev_attr_busconnected);
retval += device_create_file(_dev, &dev_attr_gotgctl);
retval += device_create_file(_dev, &dev_attr_gusbcfg);
retval += device_create_file(_dev, &dev_attr_grxfsiz);
retval += device_create_file(_dev, &dev_attr_gnptxfsiz);
retval += device_create_file(_dev, &dev_attr_gpvndctl);
retval += device_create_file(_dev, &dev_attr_ggpio);
retval += device_create_file(_dev, &dev_attr_guid);
retval += device_create_file(_dev, &dev_attr_gsnpsid);
retval += device_create_file(_dev, &dev_attr_devspeed);
retval += device_create_file(_dev, &dev_attr_enumspeed);
retval += device_create_file(_dev, &dev_attr_hptxfsiz);
retval += device_create_file(_dev, &dev_attr_hprt0);
retval += device_create_file(_dev, &dev_attr_remote_wakeup);
retval += device_create_file(_dev, &dev_attr_regdump);
retval += device_create_file(_dev, &dev_attr_hcddump);
retval += device_create_file(_dev, &dev_attr_hcd_frrem);
retval += device_create_file(_dev, &dev_attr_rd_reg_test);
retval += device_create_file(_dev, &dev_attr_wr_reg_test);
if(retval != 0)
{
DWC_PRINT("cannot create sysfs device files.\n");
// DWC_PRINT("killing own sysfs device files!\n");
dwc_otg_attr_remove(_dev);
}
}
/**
* Remove the device files
*/
void dwc_otg_attr_remove (struct device *_dev)
{
device_remove_file(_dev, &dev_attr_regoffset);
device_remove_file(_dev, &dev_attr_regvalue);
device_remove_file(_dev, &dev_attr_mode);
device_remove_file(_dev, &dev_attr_hnpcapable);
device_remove_file(_dev, &dev_attr_srpcapable);
device_remove_file(_dev, &dev_attr_hnp);
device_remove_file(_dev, &dev_attr_srp);
device_remove_file(_dev, &dev_attr_buspower);
device_remove_file(_dev, &dev_attr_bussuspend);
device_remove_file(_dev, &dev_attr_busconnected);
device_remove_file(_dev, &dev_attr_gotgctl);
device_remove_file(_dev, &dev_attr_gusbcfg);
device_remove_file(_dev, &dev_attr_grxfsiz);
device_remove_file(_dev, &dev_attr_gnptxfsiz);
device_remove_file(_dev, &dev_attr_gpvndctl);
device_remove_file(_dev, &dev_attr_ggpio);
device_remove_file(_dev, &dev_attr_guid);
device_remove_file(_dev, &dev_attr_gsnpsid);
device_remove_file(_dev, &dev_attr_devspeed);
device_remove_file(_dev, &dev_attr_enumspeed);
device_remove_file(_dev, &dev_attr_hptxfsiz);
device_remove_file(_dev, &dev_attr_hprt0);
device_remove_file(_dev, &dev_attr_remote_wakeup);
device_remove_file(_dev, &dev_attr_regdump);
device_remove_file(_dev, &dev_attr_hcddump);
device_remove_file(_dev, &dev_attr_hcd_frrem);
device_remove_file(_dev, &dev_attr_rd_reg_test);
device_remove_file(_dev, &dev_attr_wr_reg_test);
}

67
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_attr.h Normal file
View File

@@ -0,0 +1,67 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510275 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_ATTR_H__)
#define __DWC_OTG_ATTR_H__
/** @file
* This file contains the interface to the Linux device attributes.
*/
extern struct device_attribute dev_attr_regoffset;
extern struct device_attribute dev_attr_regvalue;
extern struct device_attribute dev_attr_mode;
extern struct device_attribute dev_attr_hnpcapable;
extern struct device_attribute dev_attr_srpcapable;
extern struct device_attribute dev_attr_hnp;
extern struct device_attribute dev_attr_srp;
extern struct device_attribute dev_attr_buspower;
extern struct device_attribute dev_attr_bussuspend;
extern struct device_attribute dev_attr_busconnected;
extern struct device_attribute dev_attr_gotgctl;
extern struct device_attribute dev_attr_gusbcfg;
extern struct device_attribute dev_attr_grxfsiz;
extern struct device_attribute dev_attr_gnptxfsiz;
extern struct device_attribute dev_attr_gpvndctl;
extern struct device_attribute dev_attr_ggpio;
extern struct device_attribute dev_attr_guid;
extern struct device_attribute dev_attr_gsnpsid;
extern struct device_attribute dev_attr_devspeed;
extern struct device_attribute dev_attr_enumspeed;
extern struct device_attribute dev_attr_hptxfsiz;
extern struct device_attribute dev_attr_hprt0;
void dwc_otg_attr_create (struct device *_dev);
void dwc_otg_attr_remove (struct device *_dev);
#endif

3025
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_cil.c Normal file
View File

File diff suppressed because it is too large Load Diff

911
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_cil.h Normal file
View File

@@ -0,0 +1,911 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 631780 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_CIL_H__)
#define __DWC_CIL_H__
#include "dwc_otg_plat.h"
#include "dwc_otg_regs.h"
#ifdef DEBUG
#include "linux/timer.h"
#endif
/* the OTG capabilities. */
#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
/* the maximum speed of operation in host and device mode. */
#define DWC_SPEED_PARAM_HIGH 0
#define DWC_SPEED_PARAM_FULL 1
/* the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. */
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
/* the type of PHY interface to use. */
#define DWC_PHY_TYPE_PARAM_FS 0
#define DWC_PHY_TYPE_PARAM_UTMI 1
#define DWC_PHY_TYPE_PARAM_ULPI 2
/* whether to use the internal or external supply to
* drive the vbus with a ULPI phy. */
#define DWC_PHY_ULPI_INTERNAL_VBUS 0
#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
/* EP type. */
/**
* @file
* This file contains the interface to the Core Interface Layer.
*/
/**
* The <code>dwc_ep</code> structure represents the state of a single
* endpoint when acting in device mode. It contains the data items
* needed for an endpoint to be activated and transfer packets.
*/
typedef struct dwc_ep {
/** EP number used for register address lookup */
uint8_t num;
/** EP direction 0 = OUT */
unsigned is_in : 1;
/** EP active. */
unsigned active : 1;
/** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
unsigned tx_fifo_num : 4;
/** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
unsigned type : 2;
#define DWC_OTG_EP_TYPE_CONTROL 0
#define DWC_OTG_EP_TYPE_ISOC 1
#define DWC_OTG_EP_TYPE_BULK 2
#define DWC_OTG_EP_TYPE_INTR 3
/** DATA start PID for INTR and BULK EP */
unsigned data_pid_start : 1;
/** Frame (even/odd) for ISOC EP */
unsigned even_odd_frame : 1;
/** Max Packet bytes */
unsigned maxpacket : 11;
/** @name Transfer state */
/** @{ */
/**
* Pointer to the beginning of the transfer buffer -- do not modify
* during transfer.
*/
uint32_t dma_addr;
uint8_t *start_xfer_buff;
/** pointer to the transfer buffer */
uint8_t *xfer_buff;
/** Number of bytes to transfer */
unsigned xfer_len : 19;
/** Number of bytes transferred. */
unsigned xfer_count : 19;
/** Sent ZLP */
unsigned sent_zlp : 1;
/** Total len for control transfer */
unsigned total_len : 19;
/** stall clear flag */
unsigned stall_clear_flag : 1;
/** @} */
} dwc_ep_t;
/*
* Reasons for halting a host channel.
*/
typedef enum dwc_otg_halt_status {
DWC_OTG_HC_XFER_NO_HALT_STATUS,
DWC_OTG_HC_XFER_COMPLETE,
DWC_OTG_HC_XFER_URB_COMPLETE,
DWC_OTG_HC_XFER_ACK,
DWC_OTG_HC_XFER_NAK,
DWC_OTG_HC_XFER_NYET,
DWC_OTG_HC_XFER_STALL,
DWC_OTG_HC_XFER_XACT_ERR,
DWC_OTG_HC_XFER_FRAME_OVERRUN,
DWC_OTG_HC_XFER_BABBLE_ERR,
DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
DWC_OTG_HC_XFER_AHB_ERR,
DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
DWC_OTG_HC_XFER_URB_DEQUEUE
} dwc_otg_halt_status_e;
/**
* Host channel descriptor. This structure represents the state of a single
* host channel when acting in host mode. It contains the data items needed to
* transfer packets to an endpoint via a host channel.
*/
typedef struct dwc_hc {
/** Host channel number used for register address lookup */
uint8_t hc_num;
/** Device to access */
unsigned dev_addr : 7;
/** EP to access */
unsigned ep_num : 4;
/** EP direction. 0: OUT, 1: IN */
unsigned ep_is_in : 1;
/**
* EP speed.
* One of the following values:
* - DWC_OTG_EP_SPEED_LOW
* - DWC_OTG_EP_SPEED_FULL
* - DWC_OTG_EP_SPEED_HIGH
*/
unsigned speed : 2;
#define DWC_OTG_EP_SPEED_LOW 0
#define DWC_OTG_EP_SPEED_FULL 1
#define DWC_OTG_EP_SPEED_HIGH 2
/**
* Endpoint type.
* One of the following values:
* - DWC_OTG_EP_TYPE_CONTROL: 0
* - DWC_OTG_EP_TYPE_ISOC: 1
* - DWC_OTG_EP_TYPE_BULK: 2
* - DWC_OTG_EP_TYPE_INTR: 3
*/
unsigned ep_type : 2;
/** Max packet size in bytes */
unsigned max_packet : 11;
/**
* PID for initial transaction.
* 0: DATA0,<br>
* 1: DATA2,<br>
* 2: DATA1,<br>
* 3: MDATA (non-Control EP),
* SETUP (Control EP)
*/
unsigned data_pid_start : 2;
#define DWC_OTG_HC_PID_DATA0 0
#define DWC_OTG_HC_PID_DATA2 1
#define DWC_OTG_HC_PID_DATA1 2
#define DWC_OTG_HC_PID_MDATA 3
#define DWC_OTG_HC_PID_SETUP 3
/** Number of periodic transactions per (micro)frame */
unsigned multi_count: 2;
/** @name Transfer State */
/** @{ */
/** Pointer to the current transfer buffer position. */
uint8_t *xfer_buff;
/** Total number of bytes to transfer. */
uint32_t xfer_len;
/** Number of bytes transferred so far. */
uint32_t xfer_count;
/** Packet count at start of transfer.*/
uint16_t start_pkt_count;
/**
* Flag to indicate whether the transfer has been started. Set to 1 if
* it has been started, 0 otherwise.
*/
uint8_t xfer_started;
/**
* Set to 1 to indicate that a PING request should be issued on this
* channel. If 0, process normally.
*/
uint8_t do_ping;
/**
* Set to 1 to indicate that the error count for this transaction is
* non-zero. Set to 0 if the error count is 0.
*/
uint8_t error_state;
/**
* Set to 1 to indicate that this channel should be halted the next
* time a request is queued for the channel. This is necessary in
* slave mode if no request queue space is available when an attempt
* is made to halt the channel.
*/
uint8_t halt_on_queue;
/**
* Set to 1 if the host channel has been halted, but the core is not
* finished flushing queued requests. Otherwise 0.
*/
uint8_t halt_pending;
/**
* Reason for halting the host channel.
*/
dwc_otg_halt_status_e halt_status;
/*
* Split settings for the host channel
*/
uint8_t do_split; /**< Enable split for the channel */
uint8_t complete_split; /**< Enable complete split */
uint8_t hub_addr; /**< Address of high speed hub */
uint8_t port_addr; /**< Port of the low/full speed device */
/** Split transaction position
* One of the following values:
* - DWC_HCSPLIT_XACTPOS_MID
* - DWC_HCSPLIT_XACTPOS_BEGIN
* - DWC_HCSPLIT_XACTPOS_END
* - DWC_HCSPLIT_XACTPOS_ALL */
uint8_t xact_pos;
/** Set when the host channel does a short read. */
uint8_t short_read;
/**
* Number of requests issued for this channel since it was assigned to
* the current transfer (not counting PINGs).
*/
uint8_t requests;
/**
* Queue Head for the transfer being processed by this channel.
*/
struct dwc_otg_qh *qh;
/** @} */
/** Entry in list of host channels. */
struct list_head hc_list_entry;
} dwc_hc_t;
/**
* The following parameters may be specified when starting the module. These
* parameters define how the DWC_otg controller should be configured.
* Parameter values are passed to the CIL initialization function
* dwc_otg_cil_init.
*/
typedef struct dwc_otg_core_params
{
int32_t opt;
//#define dwc_param_opt_default 1
/**
* Specifies the OTG capabilities. The driver will automatically
* detect the value for this parameter if none is specified.
* 0 - HNP and SRP capable (default)
* 1 - SRP Only capable
* 2 - No HNP/SRP capable
*/
int32_t otg_cap;
#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
/**
* Specifies whether to use slave or DMA mode for accessing the data
* FIFOs. The driver will automatically detect the value for this
* parameter if none is specified.
* 0 - Slave
* 1 - DMA (default, if available)
*/
int32_t dma_enable;
//#define dwc_param_dma_enable_default 1
/** The DMA Burst size (applicable only for External DMA
* Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
*/
int32_t dma_burst_size; /* Translate this to GAHBCFG values */
//#define dwc_param_dma_burst_size_default 32
/**
* Specifies the maximum speed of operation in host and device mode.
* The actual speed depends on the speed of the attached device and
* the value of phy_type. The actual speed depends on the speed of the
* attached device.
* 0 - High Speed (default)
* 1 - Full Speed
*/
int32_t speed;
//#define dwc_param_speed_default 0
#define DWC_SPEED_PARAM_HIGH 0
#define DWC_SPEED_PARAM_FULL 1
/** Specifies whether low power mode is supported when attached
* to a Full Speed or Low Speed device in host mode.
* 0 - Don't support low power mode (default)
* 1 - Support low power mode
*/
int32_t host_support_fs_ls_low_power;
//#define dwc_param_host_support_fs_ls_low_power_default 0
/** Specifies the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. This parameter is applicable only if
* HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
* then defaults to 6 MHZ otherwise 48 MHZ.
*
* 0 - 48 MHz
* 1 - 6 MHz
*/
int32_t host_ls_low_power_phy_clk;
//#define dwc_param_host_ls_low_power_phy_clk_default 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
/**
* 0 - Use cC FIFO size parameters
* 1 - Allow dynamic FIFO sizing (default)
*/
int32_t enable_dynamic_fifo;
//#define dwc_param_enable_dynamic_fifo_default 1
/** Total number of 4-byte words in the data FIFO memory. This
* memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
* Tx FIFOs.
* 32 to 32768 (default 8192)
* Note: The total FIFO memory depth in the FPGA configuration is 8192.
*/
int32_t data_fifo_size;
//#define dwc_param_data_fifo_size_default 8192
/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1064)
*/
int32_t dev_rx_fifo_size;
//#define dwc_param_dev_rx_fifo_size_default 1064
/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
* when dynamic FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t dev_nperio_tx_fifo_size;
//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in each of the periodic Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
//#define dwc_param_dev_perio_tx_fifo_size_default 256
/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t host_rx_fifo_size;
//#define dwc_param_host_rx_fifo_size_default 1024
/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
* when Dynamic FIFO sizing is enabled in the core.
* 16 to 32768 (default 1024)
*/
int32_t host_nperio_tx_fifo_size;
//#define dwc_param_host_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t host_perio_tx_fifo_size;
//#define dwc_param_host_perio_tx_fifo_size_default 1024
/** The maximum transfer size supported in bytes.
* 2047 to 65,535 (default 65,535)
*/
int32_t max_transfer_size;
//#define dwc_param_max_transfer_size_default 65535
/** The maximum number of packets in a transfer.
* 15 to 511 (default 511)
*/
int32_t max_packet_count;
//#define dwc_param_max_packet_count_default 511
/** The number of host channel registers to use.
* 1 to 16 (default 12)
* Note: The FPGA configuration supports a maximum of 12 host channels.
*/
int32_t host_channels;
//#define dwc_param_host_channels_default 12
/** The number of endpoints in addition to EP0 available for device
* mode operations.
* 1 to 15 (default 6 IN and OUT)
* Note: The FPGA configuration supports a maximum of 6 IN and OUT
* endpoints in addition to EP0.
*/
int32_t dev_endpoints;
//#define dwc_param_dev_endpoints_default 6
/**
* Specifies the type of PHY interface to use. By default, the driver
* will automatically detect the phy_type.
*
* 0 - Full Speed PHY
* 1 - UTMI+ (default)
* 2 - ULPI
*/
int32_t phy_type;
#define DWC_PHY_TYPE_PARAM_FS 0
#define DWC_PHY_TYPE_PARAM_UTMI 1
#define DWC_PHY_TYPE_PARAM_ULPI 2
//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
/**
* Specifies the UTMI+ Data Width. This parameter is
* applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
* PHY_TYPE, this parameter indicates the data width between
* the MAC and the ULPI Wrapper.) Also, this parameter is
* applicable only if the OTG_HSPHY_WIDTH cC parameter was set
* to "8 and 16 bits", meaning that the core has been
* configured to work at either data path width.
*
* 8 or 16 bits (default 16)
*/
int32_t phy_utmi_width;
//#define dwc_param_phy_utmi_width_default 16
/**
* Specifies whether the ULPI operates at double or single
* data rate. This parameter is only applicable if PHY_TYPE is
* ULPI.
*
* 0 - single data rate ULPI interface with 8 bit wide data
* bus (default)
* 1 - double data rate ULPI interface with 4 bit wide data
* bus
*/
int32_t phy_ulpi_ddr;
//#define dwc_param_phy_ulpi_ddr_default 0
/**
* Specifies whether to use the internal or external supply to
* drive the vbus with a ULPI phy.
*/
int32_t phy_ulpi_ext_vbus;
#define DWC_PHY_ULPI_INTERNAL_VBUS 0
#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
/**
* Specifies whether to use the I2Cinterface for full speed PHY. This
* parameter is only applicable if PHY_TYPE is FS.
* 0 - No (default)
* 1 - Yes
*/
int32_t i2c_enable;
//#define dwc_param_i2c_enable_default 0
int32_t ulpi_fs_ls;
//#define dwc_param_ulpi_fs_ls_default 0
int32_t ts_dline;
//#define dwc_param_ts_dline_default 0
/**
* Specifies whether dedicated transmit FIFOs are
* enabled for non periodic IN endpoints in device mode
* 0 - No
* 1 - Yes
*/
int32_t en_multiple_tx_fifo;
#define dwc_param_en_multiple_tx_fifo_default 1
/** Number of 4-byte words in each of the Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
#define dwc_param_dev_tx_fifo_size_default 256
/** Thresholding enable flag-
* bit 0 - enable non-ISO Tx thresholding
* bit 1 - enable ISO Tx thresholding
* bit 2 - enable Rx thresholding
*/
uint32_t thr_ctl;
#define dwc_param_thr_ctl_default 0
/** Thresholding length for Tx
* FIFOs in 32 bit DWORDs
*/
uint32_t tx_thr_length;
#define dwc_param_tx_thr_length_default 64
/** Thresholding length for Rx
* FIFOs in 32 bit DWORDs
*/
uint32_t rx_thr_length;
#define dwc_param_rx_thr_length_default 64
} dwc_otg_core_params_t;
#ifdef DEBUG
struct dwc_otg_core_if;
typedef struct hc_xfer_info
{
struct dwc_otg_core_if *core_if;
dwc_hc_t *hc;
} hc_xfer_info_t;
#endif
/**
* The <code>dwc_otg_core_if</code> structure contains information needed to manage
* the DWC_otg controller acting in either host or device mode. It
* represents the programming view of the controller as a whole.
*/
typedef struct dwc_otg_core_if
{
/** Parameters that define how the core should be configured.*/
dwc_otg_core_params_t *core_params;
/** Core Global registers starting at offset 000h. */
dwc_otg_core_global_regs_t *core_global_regs;
/** Device-specific information */
dwc_otg_dev_if_t *dev_if;
/** Host-specific information */
dwc_otg_host_if_t *host_if;
/*
* Set to 1 if the core PHY interface bits in USBCFG have been
* initialized.
*/
uint8_t phy_init_done;
/*
* SRP Success flag, set by srp success interrupt in FS I2C mode
*/
uint8_t srp_success;
uint8_t srp_timer_started;
/* Common configuration information */
/** Power and Clock Gating Control Register */
volatile uint32_t *pcgcctl;
#define DWC_OTG_PCGCCTL_OFFSET 0xE00
/** Push/pop addresses for endpoints or host channels.*/
uint32_t *data_fifo[MAX_EPS_CHANNELS];
#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
#define DWC_OTG_DATA_FIFO_SIZE 0x1000
/** Total RAM for FIFOs (Bytes) */
uint16_t total_fifo_size;
/** Size of Rx FIFO (Bytes) */
uint16_t rx_fifo_size;
/** Size of Non-periodic Tx FIFO (Bytes) */
uint16_t nperio_tx_fifo_size;
/** 1 if DMA is enabled, 0 otherwise. */
uint8_t dma_enable;
/** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
uint8_t en_multiple_tx_fifo;
/** Set to 1 if multiple packets of a high-bandwidth transfer is in
* process of being queued */
uint8_t queuing_high_bandwidth;
/** Hardware Configuration -- stored here for convenience.*/
hwcfg1_data_t hwcfg1;
hwcfg2_data_t hwcfg2;
hwcfg3_data_t hwcfg3;
hwcfg4_data_t hwcfg4;
/** The operational State, during transations
* (a_host>>a_peripherial and b_device=>b_host) this may not
* match the core but allows the software to determine
* transitions.
*/
uint8_t op_state;
/**
* Set to 1 if the HCD needs to be restarted on a session request
* interrupt. This is required if no connector ID status change has
* occurred since the HCD was last disconnected.
*/
uint8_t restart_hcd_on_session_req;
/** HCD callbacks */
/** A-Device is a_host */
#define A_HOST (1)
/** A-Device is a_suspend */
#define A_SUSPEND (2)
/** A-Device is a_peripherial */
#define A_PERIPHERAL (3)
/** B-Device is operating as a Peripheral. */
#define B_PERIPHERAL (4)
/** B-Device is operating as a Host. */
#define B_HOST (5)
/** HCD callbacks */
struct dwc_otg_cil_callbacks *hcd_cb;
/** PCD callbacks */
struct dwc_otg_cil_callbacks *pcd_cb;
/** Device mode Periodic Tx FIFO Mask */
uint32_t p_tx_msk;
/** Device mode Periodic Tx FIFO Mask */
uint32_t tx_msk;
#ifdef DEBUG
uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
#if 1 // winder
uint32_t hfnum_7_samples;
uint32_t hfnum_7_frrem_accum;
uint32_t hfnum_0_samples;
uint32_t hfnum_0_frrem_accum;
uint32_t hfnum_other_samples;
uint32_t hfnum_other_frrem_accum;
#else
uint32_t hfnum_7_samples;
uint64_t hfnum_7_frrem_accum;
uint32_t hfnum_0_samples;
uint64_t hfnum_0_frrem_accum;
uint32_t hfnum_other_samples;
uint64_t hfnum_other_frrem_accum;
#endif
resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */
#endif
} dwc_otg_core_if_t;
/*
* The following functions support initialization of the CIL driver component
* and the DWC_otg controller.
*/
extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
dwc_otg_core_params_t *_core_params);
extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
/** @name Device CIL Functions
* The following functions support managing the DWC_otg controller in device
* mode.
*/
/**@{*/
extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
/**@}*/
/** @name Host CIL Functions
* The following functions support managing the DWC_otg controller in host
* mode.
*/
/**@{*/
extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
dwc_hc_t *_hc,
dwc_otg_halt_status_e _halt_status);
extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
/**
* This function Reads HPRT0 in preparation to modify. It keeps the
* WC bits 0 so that if they are read as 1, they won't clear when you
* write it back
*/
static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
{
hprt0_data_t hprt0;
hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
hprt0.b.prtena = 0;
hprt0.b.prtconndet = 0;
hprt0.b.prtenchng = 0;
hprt0.b.prtovrcurrchng = 0;
return hprt0.d32;
}
extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
/**@}*/
/** @name Common CIL Functions
* The following functions support managing the DWC_otg controller in either
* device or host mode.
*/
/**@{*/
extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
uint8_t *dest,
uint16_t bytes);
extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
const int _num );
extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
#define NP_TXFIFO_EMPTY -1
#define MAX_NP_TXREQUEST_Q_SLOTS 8
/**
* This function returns the endpoint number of the request at
* the top of non-periodic TX FIFO, or -1 if the request FIFO is
* empty.
*/
static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) {
gnptxsts_data_t txstatus = {.d32 = 0};
txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ?
-1 : txstatus.b.nptxqtop_chnep);
}
/**
* This function returns the Core Interrupt register.
*/
static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
}
/**
* This function returns the OTG Interrupt register.
*/
static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
}
/**
* This function reads the Device All Endpoints Interrupt register and
* returns the IN endpoint interrupt bits.
*/
static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) {
uint32_t v;
v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
return (v & 0xffff);
}
/**
* This function reads the Device All Endpoints Interrupt register and
* returns the OUT endpoint interrupt bits.
*/
static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) {
uint32_t v;
v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
return ((v & 0xffff0000) >> 16);
}
/**
* This function returns the Device IN EP Interrupt register
*/
static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if,
dwc_ep_t *_ep)
{
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v, msk, emp;
msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
msk |= ((emp >> _ep->num) & 0x1) << 7;
v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk;
/*
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v;
v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) &
dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
*/
return v;
}
/**
* This function returns the Device OUT EP Interrupt register
*/
static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
dwc_ep_t *_ep)
{
dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
uint32_t v;
v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) &
dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
return v;
}
/**
* This function returns the Host All Channel Interrupt register
*/
static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
{
return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
}
static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
{
return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
}
/**
* This function returns the mode of the operation, host or device.
*
* @return 0 - Device Mode, 1 - Host Mode
*/
static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) {
return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
}
static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
{
return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
}
static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
{
return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
}
extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
/**@}*/
/**
* DWC_otg CIL callback structure. This structure allows the HCD and
* PCD to register functions used for starting and stopping the PCD
* and HCD for role change on for a DRD.
*/
typedef struct dwc_otg_cil_callbacks
{
/** Start function for role change */
int (*start) (void *_p);
/** Stop Function for role change */
int (*stop) (void *_p);
/** Disconnect Function for role change */
int (*disconnect) (void *_p);
/** Resume/Remote wakeup Function */
int (*resume_wakeup) (void *_p);
/** Suspend function */
int (*suspend) (void *_p);
/** Session Start (SRP) */
int (*session_start) (void *_p);
/** Pointer passed to start() and stop() */
void *p;
} dwc_otg_cil_callbacks_t;
extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
dwc_otg_cil_callbacks_t *_cb,
void *_p);
extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
dwc_otg_cil_callbacks_t *_cb,
void *_p);
#endif

58
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h Normal file
View File

@@ -0,0 +1,58 @@
/******************************************************************************
**
** FILE NAME : dwc_otg_cil_ifx.h
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 07 Sep. 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Default param value.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 April 2007 Sung Winder Initiate Version
*******************************************************************************/
#if !defined(__DWC_OTG_CIL_IFX_H__)
#define __DWC_OTG_CIL_IFX_H__
/* ================ Default param value ================== */
#define dwc_param_opt_default 1
#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
#define dwc_param_dma_enable_default 1
#define dwc_param_dma_burst_size_default 32
#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH
#define dwc_param_host_support_fs_ls_low_power_default 0
#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ
#define dwc_param_enable_dynamic_fifo_default 1
#define dwc_param_data_fifo_size_default 2048
#define dwc_param_dev_rx_fifo_size_default 1024
#define dwc_param_dev_nperio_tx_fifo_size_default 1024
#define dwc_param_dev_perio_tx_fifo_size_default 768
#define dwc_param_host_rx_fifo_size_default 640
#define dwc_param_host_nperio_tx_fifo_size_default 640
#define dwc_param_host_perio_tx_fifo_size_default 768
#define dwc_param_max_transfer_size_default 65535
#define dwc_param_max_packet_count_default 511
#define dwc_param_host_channels_default 16
#define dwc_param_dev_endpoints_default 6
#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
#define dwc_param_phy_utmi_width_default 16
#define dwc_param_phy_ulpi_ddr_default 0
#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
#define dwc_param_i2c_enable_default 0
#define dwc_param_ulpi_fs_ls_default 0
#define dwc_param_ts_dline_default 0
/* ======================================================= */
#endif // __DWC_OTG_CIL_IFX_H__

708
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_cil_intr.c Normal file
View File

@@ -0,0 +1,708 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil_intr.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 553126 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
/** @file
*
* The Core Interface Layer provides basic services for accessing and
* managing the DWC_otg hardware. These services are used by both the
* Host Controller Driver and the Peripheral Controller Driver.
*
* This file contains the Common Interrupt handlers.
*/
#include "dwc_otg_plat.h"
#include "dwc_otg_regs.h"
#include "dwc_otg_cil.h"
#ifdef DEBUG
inline const char *op_state_str( dwc_otg_core_if_t *_core_if )
{
return (_core_if->op_state==A_HOST?"a_host":
(_core_if->op_state==A_SUSPEND?"a_suspend":
(_core_if->op_state==A_PERIPHERAL?"a_peripheral":
(_core_if->op_state==B_PERIPHERAL?"b_peripheral":
(_core_if->op_state==B_HOST?"b_host":
"unknown")))));
}
#endif
/** This function will log a debug message
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
dwc_otg_mode(_core_if) ? "Host" : "Device");
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.modemismatch = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/** Start the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
_core_if->hcd_cb->start( _core_if->hcd_cb->p );
}
}
/** Stop the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_stop( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
_core_if->hcd_cb->stop( _core_if->hcd_cb->p );
}
}
/** Disconnect the HCD. Helper function for using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_disconnect( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
_core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
}
}
/** Inform the HCD the a New Session has begun. Helper function for
* using the HCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void hcd_session_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->hcd_cb && _core_if->hcd_cb->session_start) {
_core_if->hcd_cb->session_start( _core_if->hcd_cb->p );
}
}
/** Start the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_start( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->start ) {
_core_if->pcd_cb->start( _core_if->pcd_cb->p );
}
}
/** Stop the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_stop( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->stop ) {
_core_if->pcd_cb->stop( _core_if->pcd_cb->p );
}
}
/** Suspend the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_suspend( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->suspend ) {
_core_if->pcd_cb->suspend( _core_if->pcd_cb->p );
}
}
/** Resume the PCD. Helper function for using the PCD callbacks.
*
* @param _core_if Programming view of DWC_otg controller.
*/
static inline void pcd_resume( dwc_otg_core_if_t *_core_if )
{
if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup ) {
_core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
}
}
/**
* This function handles the OTG Interrupts. It reads the OTG
* Interrupt Register (GOTGINT) to determine what interrupt has
* occurred.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *_core_if)
{
dwc_otg_core_global_regs_t *global_regs =
_core_if->core_global_regs;
gotgint_data_t gotgint;
gotgctl_data_t gotgctl;
gintmsk_data_t gintmsk;
gotgint.d32 = dwc_read_reg32( &global_regs->gotgint);
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
op_state_str(_core_if));
//DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32 );
if (gotgint.b.sesenddet) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Session End Detected++ (%s)\n",
op_state_str(_core_if));
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
if (_core_if->op_state == B_HOST) {
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else {
/* If not B_HOST and Device HNP still set. HNP
* Did not succeed!*/
if (gotgctl.b.devhnpen) {
DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
DWC_ERROR( "Device Not Connected/Responding!\n" );
}
/* If Session End Detected the B-Cable has
* been disconnected. */
/* Reset PCD and Gadget driver to a
* clean state. */
pcd_stop(_core_if);
}
gotgctl.d32 = 0;
gotgctl.b.devhnpen = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
}
if (gotgint.b.sesreqsucstschng) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Session Reqeust Success Status Change++\n");
gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
if (gotgctl.b.sesreqscs) {
if ((_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
(_core_if->core_params->i2c_enable)) {
_core_if->srp_success = 1;
}
else {
pcd_resume( _core_if );
/* Clear Session Request */
gotgctl.d32 = 0;
gotgctl.b.sesreq = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
}
}
}
if (gotgint.b.hstnegsucstschng) {
/* Print statements during the HNP interrupt handling
* can cause it to fail.*/
gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
if (gotgctl.b.hstnegscs) {
if (dwc_otg_is_host_mode(_core_if) ) {
_core_if->op_state = B_HOST;
/*
* Need to disable SOF interrupt immediately.
* When switching from device to host, the PCD
* interrupt handler won't handle the
* interrupt if host mode is already set. The
* HCD interrupt handler won't get called if
* the HCD state is HALT. This means that the
* interrupt does not get handled and Linux
* complains loudly.
*/
gintmsk.d32 = 0;
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&global_regs->gintmsk,
gintmsk.d32, 0);
pcd_stop(_core_if);
/*
* Initialize the Core for Host mode.
*/
hcd_start( _core_if );
_core_if->op_state = B_HOST;
}
} else {
gotgctl.d32 = 0;
gotgctl.b.hnpreq = 1;
gotgctl.b.devhnpen = 1;
dwc_modify_reg32( &global_regs->gotgctl,
gotgctl.d32, 0);
DWC_DEBUGPL( DBG_ANY, "HNP Failed\n");
DWC_ERROR( "Device Not Connected/Responding\n" );
}
}
if (gotgint.b.hstnegdet) {
/* The disconnect interrupt is set at the same time as
* Host Negotiation Detected. During the mode
* switch all interrupts are cleared so the disconnect
* interrupt handler will not get executed.
*/
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Host Negotiation Detected++ (%s)\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
if (dwc_otg_is_device_mode(_core_if)){
DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",_core_if->op_state);
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = A_PERIPHERAL;
} else {
/*
* Need to disable SOF interrupt immediately. When
* switching from device to host, the PCD interrupt
* handler won't handle the interrupt if host mode is
* already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that
* the interrupt does not get handled and Linux
* complains loudly.
*/
gintmsk.d32 = 0;
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&global_regs->gintmsk,
gintmsk.d32, 0);
pcd_stop( _core_if );
hcd_start( _core_if );
_core_if->op_state = A_HOST;
}
}
if (gotgint.b.adevtoutchng) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"A-Device Timeout Change++\n");
}
if (gotgint.b.debdone) {
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
"Debounce Done++\n");
}
/* Clear GOTGINT */
dwc_write_reg32 (&_core_if->core_global_regs->gotgint, gotgint.d32);
return 1;
}
/**
* This function handles the Connector ID Status Change Interrupt. It
* reads the OTG Interrupt Register (GOTCTL) to determine whether this
* is a Device to Host Mode transition or a Host Mode to Device
* Transition.
*
* This only occurs when the cable is connected/removed from the PHY
* connector.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *_core_if)
{
uint32_t count = 0;
gintsts_data_t gintsts = { .d32 = 0 };
gintmsk_data_t gintmsk = { .d32 = 0 };
gotgctl_data_t gotgctl = { .d32 = 0 };
/*
* Need to disable SOF interrupt immediately. If switching from device
* to host, the PCD interrupt handler won't handle the interrupt if
* host mode is already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that the interrupt does
* not get handled and Linux complains loudly.
*/
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts) {
/* Wait for switch to device mode. */
while (!dwc_otg_is_device_mode(_core_if) ){
DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
MDELAY(100);
if (++count > 10000) *(uint32_t*)NULL=0;
}
_core_if->op_state = B_PERIPHERAL;
dwc_otg_core_init(_core_if);
dwc_otg_enable_global_interrupts(_core_if);
pcd_start( _core_if );
} else {
/* A-Device connector (Host Mode) */
while (!dwc_otg_is_host_mode(_core_if) ) {
DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
MDELAY(100);
if (++count > 10000) *(uint32_t*)NULL=0;
}
_core_if->op_state = A_HOST;
/*
* Initialize the Core for Host mode.
*/
dwc_otg_core_init(_core_if);
dwc_otg_enable_global_interrupts(_core_if);
hcd_start( _core_if );
}
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device is initiating the Session
* Request Protocol to request the host to turn on bus power so a new
* session can begin. The handler responds by turning on bus power. If
* the DWC_otg controller is in low power mode, the handler brings the
* controller out of low power mode before turning on bus power.
*
* @param _core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_session_req_intr( dwc_otg_core_if_t *_core_if )
{
#ifndef DWC_HOST_ONLY // winder
hprt0_data_t hprt0;
#endif
gintsts_data_t gintsts;
#ifndef DWC_HOST_ONLY
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
if (dwc_otg_is_device_mode(_core_if) ) {
DWC_PRINT("SRP: Device mode\n");
} else {
DWC_PRINT("SRP: Host mode\n");
/* Turn on the port power bit. */
hprt0.d32 = dwc_otg_read_hprt0( _core_if );
hprt0.b.prtpwr = 1;
dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
/* Start the Connection timer. So a message can be displayed
* if connect does not occur within 10 seconds. */
hcd_session_start( _core_if );
}
#endif
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that the DWC_otg controller has detected a
* resume or remote wakeup sequence. If the DWC_otg controller is in
* low power mode, the handler must brings the controller out of low
* power mode. The controller automatically begins resume
* signaling. The handler schedules a time to stop resume signaling.
*/
int32_t dwc_otg_handle_wakeup_detected_intr( dwc_otg_core_if_t *_core_if )
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
if (dwc_otg_is_device_mode(_core_if) ) {
dctl_data_t dctl = {.d32=0};
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts));
#ifdef PARTIAL_POWER_DOWN
if (_core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32=0};
power.d32 = dwc_read_reg32( _core_if->pcgcctl );
DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
power.b.stoppclk = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.pwrclmp = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 0;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
}
#endif
/* Clear the Remote Wakeup Signalling */
dctl.b.rmtwkupsig = 1;
dwc_modify_reg32( &_core_if->dev_if->dev_global_regs->dctl,
dctl.d32, 0 );
if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) {
_core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
}
} else {
/*
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
* so that OPT tests pass with all PHYs).
*/
hprt0_data_t hprt0 = {.d32=0};
pcgcctl_data_t pcgcctl = {.d32=0};
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0);
UDELAY(10);
/* Now wait for 70 ms. */
hprt0.d32 = dwc_otg_read_hprt0( _core_if );
DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
MDELAY(70);
hprt0.b.prtres = 0; /* Resume */
dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(_core_if->host_if->hprt0));
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.wkupintr = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device has been disconnected from
* the root port.
*/
int32_t dwc_otg_handle_disconnect_intr( dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
(dwc_otg_is_host_mode(_core_if)?"Host":"Device"),
op_state_str(_core_if));
/** @todo Consolidate this if statement. */
#ifndef DWC_HOST_ONLY
if (_core_if->op_state == B_HOST) {
/* If in device mode Disconnect and stop the HCD, then
* start the PCD. */
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else if (dwc_otg_is_device_mode(_core_if)) {
gotgctl_data_t gotgctl = { .d32 = 0 };
gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
if (gotgctl.b.hstsethnpen==1) {
/* Do nothing, if HNP in process the OTG
* interrupt "Host Negotiation Detected"
* interrupt will do the mode switch.
*/
} else if (gotgctl.b.devhnpen == 0) {
/* If in device mode Disconnect and stop the HCD, then
* start the PCD. */
hcd_disconnect( _core_if );
pcd_start( _core_if );
_core_if->op_state = B_PERIPHERAL;
} else {
DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
}
} else {
if (_core_if->op_state == A_HOST) {
/* A-Cable still connected but device disconnected. */
hcd_disconnect( _core_if );
}
}
#endif
/* Without OTG, we should use the disconnect function!? winder added.*/
#if 1 // NO OTG, so host only!!
hcd_disconnect( _core_if );
#endif
gintsts.d32 = 0;
gintsts.b.disconnect = 1;
dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that SUSPEND state has been detected on
* the USB.
*
* For HNP the USB Suspend interrupt signals the change from
* "a_peripheral" to "a_host".
*
* When power management is enabled the core will be put in low power
* mode.
*/
int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *_core_if )
{
dsts_data_t dsts;
gintsts_data_t gintsts;
//805141:<IFTW-fchang>.removed DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
if (dwc_otg_is_device_mode( _core_if ) ) {
/* Check the Device status register to determine if the Suspend
* state is active. */
dsts.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts);
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
"HWCFG4.power Optimize=%d\n",
dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz);
#ifdef PARTIAL_POWER_DOWN
/** @todo Add a module parameter for power management. */
if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32=0};
DWC_DEBUGPL(DBG_CIL, "suspend\n");
power.b.pwrclmp = 1;
dwc_write_reg32( _core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 1;
dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
power.b.stoppclk = 1;
dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
} else {
DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
}
#endif
/* PCD callback for suspend. */
pcd_suspend(_core_if);
} else {
if (_core_if->op_state == A_PERIPHERAL) {
DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
/* Clear the a_peripheral flag, back to a_host. */
pcd_stop( _core_if );
hcd_start( _core_if );
_core_if->op_state = A_HOST;
}
}
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.usbsuspend = 1;
dwc_write_reg32( &_core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This function returns the Core Interrupt register.
*/
static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *_core_if)
{
gintsts_data_t gintsts;
gintmsk_data_t gintmsk;
gintmsk_data_t gintmsk_common = {.d32=0};
gintmsk_common.b.wkupintr = 1;
gintmsk_common.b.sessreqintr = 1;
gintmsk_common.b.conidstschng = 1;
gintmsk_common.b.otgintr = 1;
gintmsk_common.b.modemismatch = 1;
gintmsk_common.b.disconnect = 1;
gintmsk_common.b.usbsuspend = 1;
/** @todo: The port interrupt occurs while in device
* mode. Added code to CIL to clear the interrupt for now!
*/
gintmsk_common.b.portintr = 1;
gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts);
gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk);
#ifdef DEBUG
/* if any common interrupts set */
if (gintsts.d32 & gintmsk_common.d32) {
DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
gintsts.d32, gintmsk.d32);
}
#endif
return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
}
/**
* Common interrupt handler.
*
* The common interrupts are those that occur in both Host and Device mode.
* This handler handles the following interrupts:
* - Mode Mismatch Interrupt
* - Disconnect Interrupt
* - OTG Interrupt
* - Connector ID Status Change Interrupt
* - Session Request Interrupt.
* - Resume / Remote Wakeup Detected Interrupt.
*
*/
extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if )
{
int retval = 0;
gintsts_data_t gintsts;
gintsts.d32 = dwc_otg_read_common_intr(_core_if);
if (gintsts.b.modemismatch) {
retval |= dwc_otg_handle_mode_mismatch_intr( _core_if );
}
if (gintsts.b.otgintr) {
retval |= dwc_otg_handle_otg_intr( _core_if );
}
if (gintsts.b.conidstschng) {
retval |= dwc_otg_handle_conn_id_status_change_intr( _core_if );
}
if (gintsts.b.disconnect) {
retval |= dwc_otg_handle_disconnect_intr( _core_if );
}
if (gintsts.b.sessreqintr) {
retval |= dwc_otg_handle_session_req_intr( _core_if );
}
if (gintsts.b.wkupintr) {
retval |= dwc_otg_handle_wakeup_detected_intr( _core_if );
}
if (gintsts.b.usbsuspend) {
retval |= dwc_otg_handle_usb_suspend_intr( _core_if );
}
if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) {
/* The port interrupt occurs while in device mode with HPRT0
* Port Enable/Disable.
*/
gintsts.d32 = 0;
gintsts.b.portintr = 1;
dwc_write_reg32(&_core_if->core_global_regs->gintsts,
gintsts.d32);
retval |= 1;
}
return retval;
}

1277
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_driver.c Normal file
View File

File diff suppressed because it is too large Load Diff

84
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_driver.h Normal file
View File

@@ -0,0 +1,84 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510275 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_DRIVER_H__)
#define __DWC_OTG_DRIVER_H__
/** @file
* This file contains the interface to the Linux driver.
*/
#include "dwc_otg_cil.h"
/* Type declarations */
struct dwc_otg_pcd;
struct dwc_otg_hcd;
/**
* This structure is a wrapper that encapsulates the driver components used to
* manage a single DWC_otg controller.
*/
typedef struct dwc_otg_device
{
/** Base address returned from ioremap() */
void *base;
/** Pointer to the core interface structure. */
dwc_otg_core_if_t *core_if;
/** Register offset for Diagnostic API.*/
uint32_t reg_offset;
/** Pointer to the PCD structure. */
struct dwc_otg_pcd *pcd;
/** Pointer to the HCD structure. */
struct dwc_otg_hcd *hcd;
/** Flag to indicate whether the common IRQ handler is installed. */
uint8_t common_irq_installed;
/** Interrupt request number. */
unsigned int irq;
/** Physical address of Control and Status registers, used by
* release_mem_region().
*/
resource_size_t phys_addr;
/** Length of memory region, used by release_mem_region(). */
unsigned long base_len;
} dwc_otg_device_t;
//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg)
#endif

2870
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_hcd.c Normal file
View File

File diff suppressed because it is too large Load Diff

676
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_hcd.h Normal file
View File

@@ -0,0 +1,676 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef DWC_DEVICE_ONLY
#if !defined(__DWC_HCD_H__)
#define __DWC_HCD_H__
#include <linux/list.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
struct lm_device;
struct dwc_otg_device;
#include "dwc_otg_cil.h"
//#include "dwc_otg_ifx.h" // winder
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Host Contoller Driver (HCD).
*
* The Host Controller Driver (HCD) is responsible for translating requests
* from the USB Driver into the appropriate actions on the DWC_otg controller.
* It isolates the USBD from the specifics of the controller by providing an
* API to the USBD.
*/
/**
* Phases for control transfers.
*/
typedef enum dwc_otg_control_phase {
DWC_OTG_CONTROL_SETUP,
DWC_OTG_CONTROL_DATA,
DWC_OTG_CONTROL_STATUS
} dwc_otg_control_phase_e;
/** Transaction types. */
typedef enum dwc_otg_transaction_type {
DWC_OTG_TRANSACTION_NONE,
DWC_OTG_TRANSACTION_PERIODIC,
DWC_OTG_TRANSACTION_NON_PERIODIC,
DWC_OTG_TRANSACTION_ALL
} dwc_otg_transaction_type_e;
/**
* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
* interrupt, or isochronous transfer. A single QTD is created for each URB
* (of one of these types) submitted to the HCD. The transfer associated with
* a QTD may require one or multiple transactions.
*
* A QTD is linked to a Queue Head, which is entered in either the
* non-periodic or periodic schedule for execution. When a QTD is chosen for
* execution, some or all of its transactions may be executed. After
* execution, the state of the QTD is updated. The QTD may be retired if all
* its transactions are complete or if an error occurred. Otherwise, it
* remains in the schedule so more transactions can be executed later.
*/
struct dwc_otg_qh;
typedef struct dwc_otg_qtd {
/**
* Determines the PID of the next data packet for the data phase of
* control transfers. Ignored for other transfer types.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Current phase for control transfers (Setup, Data, or Status). */
dwc_otg_control_phase_e control_phase;
/** Keep track of the current split type
* for FS/LS endpoints on a HS Hub */
uint8_t complete_split;
/** How many bytes transferred during SSPLIT OUT */
uint32_t ssplit_out_xfer_count;
/**
* Holds the number of bus errors that have occurred for a transaction
* within this transfer.
*/
uint8_t error_count;
/**
* Index of the next frame descriptor for an isochronous transfer. A
* frame descriptor describes the buffer position and length of the
* data to be transferred in the next scheduled (micro)frame of an
* isochronous transfer. It also holds status for that transaction.
* The frame index starts at 0.
*/
int isoc_frame_index;
/** Position of the ISOC split on full/low speed */
uint8_t isoc_split_pos;
/** Position of the ISOC split in the buffer for the current frame */
uint16_t isoc_split_offset;
/** URB for this transfer */
struct urb *urb;
/** This list of QTDs */
struct list_head qtd_list_entry;
/* Field to track the qh pointer */
struct dwc_otg_qh *qtd_qh_ptr;
} dwc_otg_qtd_t;
/**
* A Queue Head (QH) holds the static characteristics of an endpoint and
* maintains a list of transfers (QTDs) for that endpoint. A QH structure may
* be entered in either the non-periodic or periodic schedule.
*/
typedef struct dwc_otg_qh {
/**
* Endpoint type.
* One of the following values:
* - USB_ENDPOINT_XFER_CONTROL
* - USB_ENDPOINT_XFER_ISOC
* - USB_ENDPOINT_XFER_BULK
* - USB_ENDPOINT_XFER_INT
*/
uint8_t ep_type;
uint8_t ep_is_in;
/** wMaxPacketSize Field of Endpoint Descriptor. */
uint16_t maxp;
/**
* Determines the PID of the next data packet for non-control
* transfers. Ignored for control transfers.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Ping state if 1. */
uint8_t ping_state;
/**
* List of QTDs for this QH.
*/
struct list_head qtd_list;
/** Host channel currently processing transfers for this QH. */
dwc_hc_t *channel;
/** QTD currently assigned to a host channel for this QH. */
dwc_otg_qtd_t *qtd_in_process;
/** Full/low speed endpoint on high-speed hub requires split. */
uint8_t do_split;
/** @name Periodic schedule information */
/** @{ */
/** Bandwidth in microseconds per (micro)frame. */
uint8_t usecs;
/** Interval between transfers in (micro)frames. */
uint16_t interval;
/**
* (micro)frame to initialize a periodic transfer. The transfer
* executes in the following (micro)frame.
*/
uint16_t sched_frame;
/** (micro)frame at which last start split was initialized. */
uint16_t start_split_frame;
/** @} */
uint16_t speed;
uint16_t frame_usecs[8];
/** Entry for QH in either the periodic or non-periodic schedule. */
struct list_head qh_list_entry;
} dwc_otg_qh_t;
/**
* This structure holds the state of the HCD, including the non-periodic and
* periodic schedules.
*/
typedef struct dwc_otg_hcd {
spinlock_t lock;
/** DWC OTG Core Interface Layer */
dwc_otg_core_if_t *core_if;
/** Internal DWC HCD Flags */
volatile union dwc_otg_hcd_internal_flags {
uint32_t d32;
struct {
unsigned port_connect_status_change : 1;
unsigned port_connect_status : 1;
unsigned port_reset_change : 1;
unsigned port_enable_change : 1;
unsigned port_suspend_change : 1;
unsigned port_over_current_change : 1;
unsigned reserved : 27;
} b;
} flags;
/**
* Inactive items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are not
* currently assigned to a host channel.
*/
struct list_head non_periodic_sched_inactive;
/**
* Deferred items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are not
* currently assigned to a host channel.
* When we get an NAK, the QH goes here.
*/
struct list_head non_periodic_sched_deferred;
/**
* Active items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are
* currently assigned to a host channel.
*/
struct list_head non_periodic_sched_active;
/**
* Pointer to the next Queue Head to process in the active
* non-periodic schedule.
*/
struct list_head *non_periodic_qh_ptr;
/**
* Inactive items in the periodic schedule. This is a list of QHs for
* periodic transfers that are _not_ scheduled for the next frame.
* Each QH in the list has an interval counter that determines when it
* needs to be scheduled for execution. This scheduling mechanism
* allows only a simple calculation for periodic bandwidth used (i.e.
* must assume that all periodic transfers may need to execute in the
* same frame). However, it greatly simplifies scheduling and should
* be sufficient for the vast majority of OTG hosts, which need to
* connect to a small number of peripherals at one time.
*
* Items move from this list to periodic_sched_ready when the QH
* interval counter is 0 at SOF.
*/
struct list_head periodic_sched_inactive;
/**
* List of periodic QHs that are ready for execution in the next
* frame, but have not yet been assigned to host channels.
*
* Items move from this list to periodic_sched_assigned as host
* channels become available during the current frame.
*/
struct list_head periodic_sched_ready;
/**
* List of periodic QHs to be executed in the next frame that are
* assigned to host channels.
*
* Items move from this list to periodic_sched_queued as the
* transactions for the QH are queued to the DWC_otg controller.
*/
struct list_head periodic_sched_assigned;
/**
* List of periodic QHs that have been queued for execution.
*
* Items move from this list to either periodic_sched_inactive or
* periodic_sched_ready when the channel associated with the transfer
* is released. If the interval for the QH is 1, the item moves to
* periodic_sched_ready because it must be rescheduled for the next
* frame. Otherwise, the item moves to periodic_sched_inactive.
*/
struct list_head periodic_sched_queued;
/**
* Total bandwidth claimed so far for periodic transfers. This value
* is in microseconds per (micro)frame. The assumption is that all
* periodic transfers may occur in the same (micro)frame.
*/
uint16_t periodic_usecs;
/**
* Total bandwidth claimed so far for all periodic transfers
* in a frame.
* This will include a mixture of HS and FS transfers.
* Units are microseconds per (micro)frame.
* We have a budget per frame and have to schedule
* transactions accordingly.
* Watch out for the fact that things are actually scheduled for the
* "next frame".
*/
uint16_t frame_usecs[8];
/**
* Frame number read from the core at SOF. The value ranges from 0 to
* DWC_HFNUM_MAX_FRNUM.
*/
uint16_t frame_number;
/**
* Free host channels in the controller. This is a list of
* dwc_hc_t items.
*/
struct list_head free_hc_list;
/**
* Number of available host channels.
*/
int available_host_channels;
/**
* Array of pointers to the host channel descriptors. Allows accessing
* a host channel descriptor given the host channel number. This is
* useful in interrupt handlers.
*/
dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
/**
* Buffer to use for any data received during the status phase of a
* control transfer. Normally no data is transferred during the status
* phase. This buffer is used as a bit bucket.
*/
uint8_t *status_buf;
/**
* DMA address for status_buf.
*/
dma_addr_t status_buf_dma;
#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
/**
* Structure to allow starting the HCD in a non-interrupt context
* during an OTG role change.
*/
struct work_struct start_work;
struct usb_hcd *_p;
/**
* Connection timer. An OTG host must display a message if the device
* does not connect. Started when the VBus power is turned on via
* sysfs attribute "buspower".
*/
struct timer_list conn_timer;
/* Tasket to do a reset */
struct tasklet_struct *reset_tasklet;
#ifdef DEBUG
uint32_t frrem_samples;
uint64_t frrem_accum;
uint32_t hfnum_7_samples_a;
uint64_t hfnum_7_frrem_accum_a;
uint32_t hfnum_0_samples_a;
uint64_t hfnum_0_frrem_accum_a;
uint32_t hfnum_other_samples_a;
uint64_t hfnum_other_frrem_accum_a;
uint32_t hfnum_7_samples_b;
uint64_t hfnum_7_frrem_accum_b;
uint32_t hfnum_0_samples_b;
uint64_t hfnum_0_frrem_accum_b;
uint32_t hfnum_other_samples_b;
uint64_t hfnum_other_frrem_accum_b;
#endif
} dwc_otg_hcd_t;
/** Gets the dwc_otg_hcd from a struct usb_hcd */
static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
{
return (dwc_otg_hcd_t *)(hcd->hcd_priv);
}
/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
{
return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
}
/** @name HCD Create/Destroy Functions */
/** @{ */
extern int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device);
extern void dwc_otg_hcd_remove(struct device *_dev);
/** @} */
/** @name Linux HC Driver API Functions */
/** @{ */
extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
struct urb *urb,
gfp_t mem_flags);
extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
struct urb *urb,
int status);
extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
struct usb_host_endpoint *ep);
extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
char *buf);
extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
u16 typeReq,
u16 wValue,
u16 wIndex,
char *buf,
u16 wLength);
/** @} */
/** @name Transaction Execution Functions */
/** @{ */
extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd);
extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
dwc_otg_transaction_type_e _tr_type);
extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *_urb,
int _status);
/** @} */
/** @name Interrupt Handler Functions */
/** @{ */
extern int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num);
extern int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
/** @} */
/** @name Schedule Queue Functions */
/** @{ */
/* Implemented in dwc_otg_hcd_queue.c */
extern dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb);
extern void dwc_otg_hcd_qh_init (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb);
extern void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh);
extern int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
extern void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
extern void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_csplit);
extern int dwc_otg_hcd_qh_deferr (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int delay);
/** Remove and free a QH */
static inline void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *_hcd,
dwc_otg_qh_t *_qh)
{
dwc_otg_hcd_qh_remove (_hcd, _qh);
dwc_otg_hcd_qh_free (_qh);
}
/** Allocates memory for a QH structure.
* @return Returns the memory allocate or NULL on error. */
static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc (void)
{
#ifdef _SC_BUILD_
return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_ATOMIC);
#else
return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_KERNEL);
#endif
}
extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb);
extern void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb);
extern int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
/** Allocates memory for a QTD structure.
* @return Returns the memory allocate or NULL on error. */
static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc (void)
{
#ifdef _SC_BUILD_
return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_ATOMIC);
#else
return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_KERNEL);
#endif
}
/** Frees the memory for a QTD structure. QTD should already be removed from
* list.
* @param[in] _qtd QTD to free.*/
static inline void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *_qtd)
{
kfree (_qtd);
}
/** Removes a QTD from list.
* @param[in] _qtd QTD to remove from list. */
static inline void dwc_otg_hcd_qtd_remove (dwc_otg_qtd_t *_qtd)
{
unsigned long flags;
local_irq_save (flags);
list_del (&_qtd->qtd_list_entry);
local_irq_restore (flags);
}
/** Remove and free a QTD */
static inline void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_qtd_t *_qtd)
{
dwc_otg_hcd_qtd_remove (_qtd);
dwc_otg_hcd_qtd_free (_qtd);
}
/** @} */
/** @name Internal Functions */
/** @{ */
dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb);
void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd);
void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd);
/** @} */
/** Gets the usb_host_endpoint associated with an URB. */
static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *_urb)
{
struct usb_device *dev = _urb->dev;
int ep_num = usb_pipeendpoint(_urb->pipe);
if (usb_pipein(_urb->pipe))
return dev->ep_in[ep_num];
else
return dev->ep_out[ep_num];
}
/**
* Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
* qualified with its direction (possible 32 endpoints per device).
*/
#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) \
((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
/** Gets the QH that contains the list_head */
#define dwc_list_to_qh(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qh_t,qh_list_entry))
/** Gets the QTD that contains the list_head */
#define dwc_list_to_qtd(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qtd_t,qtd_list_entry))
/** Check if QH is non-periodic */
#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
(_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
/** Packet size for any kind of endpoint descriptor */
#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
/**
* Returns true if _frame1 is less than or equal to _frame2. The comparison is
* done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
* frame number when the max frame number is reached.
*/
static inline int dwc_frame_num_le(uint16_t _frame1, uint16_t _frame2)
{
return ((_frame2 - _frame1) & DWC_HFNUM_MAX_FRNUM) <=
(DWC_HFNUM_MAX_FRNUM >> 1);
}
/**
* Returns true if _frame1 is greater than _frame2. The comparison is done
* modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
* number when the max frame number is reached.
*/
static inline int dwc_frame_num_gt(uint16_t _frame1, uint16_t _frame2)
{
return (_frame1 != _frame2) &&
(((_frame1 - _frame2) & DWC_HFNUM_MAX_FRNUM) <
(DWC_HFNUM_MAX_FRNUM >> 1));
}
/**
* Increments _frame by the amount specified by _inc. The addition is done
* modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
*/
static inline uint16_t dwc_frame_num_inc(uint16_t _frame, uint16_t _inc)
{
return (_frame + _inc) & DWC_HFNUM_MAX_FRNUM;
}
static inline uint16_t dwc_full_frame_num (uint16_t _frame)
{
return ((_frame) & DWC_HFNUM_MAX_FRNUM) >> 3;
}
static inline uint16_t dwc_micro_frame_num (uint16_t _frame)
{
return (_frame) & 0x7;
}
#ifdef DEBUG
/**
* Macro to sample the remaining PHY clocks left in the current frame. This
* may be used during debugging to determine the average time it takes to
* execute sections of code. There are two possible sample points, "a" and
* "b", so the _letter argument must be one of these values.
*
* To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
* example, "cat /sys/devices/lm0/hcd_frrem".
*/
#define dwc_sample_frrem(_hcd, _qh, _letter) \
{ \
hfnum_data_t hfnum; \
dwc_otg_qtd_t *qtd; \
qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
switch (hfnum.b.frnum & 0x7) { \
case 7: \
_hcd->hfnum_7_samples_##_letter++; \
_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
case 0: \
_hcd->hfnum_0_samples_##_letter++; \
_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
default: \
_hcd->hfnum_other_samples_##_letter++; \
_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
} \
} \
}
#else // DEBUG
#define dwc_sample_frrem(_hcd, _qh, _letter)
#endif // DEBUG
#endif // __DWC_HCD_H__
#endif /* DWC_DEVICE_ONLY */

1839
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c Normal file
View File

File diff suppressed because it is too large Load Diff

794
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c Normal file
View File

@@ -0,0 +1,794 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 537387 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef DWC_DEVICE_ONLY
/**
* @file
*
* This file contains the functions to manage Queue Heads and Queue
* Transfer Descriptors.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include "dwc_otg_driver.h"
#include "dwc_otg_hcd.h"
#include "dwc_otg_regs.h"
/**
* This function allocates and initializes a QH.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param[in] _urb Holds the information about the device/endpoint that we need
* to initialize the QH.
*
* @return Returns pointer to the newly allocated QH, or NULL on error. */
dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
{
dwc_otg_qh_t *qh;
/* Allocate memory */
/** @todo add memflags argument */
qh = dwc_otg_hcd_qh_alloc ();
if (qh == NULL) {
return NULL;
}
dwc_otg_hcd_qh_init (_hcd, qh, _urb);
return qh;
}
/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
* removed from a list. QTD list should already be empty if called from URB
* Dequeue.
*
* @param[in] _qh The QH to free.
*/
void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
{
dwc_otg_qtd_t *qtd;
struct list_head *pos;
unsigned long flags;
/* Free each QTD in the QTD list */
local_irq_save (flags);
for (pos = _qh->qtd_list.next;
pos != &_qh->qtd_list;
pos = _qh->qtd_list.next)
{
list_del (pos);
qtd = dwc_list_to_qtd (pos);
dwc_otg_hcd_qtd_free (qtd);
}
local_irq_restore (flags);
kfree (_qh);
return;
}
/** Initializes a QH structure.
*
* @param[in] _hcd The HCD state structure for the DWC OTG controller.
* @param[in] _qh The QH to init.
* @param[in] _urb Holds the information about the device/endpoint that we need
* to initialize the QH. */
#define SCHEDULE_SLOP 10
void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
{
memset (_qh, 0, sizeof (dwc_otg_qh_t));
/* Initialize QH */
switch (usb_pipetype(_urb->pipe)) {
case PIPE_CONTROL:
_qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
break;
case PIPE_BULK:
_qh->ep_type = USB_ENDPOINT_XFER_BULK;
break;
case PIPE_ISOCHRONOUS:
_qh->ep_type = USB_ENDPOINT_XFER_ISOC;
break;
case PIPE_INTERRUPT:
_qh->ep_type = USB_ENDPOINT_XFER_INT;
break;
}
_qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
_qh->data_toggle = DWC_OTG_HC_PID_DATA0;
_qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
INIT_LIST_HEAD(&_qh->qtd_list);
INIT_LIST_HEAD(&_qh->qh_list_entry);
_qh->channel = NULL;
/* FS/LS Enpoint on HS Hub
* NOT virtual root hub */
_qh->do_split = 0;
_qh->speed = _urb->dev->speed;
if (((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)) &&
(_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) {
DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
_urb->dev->ttport);
_qh->do_split = 1;
}
if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
_qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
/* Compute scheduling parameters once and save them. */
hprt0_data_t hprt;
/** @todo Account for split transfers in the bus time. */
int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
_qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed,
usb_pipein(_urb->pipe),
(_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount));
/* Start in a slightly future (micro)frame. */
_qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP);
_qh->interval = _urb->interval;
#if 0
/* Increase interrupt polling rate for debugging. */
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
_qh->interval = 8;
}
#endif
hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)))
{
_qh->interval *= 8;
_qh->sched_frame |= 0x7;
_qh->start_split_frame = _qh->sched_frame;
}
}
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
_urb->dev->devnum);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
usb_pipeendpoint(_urb->pipe),
usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
({ char *speed; switch (_urb->dev->speed) {
case USB_SPEED_LOW: speed = "low"; break;
case USB_SPEED_FULL: speed = "full"; break;
case USB_SPEED_HIGH: speed = "high"; break;
default: speed = "?"; break;
}; speed;}));
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
({ char *type; switch (_qh->ep_type) {
case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
default: type = "?"; break;
}; type;}));
#ifdef DEBUG
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
_qh->usecs);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
_qh->interval);
}
#endif
return;
}
/**
* Microframe scheduler
* track the total use in hcd->frame_usecs
* keep each qh use in qh->frame_usecs
* when surrendering the qh then donate the time back
*/
const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
/*
* called from dwc_otg_hcd.c:dwc_otg_hcd_init
*/
int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
{
int i;
for (i=0; i<8; i++) {
_hcd->frame_usecs[i] = max_uframe_usecs[i];
}
return 0;
}
static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int i;
unsigned short utime;
int t_left;
int ret;
int done;
ret = -1;
utime = _qh->usecs;
t_left = utime;
i = 0;
done = 0;
while (done == 0) {
/* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
if (utime <= _hcd->frame_usecs[i]) {
_hcd->frame_usecs[i] -= utime;
_qh->frame_usecs[i] += utime;
t_left -= utime;
ret = i;
done = 1;
return ret;
} else {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
}
}
return ret;
}
/*
* use this for FS apps that can span multiple uframes
*/
static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int i;
int j;
unsigned short utime;
int t_left;
int ret;
int done;
unsigned short xtime;
ret = -1;
utime = _qh->usecs;
t_left = utime;
i = 0;
done = 0;
loop:
while (done == 0) {
if(_hcd->frame_usecs[i] <= 0) {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
goto loop;
}
/*
* we need n consequtive slots
* so use j as a start slot j plus j+1 must be enough time (for now)
*/
xtime= _hcd->frame_usecs[i];
for (j = i+1 ; j < 8 ; j++ ) {
/*
* if we add this frame remaining time to xtime we may
* be OK, if not we need to test j for a complete frame
*/
if ((xtime+_hcd->frame_usecs[j]) < utime) {
if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
j = 8;
ret = -1;
continue;
}
}
if (xtime >= utime) {
ret = i;
j = 8; /* stop loop with a good value ret */
continue;
}
/* add the frame time to x time */
xtime += _hcd->frame_usecs[j];
/* we must have a fully available next frame or break */
if ((xtime < utime)
&& (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
ret = -1;
j = 8; /* stop loop with a bad value ret */
continue;
}
}
if (ret >= 0) {
t_left = utime;
for (j = i; (t_left>0) && (j < 8); j++ ) {
t_left -= _hcd->frame_usecs[j];
if ( t_left <= 0 ) {
_qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
_hcd->frame_usecs[j]= -t_left;
ret = i;
done = 1;
} else {
_qh->frame_usecs[j] += _hcd->frame_usecs[j];
_hcd->frame_usecs[j] = 0;
}
}
} else {
i++;
if (i == 8) {
done = 1;
ret = -1;
}
}
}
return ret;
}
static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
int ret;
ret = -1;
if (_qh->speed == USB_SPEED_HIGH) {
/* if this is a hs transaction we need a full frame */
ret = find_single_uframe(_hcd, _qh);
} else {
/* if this is a fs transaction we may need a sequence of frames */
ret = find_multi_uframe(_hcd, _qh);
}
return ret;
}
/**
* Checks that the max transfer size allowed in a host channel is large enough
* to handle the maximum data transfer in a single (micro)frame for a periodic
* transfer.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for a periodic endpoint.
*
* @return 0 if successful, negative error code otherwise.
*/
static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int status;
uint32_t max_xfer_size;
uint32_t max_channel_xfer_size;
status = 0;
max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
if (max_xfer_size > max_channel_xfer_size) {
DWC_NOTICE("%s: Periodic xfer length %d > "
"max xfer length for channel %d\n",
__func__, max_xfer_size, max_channel_xfer_size);
status = -ENOSPC;
}
return status;
}
/**
* Schedules an interrupt or isochronous transfer in the periodic schedule.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for the periodic transfer. The QH should already contain the
* scheduling information.
*
* @return 0 if successful, negative error code otherwise.
*/
static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int status = 0;
int frame;
status = find_uframe(_hcd, _qh);
frame = -1;
if (status == 0) {
frame = 7;
} else {
if (status > 0 )
frame = status-1;
}
/* Set the new frame up */
if (frame > -1) {
_qh->sched_frame &= ~0x7;
_qh->sched_frame |= (frame & 7);
}
if (status != -1 )
status = 0;
if (status) {
DWC_NOTICE("%s: Insufficient periodic bandwidth for "
"periodic transfer.\n", __func__);
return status;
}
status = check_max_xfer_size(_hcd, _qh);
if (status) {
DWC_NOTICE("%s: Channel max transfer size too small "
"for periodic transfer.\n", __func__);
return status;
}
/* Always start in the inactive schedule. */
list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
/* Update claimed usecs per (micro)frame. */
_hcd->periodic_usecs += _qh->usecs;
/* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
} else {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
}
return status;
}
/**
* This function adds a QH to either the non periodic or periodic schedule if
* it is not already in the schedule. If the QH is already in the schedule, no
* action is taken.
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
unsigned long flags;
int status = 0;
local_irq_save(flags);
if (!list_empty(&_qh->qh_list_entry)) {
/* QH already in a schedule. */
goto done;
}
/* Add the new QH to the appropriate schedule */
if (dwc_qh_is_non_per(_qh)) {
/* Always start in the inactive schedule. */
list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
} else {
status = schedule_periodic(_hcd, _qh);
}
done:
local_irq_restore(flags);
return status;
}
/**
* This function adds a QH to the non periodic deferred schedule.
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
{
unsigned long flags;
local_irq_save(flags);
if (!list_empty(&_qh->qh_list_entry)) {
/* QH already in a schedule. */
goto done;
}
/* Add the new QH to the non periodic deferred schedule */
if (dwc_qh_is_non_per(_qh)) {
list_add_tail(&_qh->qh_list_entry,
&_hcd->non_periodic_sched_deferred);
}
done:
local_irq_restore(flags);
return 0;
}
/**
* Removes an interrupt or isochronous transfer from the periodic schedule.
*
* @param _hcd The HCD state structure for the DWC OTG controller.
* @param _qh QH for the periodic transfer.
*/
static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
int i;
list_del_init(&_qh->qh_list_entry);
/* Update claimed usecs per (micro)frame. */
_hcd->periodic_usecs -= _qh->usecs;
for (i = 0; i < 8; i++) {
_hcd->frame_usecs[i] += _qh->frame_usecs[i];
_qh->frame_usecs[i] = 0;
}
/* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
} else {
hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
_qh, _qh->usecs, _qh->interval);
}
}
/**
* Removes a QH from either the non-periodic or periodic schedule. Memory is
* not freed.
*
* @param[in] _hcd The HCD state structure.
* @param[in] _qh QH to remove from schedule. */
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
unsigned long flags;
local_irq_save(flags);
if (list_empty(&_qh->qh_list_entry)) {
/* QH is not in a schedule. */
goto done;
}
if (dwc_qh_is_non_per(_qh)) {
if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
_hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
}
list_del_init(&_qh->qh_list_entry);
} else {
deschedule_periodic(_hcd, _qh);
}
done:
local_irq_restore(flags);
}
/**
* Defers a QH. For non-periodic QHs, removes the QH from the active
* non-periodic schedule. The QH is added to the deferred non-periodic
* schedule if any QTDs are still attached to the QH.
*/
int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay)
{
int deact = 1;
unsigned long flags;
local_irq_save(flags);
if (dwc_qh_is_non_per(_qh)) {
_qh->sched_frame =
dwc_frame_num_inc(_hcd->frame_number,
delay);
_qh->channel = NULL;
_qh->qtd_in_process = NULL;
deact = 0;
dwc_otg_hcd_qh_remove(_hcd, _qh);
if (!list_empty(&_qh->qtd_list)) {
/* Add back to deferred non-periodic schedule. */
dwc_otg_hcd_qh_add_deferred(_hcd, _qh);
}
}
local_irq_restore(flags);
return deact;
}
/**
* Deactivates a QH. For non-periodic QHs, removes the QH from the active
* non-periodic schedule. The QH is added to the inactive non-periodic
* schedule if any QTDs are still attached to the QH.
*
* For periodic QHs, the QH is removed from the periodic queued schedule. If
* there are any QTDs still attached to the QH, the QH is added to either the
* periodic inactive schedule or the periodic ready schedule and its next
* scheduled frame is calculated. The QH is placed in the ready schedule if
* the scheduled frame has been reached already. Otherwise it's placed in the
* inactive schedule. If there are no QTDs attached to the QH, the QH is
* completely removed from the periodic schedule.
*/
void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
{
unsigned long flags;
local_irq_save(flags);
if (dwc_qh_is_non_per(_qh)) {
dwc_otg_hcd_qh_remove(_hcd, _qh);
if (!list_empty(&_qh->qtd_list)) {
/* Add back to inactive non-periodic schedule. */
dwc_otg_hcd_qh_add(_hcd, _qh);
}
} else {
uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
if (_qh->do_split) {
/* Schedule the next continuing periodic split transfer */
if (sched_next_periodic_split) {
_qh->sched_frame = frame_number;
if (dwc_frame_num_le(frame_number,
dwc_frame_num_inc(_qh->start_split_frame, 1))) {
/*
* Allow one frame to elapse after start
* split microframe before scheduling
* complete split, but DONT if we are
* doing the next start split in the
* same frame for an ISOC out.
*/
if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
_qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
}
}
} else {
_qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
_qh->interval);
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
_qh->sched_frame = frame_number;
}
_qh->sched_frame |= 0x7;
_qh->start_split_frame = _qh->sched_frame;
}
} else {
_qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
_qh->sched_frame = frame_number;
}
}
if (list_empty(&_qh->qtd_list)) {
dwc_otg_hcd_qh_remove(_hcd, _qh);
} else {
/*
* Remove from periodic_sched_queued and move to
* appropriate queue.
*/
if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
list_move(&_qh->qh_list_entry,
&_hcd->periodic_sched_ready);
} else {
list_move(&_qh->qh_list_entry,
&_hcd->periodic_sched_inactive);
}
}
}
local_irq_restore(flags);
}
/**
* This function allocates and initializes a QTD.
*
* @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
* pointing to each other so each pair should have a unique correlation.
*
* @return Returns pointer to the newly allocated QTD, or NULL on error. */
dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
{
dwc_otg_qtd_t *qtd;
qtd = dwc_otg_hcd_qtd_alloc ();
if (qtd == NULL) {
return NULL;
}
dwc_otg_hcd_qtd_init (qtd, _urb);
return qtd;
}
/**
* Initializes a QTD structure.
*
* @param[in] _qtd The QTD to initialize.
* @param[in] _urb The URB to use for initialization. */
void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
{
memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
_qtd->urb = _urb;
if (usb_pipecontrol(_urb->pipe)) {
/*
* The only time the QTD data toggle is used is on the data
* phase of control transfers. This phase always starts with
* DATA1.
*/
_qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
_qtd->control_phase = DWC_OTG_CONTROL_SETUP;
}
/* start split */
_qtd->complete_split = 0;
_qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
_qtd->isoc_split_offset = 0;
/* Store the qtd ptr in the urb to reference what QTD. */
_urb->hcpriv = _qtd;
return;
}
/**
* This function adds a QTD to the QTD-list of a QH. It will find the correct
* QH to place the QTD into. If it does not find a QH, then it will create a
* new QH. If the QH to which the QTD is added is not currently scheduled, it
* is placed into the proper schedule based on its EP type.
*
* @param[in] _qtd The QTD to add
* @param[in] _dwc_otg_hcd The DWC HCD structure
*
* @return 0 if successful, negative error code otherwise.
*/
int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd)
{
struct usb_host_endpoint *ep;
dwc_otg_qh_t *qh;
unsigned long flags;
int retval = 0;
struct urb *urb = _qtd->urb;
local_irq_save(flags);
/*
* Get the QH which holds the QTD-list to insert to. Create QH if it
* doesn't exist.
*/
ep = dwc_urb_to_endpoint(urb);
qh = (dwc_otg_qh_t *)ep->hcpriv;
if (qh == NULL) {
qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
if (qh == NULL) {
retval = -1;
goto done;
}
ep->hcpriv = qh;
}
_qtd->qtd_qh_ptr = qh;
retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
if (retval == 0) {
list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
}
done:
local_irq_restore(flags);
return retval;
}
#endif /* DWC_DEVICE_ONLY */

103
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_ifx.c Normal file
View File

@@ -0,0 +1,103 @@
/******************************************************************************
**
** FILE NAME : dwc_otg_ifx.c
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 12 Auguest 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Platform specific initialization.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 Auguest 2007 Sung Winder Initiate Version
*******************************************************************************/
#include "dwc_otg_ifx.h"
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/gpio.h>
#include <asm/io.h>
//#include <asm/mach-ifxmips/ifxmips.h>
#include <lantiq_soc.h>
#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
#define writel ltq_w32
#define readl ltq_r32
void dwc_otg_power_on (void)
{
// clear power
writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
// set clock gating
if (ltq_is_ase())
writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR);
else
writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
// set power
writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);
writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR);
#if 1//defined (DWC_HOST_ONLY)
// make the hardware be a host controller (default)
//clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_HDSEL_BIT), DANUBE_RCU_UBSCFG);
//#elif defined (DWC_DEVICE_ONLY)
/* set the controller to the device mode */
// set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
#else
#error "For Danube/Twinpass, it should be HOST or Device Only."
#endif
// set the HC's byte-order to big-endian
//set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) | (1<<DANUBE_USBCFG_HOST_END_BIT), DANUBE_RCU_UBSCFG);
//clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_SLV_END_BIT), DANUBE_RCU_UBSCFG);
//writel(0x400, DANUBE_RCU_UBSCFG);
// PHY configurations.
writel (0x14014, (volatile unsigned long *)0xbe10103c);
}
int ifx_usb_hc_init(unsigned long base_addr, int irq)
{
return 0;
}
void ifx_usb_hc_remove(void)
{
}

85
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_ifx.h Normal file
View File

@@ -0,0 +1,85 @@
/******************************************************************************
**
** FILE NAME : dwc_otg_ifx.h
** PROJECT : Twinpass/Danube
** MODULES : DWC OTG USB
**
** DATE : 12 April 2007
** AUTHOR : Sung Winder
** DESCRIPTION : Platform specific initialization.
** COPYRIGHT : Copyright (c) 2007
** Infineon Technologies AG
** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
** Hsin-chu City, 300 Taiwan.
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 12 April 2007 Sung Winder Initiate Version
*******************************************************************************/
#if !defined(__DWC_OTG_IFX_H__)
#define __DWC_OTG_IFX_H__
#include <linux/irq.h>
#include <irq.h>
// 20070316, winder added.
#ifndef SZ_256K
#define SZ_256K 0x00040000
#endif
extern void dwc_otg_power_on (void);
/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */
// #include <asm/danube/danube.h>
// #include <asm/ifx/irq.h>
/* winder, I used the Danube parameter as default. *
* We could change this through module param. */
#define IFX_USB_IOMEM_BASE 0x1e101000
#define IFX_USB_IOMEM_SIZE SZ_256K
#define IFX_USB_IRQ LTQ_USB_INT
/**
* This function is called to set correct clock gating and power.
* For Twinpass/Danube board.
*/
#ifndef DANUBE_RCU_BASE_ADDR
#define DANUBE_RCU_BASE_ADDR (0xBF203000)
#endif
#ifndef DANUBE_CGU
#define DANUBE_CGU (0xBF103000)
#endif
#ifndef DANUBE_CGU_IFCCR
/***CGU Interface Clock Control Register***/
#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
#endif
#ifndef DANUBE_PMU
#define DANUBE_PMU (KSEG1+0x1F102000)
#endif
#ifndef DANUBE_PMU_PWDCR
/* PMU Power down Control Register */
#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C))
#endif
#define DANUBE_RCU_UBSCFG ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18))
#define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device
#define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end
#define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end
extern void ltq_mask_and_ack_irq(struct irq_data *d);
static void inline mask_and_ack_ifx_irq(int x)
{
struct irq_data d;
d.irq = x;
ltq_mask_and_ack_irq(&d);
}
#endif //__DWC_OTG_IFX_H__

269
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_plat.h Normal file
View File

@@ -0,0 +1,269 @@
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/platform/dwc_otg_plat.h $
* $Revision: 1.1.1.1 $
* $Date: 2009-04-17 06:15:34 $
* $Change: 510301 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_PLAT_H__)
#define __DWC_OTG_PLAT_H__
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <asm/io.h>
/**
* @file
*
* This file contains the Platform Specific constants, interfaces
* (functions and macros) for Linux.
*
*/
/*#if !defined(__LINUX__)
#error "The contents of this file is Linux specific!!!"
#endif
*/
#include <lantiq_soc.h>
#define writel ltq_w32
#define readl ltq_r32
/**
* Reads the content of a register.
*
* @param _reg address of register to read.
* @return contents of the register.
*
* Usage:<br>
* <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
*/
static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg)
{
return readl(_reg);
};
/**
* Writes a register with a 32 bit value.
*
* @param _reg address of register to read.
* @param _value to write to _reg.
*
* Usage:<br>
* <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
*/
static __inline__ void dwc_write_reg32( volatile uint32_t *_reg, const uint32_t _value)
{
writel( _value, _reg );
};
/**
* This function modifies bit values in a register. Using the
* algorithm: (reg_contents & ~clear_mask) | set_mask.
*
* @param _reg address of register to read.
* @param _clear_mask bit mask to be cleared.
* @param _set_mask bit mask to be set.
*
* Usage:<br>
* <code> // Clear the SOF Interrupt Mask bit and <br>
* // set the OTG Interrupt mask bit, leaving all others as they were.
* dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
*/
static __inline__
void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
{
writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg );
};
/**
* Wrapper for the OS micro-second delay function.
* @param[in] _usecs Microseconds of delay
*/
static __inline__ void UDELAY( const uint32_t _usecs )
{
udelay( _usecs );
}
/**
* Wrapper for the OS milli-second delay function.
* @param[in] _msecs milliseconds of delay
*/
static __inline__ void MDELAY( const uint32_t _msecs )
{
mdelay( _msecs );
}
/**
* Wrapper for the Linux spin_lock. On the ARM (Integrator)
* spin_lock() is a nop.
*
* @param _lock Pointer to the spinlock.
*/
static __inline__ void SPIN_LOCK( spinlock_t *_lock )
{
spin_lock(_lock);
}
/**
* Wrapper for the Linux spin_unlock. On the ARM (Integrator)
* spin_lock() is a nop.
*
* @param _lock Pointer to the spinlock.
*/
static __inline__ void SPIN_UNLOCK( spinlock_t *_lock )
{
spin_unlock(_lock);
}
/**
* Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM
* (Integrator) spin_lock() is a nop.
*
* @param _l Pointer to the spinlock.
* @param _f unsigned long for irq flags storage.
*/
#define SPIN_LOCK_IRQSAVE( _l, _f ) { \
spin_lock_irqsave(_l,_f); \
}
/**
* Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM
* (Integrator) spin_lock() is a nop.
*
* @param _l Pointer to the spinlock.
* @param _f unsigned long for irq flags storage.
*/
#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) {\
spin_unlock_irqrestore(_l,_f); \
}
/*
* Debugging support vanishes in non-debug builds.
*/
/**
* The Debug Level bit-mask variable.
*/
extern uint32_t g_dbg_lvl;
/**
* Set the Debug Level variable.
*/
static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new )
{
uint32_t old = g_dbg_lvl;
g_dbg_lvl = _new;
return old;
}
/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
#define DBG_CIL (0x2)
/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
* messages */
#define DBG_CILV (0x20)
/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
* messages */
#define DBG_PCD (0x4)
/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
* messages */
#define DBG_PCDV (0x40)
/** When debug level has the DBG_HCD bit set, display Host debug messages */
#define DBG_HCD (0x8)
/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
* messages */
#define DBG_HCDV (0x80)
/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
* mode. */
#define DBG_HCD_URB (0x800)
/** When debug level has any bit set, display debug messages */
#define DBG_ANY (0xFF)
/** All debug messages off */
#define DBG_OFF 0
/** Prefix string for DWC_DEBUG print macros. */
#define USB_DWC "DWC_otg: "
/**
* Print a debug message when the Global debug level variable contains
* the bit defined in <code>lvl</code>.
*
* @param[in] lvl - Debug level, use one of the DBG_ constants above.
* @param[in] x - like printf
*
* Example:<p>
* <code>
* DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
* </code>
* <br>
* results in:<br>
* <code>
* usb-DWC_otg: dwc_otg_cil_init(ca867000)
* </code>
*/
#ifdef DEBUG
# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
#else
# define DWC_DEBUGPL(lvl, x...) do{}while(0)
# define DWC_DEBUGP(x...)
# define CHK_DEBUG_LEVEL(level) (0)
#endif /*DEBUG*/
/**
* Print an Error message.
*/
#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
/**
* Print a Warning message.
*/
#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
/**
* Print a notice (normal but significant message).
*/
#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
/**
* Basic message printing.
*/
#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
#endif

1797
target/linux/lantiq/files-3.3/drivers/usb/dwc_otg/dwc_otg_regs.h Normal file
View File

File diff suppressed because it is too large Load Diff