mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
[lantiq] move files/ -> files-3.3/
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34060 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
58
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/Kconfig
Normal file
58
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/Kconfig
Normal file
@@ -0,0 +1,58 @@
|
||||
|
||||
config USB_HOST_IFX
|
||||
tristate "Infineon USB Host Controller Driver"
|
||||
depends on USB
|
||||
default n
|
||||
help
|
||||
Infineon USB Host Controller
|
||||
|
||||
config USB_HOST_IFX_B
|
||||
bool "USB host mode on core 1 and 2"
|
||||
depends on USB_HOST_IFX
|
||||
help
|
||||
Both cores run as host
|
||||
|
||||
#config USB_HOST_IFX_1
|
||||
#config USB_HOST_IFX_2
|
||||
|
||||
#config IFX_DANUBE
|
||||
#config IFX_AMAZON_SE
|
||||
config IFX_AR9
|
||||
depends on USB_HOST_IFX
|
||||
bool "AR9"
|
||||
|
||||
config IFX_VR9
|
||||
depends on USB_HOST_IFX
|
||||
bool "VR9"
|
||||
|
||||
#config USB_HOST_IFX_FORCE_USB11
|
||||
# bool "Forced USB1.1"
|
||||
# depends on USB_HOST_IFX
|
||||
# default n
|
||||
# help
|
||||
# force to be USB 1.1
|
||||
|
||||
#config USB_HOST_IFX_WITH_HS_ELECT_TST
|
||||
# bool "With HS_Electrical Test"
|
||||
# depends on USB_HOST_IFX
|
||||
# default n
|
||||
# help
|
||||
# With USBIF HSET routines
|
||||
|
||||
#config USB_HOST_IFX_WITH_ISO
|
||||
# bool "With ISO transfer"
|
||||
# depends on USB_HOST_IFX
|
||||
# default n
|
||||
# help
|
||||
# With USBIF ISO transfer
|
||||
|
||||
config USB_HOST_IFX_UNALIGNED_ADJ
|
||||
bool "Adjust"
|
||||
depends on USB_HOST_IFX
|
||||
help
|
||||
USB_HOST_IFX_UNALIGNED_ADJ
|
||||
|
||||
#config USB_HOST_IFX_UNALIGNED_CHK
|
||||
#config USB_HOST_IFX_UNALIGNED_NONE
|
||||
|
||||
|
||||
85
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/Makefile
Normal file
85
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/Makefile
Normal file
@@ -0,0 +1,85 @@
|
||||
|
||||
#
|
||||
# Makefile for USB Core files and filesystem
|
||||
#
|
||||
ifxusb_host-objs := ifxusb_driver.o
|
||||
ifxusb_host-objs += ifxusb_ctl.o
|
||||
ifxusb_host-objs += ifxusb_cif.o
|
||||
ifxusb_host-objs += ifxusb_cif_h.o
|
||||
ifxusb_host-objs += ifxhcd.o
|
||||
ifxusb_host-objs += ifxhcd_es.o
|
||||
ifxusb_host-objs += ifxhcd_intr.o
|
||||
ifxusb_host-objs += ifxhcd_queue.o
|
||||
|
||||
ifeq ($(CONFIG_IFX_TWINPASS),y)
|
||||
EXTRA_CFLAGS += -D__IS_TWINPASS__
|
||||
endif
|
||||
ifeq ($(CONFIG_IFX_DANUBE),y)
|
||||
EXTRA_CFLAGS += -D__IS_DANUBE__
|
||||
endif
|
||||
ifeq ($(CONFIG_IFX_AMAZON_SE),y)
|
||||
EXTRA_CFLAGS += -D__IS_AMAZON_SE__
|
||||
endif
|
||||
ifeq ($(CONFIG_IFX_AR9),y)
|
||||
EXTRA_CFLAGS += -D__IS_AR9__
|
||||
endif
|
||||
ifeq ($(CONFIG_IFX_AMAZON_S),y)
|
||||
EXTRA_CFLAGS += -D__IS_AR9__
|
||||
endif
|
||||
ifeq ($(CONFIG_IFX_VR9),y)
|
||||
EXTRA_CFLAGS += -D__IS_VR9__
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USB_HOST_IFX),y)
|
||||
EXTRA_CFLAGS += -Dlinux -D__LINUX__
|
||||
EXTRA_CFLAGS += -D__IS_HOST__
|
||||
EXTRA_CFLAGS += -D__KERNEL__
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USB_HOST_IFX),m)
|
||||
EXTRA_CFLAGS += -Dlinux -D__LINUX__
|
||||
EXTRA_CFLAGS += -D__IS_HOST__
|
||||
EXTRA_CFLAGS += -D__KERNEL__
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USB_DEBUG),y)
|
||||
EXTRA_CFLAGS += -D__DEBUG__
|
||||
EXTRA_CFLAGS += -D__ENABLE_DUMP__
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USB_HOST_IFX_B),y)
|
||||
EXTRA_CFLAGS += -D__IS_DUAL__
|
||||
endif
|
||||
ifeq ($(CONFIG_USB_HOST_IFX_1),y)
|
||||
EXTRA_CFLAGS += -D__IS_FIRST__
|
||||
endif
|
||||
ifeq ($(CONFIG_USB_HOST_IFX_2),y)
|
||||
EXTRA_CFLAGS += -D__IS_SECOND__
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USB_HOST_IFX_FORCE_USB11),y)
|
||||
EXTRA_CFLAGS += -D__FORCE_USB11__
|
||||
endif
|
||||
ifeq ($(CONFIG_USB_HOST_IFX_WITH_HS_ELECT_TST),y)
|
||||
EXTRA_CFLAGS += -D__WITH_HS_ELECT_TST__
|
||||
endif
|
||||
ifeq ($(CONFIG_USB_HOST_IFX_WITH_ISO),y)
|
||||
EXTRA_CFLAGS += -D__EN_ISOC__
|
||||
endif
|
||||
ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_ADJ),y)
|
||||
EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_ADJ__
|
||||
endif
|
||||
ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_CHK),y)
|
||||
EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_CHK__
|
||||
endif
|
||||
|
||||
# EXTRA_CFLAGS += -D__DYN_SOF_INTR__
|
||||
EXTRA_CFLAGS += -D__UEIP__
|
||||
# EXTRA_CFLAGS += -D__EN_ISOC__
|
||||
# EXTRA_CFLAGS += -D__EN_ISOC_SPLIT__
|
||||
|
||||
## 20110628 AVM/WK New flag for less SOF IRQs
|
||||
EXTRA_CFLAGS += -D__USE_TIMER_4_SOF__
|
||||
|
||||
obj-$(CONFIG_USB_HOST_IFX) += ifxusb_host.o
|
||||
|
||||
171
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/TagHistory
Normal file
171
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/TagHistory
Normal file
@@ -0,0 +1,171 @@
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.18-r240-non_musb_ar9_vr9-SOF_Timer_Fixed
|
||||
| Erzeugt mit SVN-Tagger Version 3.74.
|
||||
+----------------------------------------------------------------------+
|
||||
FIX - Korrektur bei der SOF-Timer/IRQ Steuerung. (Bug in Tag 5.17)
|
||||
FIX - Fehlerbehandlung an mehreren Stellen korrigiert bzw. eingebaut.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.17-r237-non_musb_ar9_vr9-2_6_32_41_Kompatibel
|
||||
| Erzeugt mit SVN-Tagger Version 3.73.
|
||||
+----------------------------------------------------------------------+
|
||||
FIX - Kompatiblität zum Update auf Kernel 2.6.32-41. Weiterhin für 28er geeignet.
|
||||
ENH - Reduktion der Interrruptlast durch Nutzung eines hrtimers anstatt SOF-IRQ.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.16-r208-non_musb_ar9_vr9-20110421_Zero_Paket_Optimiert
|
||||
| Erzeugt mit SVN-Tagger Version 3.66.
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
FIX - VR9 / AR9 - Zero Packet. Optimierung korrigiert.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.15-r205-non_musb_ar9_vr9-20110421_Zero_Paket_WA_funktioniert
|
||||
| Erzeugt mit SVN-Tagger Version 3.66.
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
FIX - VR9 / AR9 - "Zero Packet" funktioniert nun wirklich. Letzter Tag hatte einen Bug.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.14-r202-non_musb_ar9_vr9-20110420_Zero_Paket_WA
|
||||
| Erzeugt mit SVN-Tagger Version 3.66.
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
FIX - VR9 / AR9 - Zero Packet Workaround: ZLP wird nun geschickt wenn URB_ZERO_PACKET aktiv ist.
|
||||
Wird von LTE Altair Firmware benoetig.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.13-r199-non_musb_ar9_vr9-20110310_Init_Fix
|
||||
| Erzeugt mit SVN-Tagger Version 3.64.
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
FIX - VR9 / AR9 - Timing der Initialisierungsphase angepasst zum Kernel 2.6.28 mit UGW-4.3.1.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.12-r184-non_musb_ar9_vr9-20110118_Full_Speed_Fix
|
||||
| Erzeugt mit SVN-Tagger Version 3.58.
|
||||
+----------------------------------------------------------------------+
|
||||
AR9/VR9 (3370,6840,7320):
|
||||
Makefile - FIX - (Workaround) Debug Modus hilft gegen Enumerationsfehler bei Full Speed Drucker.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.11-r175-non_musb_ar9_vr9-20101220_VR9_2_Ports_DMA_Fix
|
||||
| Erzeugt mit SVN-Tagger Version 3.58.
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
FIX - VR9 - Workaround DMA Burst Size. Wenn beiden USB Ports benutzt werden, geht der USB Host nicht mehr.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.10-r169-non_musb_ar9_vr9-Fix_Spontan_Reboot
|
||||
| Erzeugt mit SVN-Tagger Version 3.58.
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
FIX - Endlosschleife führte zu einem spontanen Reboot.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.9-r166-non_musb_ar9_vr9-20101112_deferred_completion
|
||||
| Erzeugt mit SVN-Tagger Version 3.58.
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
ENH - Deferred URB Completion Mechanismus eingebaut. Nun ca. 10% schneller bei usb-storage.
|
||||
|
||||
FIX - PING Flow Control gefixt.
|
||||
FIX - Channel Halt wird nun immer angerufen. (Split Transaction wurde nicht erfolgreich gestoppt).
|
||||
FIX - Spinlock Benutzung verbessert. Mehr Stabilitaet.
|
||||
|
||||
CHG - Ubersetztungsoption __DEBUG__ ist nun abhaengig von CONFIG_USB_DEBUG
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.8-r149-non_musb_ar9_vr9-20100827_LTE_Interrupt_EP_Fix
|
||||
| Erzeugt mit SVN-Tagger Version 3.57.
|
||||
+----------------------------------------------------------------------+
|
||||
AR9/VR9 - FIX - Interrupt Packets gingen verloren, wegen falschem Timing beim OddFrame Bit.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.7-r142-non_musb_ar9_vr9-20100728_Unaligned_Buf_Fix
|
||||
| Erzeugt mit SVN-Tagger Version 3.57.
|
||||
+----------------------------------------------------------------------+
|
||||
FIX - "Unaligned Data" Flag wieder nach Transfer geloescht.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.6-r133-non_musb_ar9_vr9-20100714_Toggle_Datenverlust_Fix
|
||||
| Erzeugt mit SVN-Tagger Version 3.57.
|
||||
+----------------------------------------------------------------------+
|
||||
TL5508 - Einige UMTS Modems funktionierten nicht korrekt an der 7320 (AR9).
|
||||
FIX - USB Data Toggle des usbcore benutzen. Datenverlust nach EP-Halt.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.5-r130-non_musb_ar9_vr9-20100712_USB_Ports_abschaltbar
|
||||
| Erzeugt mit SVN-Tagger Version 3.57.
|
||||
+----------------------------------------------------------------------+
|
||||
Power - Fix - Beide USB Port abschaltbar bei rmmod.
|
||||
rmmod - FIX - URB_Dequeue funktionierte beim Entladen des Treibers nicht (mehrere Ursachen).
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.4-r126-non_musb_ar9_vr9-20100701_Lost_Interrupt_Workaround
|
||||
| Erzeugt mit SVN-Tagger Version 3.57.
|
||||
+----------------------------------------------------------------------+
|
||||
FIX - Workaround wegen verpasstem Interrupt, bei Full-Speed Interrupt EP.
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.3-r123-non_musb_ar9_vr9-20100630_UMTS_Fixes
|
||||
| Erzeugt mit SVN-Tagger Version 3.57.
|
||||
+----------------------------------------------------------------------+
|
||||
FIX - Full-Speed Interrupt Endpoint hinter Hi-Speed Hub funktioniert nun (UMTS Modems)
|
||||
FIX - usb_hcd_link_urb_from_ep API von USBCore muss benutzt werden.
|
||||
FIX - Interrupt URBs nicht bei NAK completen.
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.2-r114-non_musb_ar9_vr9-20100520_StickAndSurf_funktioniert
|
||||
| Erzeugt mit SVN-Tagger Version 3.56.
|
||||
+----------------------------------------------------------------------+
|
||||
- Merge mit neuen LANTIQ Sourcen "3.0alpha B100312"
|
||||
- Fix - Spin_lock eingebaut, Stick&Surf funktioniert nun
|
||||
|
||||
- DEP - CONFIG_USB_HOST_IFX_WITH_ISO wird nicht unterstuetzt: In der Kernel Config deaktivieren.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.1-r107-non_musb_ar9_vr9-20100505_IFXUSB_Host_mit_Energiemonitor
|
||||
| Erzeugt mit SVN-Tagger Version 3.56.
|
||||
+----------------------------------------------------------------------+
|
||||
USB Host Treiber für AR9 und VR9
|
||||
--------------------------------
|
||||
FIX - Toggle Error nach STALL - Einfacher Workaround - Nun werden Massenspeicherpartitionen erkannt!
|
||||
AVM_POWERMETER - USB Energiemonitor Support.
|
||||
|
||||
Bekanntes Problem: Stick and Surf funktioniert nur sporadisch, weil CONTROL_IRQ manchmal ausbleibt.
|
||||
|
||||
2523
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd.c
Normal file
2523
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd.c
Normal file
File diff suppressed because it is too large
Load Diff
628
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd.h
Normal file
628
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd.h
Normal file
@@ -0,0 +1,628 @@
|
||||
/*****************************************************************************
|
||||
** FILE NAME : ifxhcd.h
|
||||
** PROJECT : IFX USB sub-system V3
|
||||
** MODULES : IFX USB sub-system Host and Device driver
|
||||
** SRC VERSION : 1.0
|
||||
** DATE : 1/Jan/2009
|
||||
** AUTHOR : Chen, Howard
|
||||
** DESCRIPTION : This file contains the structures, constants, and interfaces for
|
||||
** the Host Contoller Driver (HCD).
|
||||
**
|
||||
** The Host Controller Driver (HCD) is responsible for translating requests
|
||||
** from the USB Driver into the appropriate actions on the IFXUSB controller.
|
||||
** It isolates the USBD from the specifics of the controller by providing an
|
||||
** API to the USBD.
|
||||
** FUNCTIONS :
|
||||
** COMPILER : gcc
|
||||
** REFERENCE : Synopsys DWC-OTG Driver 2.7
|
||||
** COPYRIGHT :
|
||||
** Version Control Section **
|
||||
** $Author$
|
||||
** $Date$
|
||||
** $Revisions$
|
||||
** $Log$ Revision history
|
||||
*****************************************************************************/
|
||||
|
||||
/*!
|
||||
\defgroup IFXUSB_HCD HCD Interface
|
||||
\ingroup IFXUSB_DRIVER_V3
|
||||
\brief The Host Controller Driver (HCD) is responsible for translating requests
|
||||
from the USB Driver into the appropriate actions on the IFXUSB controller.
|
||||
It isolates the USBD from the specifics of the controller by providing an
|
||||
API to the USBD.
|
||||
*/
|
||||
|
||||
|
||||
/*!
|
||||
\file ifxhcd.h
|
||||
\ingroup IFXUSB_DRIVER_V3
|
||||
\brief This file contains the structures, constants, and interfaces for
|
||||
the Host Contoller Driver (HCD).
|
||||
*/
|
||||
|
||||
#if !defined(__IFXHCD_H__)
|
||||
#define __IFXHCD_H__
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <linux/usb.h>
|
||||
|
||||
#ifdef __USE_TIMER_4_SOF__
|
||||
#include <linux/hrtimer.h>
|
||||
#endif
|
||||
#include <linux/usb/hcd.h>
|
||||
|
||||
#include "ifxusb_cif.h"
|
||||
#include "ifxusb_plat.h"
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\addtogroup IFXUSB_HCD
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/* Phases for control transfers.*/
|
||||
typedef enum ifxhcd_control_phase {
|
||||
IFXHCD_CONTROL_SETUP,
|
||||
IFXHCD_CONTROL_DATA,
|
||||
IFXHCD_CONTROL_STATUS
|
||||
} ifxhcd_control_phase_e;
|
||||
|
||||
/* Reasons for halting a host channel. */
|
||||
typedef enum ifxhcd_halt_status
|
||||
{
|
||||
HC_XFER_NO_HALT_STATUS, // Initial
|
||||
HC_XFER_COMPLETE, // Xact complete without error, upward
|
||||
HC_XFER_URB_COMPLETE, // Xfer complete without error, short upward
|
||||
HC_XFER_STALL, // HC stopped abnormally, upward/downward
|
||||
HC_XFER_XACT_ERR, // HC stopped abnormally, upward
|
||||
HC_XFER_FRAME_OVERRUN, // HC stopped abnormally, upward
|
||||
HC_XFER_BABBLE_ERR, // HC stopped abnormally, upward
|
||||
HC_XFER_AHB_ERR, // HC stopped abnormally, upward
|
||||
HC_XFER_DATA_TOGGLE_ERR,
|
||||
HC_XFER_URB_DEQUEUE, // HC stopper manually, downward
|
||||
HC_XFER_NAK // HC stopped by nak monitor, downward
|
||||
} ifxhcd_halt_status_e;
|
||||
|
||||
struct ifxhcd_urbd;
|
||||
struct ifxhcd_hc ;
|
||||
struct ifxhcd_epqh ;
|
||||
struct ifxhcd_hcd;
|
||||
|
||||
/*!
|
||||
\brief A URB Descriptor (URBD) holds the state of a bulk, control,
|
||||
interrupt, or isochronous transfer. A single URBD is created for each URB
|
||||
(of one of these types) submitted to the HCD. The transfer associated with
|
||||
a URBD may require one or multiple transactions.
|
||||
|
||||
A URBD is linked to a EP Queue Head, which is entered in either the
|
||||
isoc, intr or non-periodic schedule for execution. When a URBD is chosen for
|
||||
execution, some or all of its transactions may be executed. After
|
||||
execution, the state of the URBD is updated. The URBD may be retired if all
|
||||
its transactions are complete or if an error occurred. Otherwise, it
|
||||
remains in the schedule so more transactions can be executed later.
|
||||
*/
|
||||
typedef struct ifxhcd_urbd {
|
||||
struct list_head urbd_list_entry; // Hook for EPQH->urbd_list and ifxhcd->urbd_complete_list
|
||||
struct urb *urb; /*!< URB for this transfer */
|
||||
//struct urb {
|
||||
// struct list_head urb_list;
|
||||
// struct list_head anchor_list;
|
||||
// struct usb_anchor * anchor;
|
||||
// struct usb_device * dev;
|
||||
// struct usb_host_endpoint * ep;
|
||||
// unsigned int pipe;
|
||||
// int status;
|
||||
// unsigned int transfer_flags;
|
||||
// void * transfer_buffer;
|
||||
// dma_addr_t transfer_dma;
|
||||
// u32 transfer_buffer_length;
|
||||
// u32 actual_length;
|
||||
// unsigned char * setup_packet;
|
||||
// dma_addr_t setup_dma;
|
||||
// int start_frame;
|
||||
// int number_of_packets;
|
||||
// int interval;
|
||||
// int error_count;
|
||||
// void * context;
|
||||
// usb_complete_t complete;
|
||||
// struct usb_iso_packet_descriptor iso_frame_desc[0];
|
||||
//};
|
||||
//urb_list For use by current owner of the URB.
|
||||
//anchor_list membership in the list of an anchor
|
||||
//anchor to anchor URBs to a common mooring
|
||||
//dev Identifies the USB device to perform the request.
|
||||
//ep Points to the endpoint's data structure. Will
|
||||
// eventually replace pipe.
|
||||
//pipe Holds endpoint number, direction, type, and more.
|
||||
// Create these values with the eight macros available; u
|
||||
// sb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is
|
||||
// "ctrl", "bulk", "int" or "iso". For example
|
||||
// usb_sndbulkpipe or usb_rcvintpipe. Endpoint numbers
|
||||
// range from zero to fifteen. Note that "in" endpoint two
|
||||
// is a different endpoint (and pipe) from "out" endpoint
|
||||
// two. The current configuration controls the existence,
|
||||
// type, and maximum packet size of any given endpoint.
|
||||
//status This is read in non-iso completion functions to get
|
||||
// the status of the particular request. ISO requests
|
||||
// only use it to tell whether the URB was unlinked;
|
||||
// detailed status for each frame is in the fields of
|
||||
// the iso_frame-desc.
|
||||
//transfer_flags A variety of flags may be used to affect how URB
|
||||
// submission, unlinking, or operation are handled.
|
||||
// Different kinds of URB can use different flags.
|
||||
// URB_SHORT_NOT_OK
|
||||
// URB_ISO_ASAP
|
||||
// URB_NO_TRANSFER_DMA_MAP
|
||||
// URB_NO_SETUP_DMA_MAP
|
||||
// URB_NO_FSBR
|
||||
// URB_ZERO_PACKET
|
||||
// URB_NO_INTERRUPT
|
||||
//transfer_buffer This identifies the buffer to (or from) which the I/O
|
||||
// request will be performed (unless URB_NO_TRANSFER_DMA_MAP
|
||||
// is set). This buffer must be suitable for DMA; allocate it
|
||||
// with kmalloc or equivalent. For transfers to "in"
|
||||
// endpoints, contents of this buffer will be modified. This
|
||||
// buffer is used for the data stage of control transfers.
|
||||
//transfer_dma When transfer_flags includes URB_NO_TRANSFER_DMA_MAP, the
|
||||
// device driver is saying that it provided this DMA address,
|
||||
// which the host controller driver should use in preference
|
||||
// to the transfer_buffer.
|
||||
//transfer_buffer_length How big is transfer_buffer. The transfer may be broken
|
||||
// up into chunks according to the current maximum packet size
|
||||
// for the endpoint, which is a function of the configuration
|
||||
// and is encoded in the pipe. When the length is zero, neither
|
||||
// transfer_buffer nor transfer_dma is used.
|
||||
//actual_length This is read in non-iso completion functions, and it tells
|
||||
// how many bytes (out of transfer_buffer_length) were transferred.
|
||||
// It will normally be the same as requested, unless either an error
|
||||
// was reported or a short read was performed. The URB_SHORT_NOT_OK
|
||||
// transfer flag may be used to make such short reads be reported
|
||||
// as errors.
|
||||
//setup_packet Only used for control transfers, this points to eight bytes of
|
||||
// setup data. Control transfers always start by sending this data
|
||||
// to the device. Then transfer_buffer is read or written, if needed.
|
||||
//setup_dma For control transfers with URB_NO_SETUP_DMA_MAP set, the device
|
||||
// driver has provided this DMA address for the setup packet. The
|
||||
// host controller driver should use this in preference to setup_packet.
|
||||
//start_frame Returns the initial frame for isochronous transfers.
|
||||
//number_of_packets Lists the number of ISO transfer buffers.
|
||||
//interval Specifies the polling interval for interrupt or isochronous transfers.
|
||||
// The units are frames (milliseconds) for for full and low speed devices,
|
||||
// and microframes (1/8 millisecond) for highspeed ones.
|
||||
//error_count Returns the number of ISO transfers that reported errors.
|
||||
//context For use in completion functions. This normally points to request-specific
|
||||
// driver context.
|
||||
//complete Completion handler. This URB is passed as the parameter to the completion
|
||||
// function. The completion function may then do what it likes with the URB,
|
||||
// including resubmitting or freeing it.
|
||||
//iso_frame_desc[0] Used to provide arrays of ISO transfer buffers and to collect the transfer
|
||||
// status for each buffer.
|
||||
|
||||
struct ifxhcd_epqh *epqh;
|
||||
// Actual data portion, not SETUP or STATUS in case of CTRL XFER
|
||||
// DMA adjusted
|
||||
uint8_t *setup_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/
|
||||
uint8_t *xfer_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/
|
||||
uint32_t xfer_len; /*!< Total number of bytes to transfer in this xfer. */
|
||||
unsigned is_in :1;
|
||||
unsigned is_active:1;
|
||||
|
||||
// For ALL XFER
|
||||
uint8_t error_count; /*!< Holds the number of bus errors that have occurred for a transaction
|
||||
within this transfer.
|
||||
*/
|
||||
/*== AVM/BC 20101111 Needed for URB Complete List ==*/
|
||||
int status;
|
||||
// For ISOC XFER only
|
||||
#ifdef __EN_ISOC__
|
||||
int isoc_frame_index; /*!< Index of the next frame descriptor for an isochronous transfer. A
|
||||
frame descriptor describes the buffer position and length of the
|
||||
data to be transferred in the next scheduled (micro)frame of an
|
||||
isochronous transfer. It also holds status for that transaction.
|
||||
The frame index starts at 0.
|
||||
*/
|
||||
// For SPLITed ISOC XFER only
|
||||
uint8_t isoc_split_pos; /*!< Position of the ISOC split on full/low speed */
|
||||
uint16_t isoc_split_offset;/*!< Position of the ISOC split in the buffer for the current frame */
|
||||
#endif
|
||||
} ifxhcd_urbd_t;
|
||||
|
||||
/*!
|
||||
\brief A EP Queue Head (EPQH) holds the static characteristics of an endpoint and
|
||||
maintains a list of transfers (URBDs) for that endpoint. A EPQH structure may
|
||||
be entered in either the isoc, intr or non-periodic schedule.
|
||||
*/
|
||||
|
||||
typedef struct ifxhcd_epqh {
|
||||
struct list_head epqh_list_entry; // Hook for EP Queues
|
||||
struct list_head urbd_list; /*!< List of URBDs for this EPQH. */
|
||||
struct ifxhcd_hc *hc; /*!< Host channel currently processing transfers for this EPQH. */
|
||||
struct ifxhcd_urbd *urbd; /*!< URBD currently assigned to a host channel for this EPQH. */
|
||||
struct usb_host_endpoint *sysep;
|
||||
uint8_t ep_type; /*!< Endpoint type. One of the following values:
|
||||
- IFXUSB_EP_TYPE_CTRL
|
||||
- IFXUSB_EP_TYPE_ISOC
|
||||
- IFXUSB_EP_TYPE_BULK
|
||||
- IFXUSB_EP_TYPE_INTR
|
||||
*/
|
||||
uint16_t mps; /*!< wMaxPacketSize Field of Endpoint Descriptor. */
|
||||
|
||||
/* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/
|
||||
/*uint8_t data_toggle;*/ /*!< Determines the PID of the next data packet
|
||||
One of the following values:
|
||||
- IFXHCD_HC_PID_DATA0
|
||||
- IFXHCD_HC_PID_DATA1
|
||||
*/
|
||||
uint8_t is_active;
|
||||
|
||||
uint8_t pkt_count_limit;
|
||||
#ifdef __EPQD_DESTROY_TIMEOUT__
|
||||
struct timer_list destroy_timer;
|
||||
#endif
|
||||
|
||||
uint16_t wait_for_sof;
|
||||
uint8_t need_split; /*!< Full/low speed endpoint on high-speed hub requires split. */
|
||||
uint16_t interval; /*!< Interval between transfers in (micro)frames. (for INTR)*/
|
||||
|
||||
uint16_t period_counter; /*!< Interval between transfers in (micro)frames. */
|
||||
uint8_t period_do;
|
||||
|
||||
uint8_t aligned_checked;
|
||||
|
||||
#if defined(__UNALIGNED_BUFFER_ADJ__)
|
||||
uint8_t using_aligned_setup;
|
||||
uint8_t *aligned_setup;
|
||||
uint8_t using_aligned_buf;
|
||||
uint8_t *aligned_buf;
|
||||
unsigned aligned_buf_len : 19;
|
||||
#endif
|
||||
|
||||
uint8_t *dump_buf;
|
||||
} ifxhcd_epqh_t;
|
||||
|
||||
|
||||
#if defined(__HC_XFER_TIMEOUT__)
|
||||
struct ifxusb_core_if;
|
||||
struct ifxhcd_hc;
|
||||
typedef struct hc_xfer_info
|
||||
{
|
||||
struct ifxusb_core_if *core_if;
|
||||
struct ifxhcd_hc *hc;
|
||||
} hc_xfer_info_t;
|
||||
#endif //defined(__HC_XFER_TIMEOUT__)
|
||||
|
||||
|
||||
/*!
|
||||
\brief Host channel descriptor. This structure represents the state of a single
|
||||
host channel when acting in host mode. It contains the data items needed to
|
||||
transfer packets to an endpoint via a host channel.
|
||||
*/
|
||||
typedef struct ifxhcd_hc
|
||||
{
|
||||
struct list_head hc_list_entry ; // Hook to free hc
|
||||
struct ifxhcd_epqh *epqh ; /*!< EP Queue Head for the transfer being processed by this channel. */
|
||||
|
||||
uint8_t hc_num ; /*!< Host channel number used for register address lookup */
|
||||
uint8_t *xfer_buff ; /*!< Pointer to the entire transfer buffer. */
|
||||
uint32_t xfer_count ; /*!< Number of bytes transferred so far. The offset of the begin of the buf */
|
||||
uint32_t xfer_len ; /*!< Total number of bytes to transfer in this xfer. */
|
||||
uint16_t start_pkt_count ; /*!< Packet count at start of transfer. Used to calculate the actual xfer size*/
|
||||
ifxhcd_halt_status_e halt_status; /*!< Reason for halting the host channel. */
|
||||
|
||||
unsigned dev_addr : 7; /*!< Device to access */
|
||||
unsigned ep_num : 4; /*!< EP to access */
|
||||
unsigned is_in : 1; /*!< EP direction. 0: OUT, 1: IN */
|
||||
unsigned speed : 2; /*!< EP speed. */
|
||||
unsigned ep_type : 2; /*!< Endpoint type. */
|
||||
unsigned mps :11; /*!< Max packet size in bytes */
|
||||
unsigned data_pid_start : 2; /*!< PID for initial transaction. */
|
||||
unsigned do_ping : 1; /*!< Set to 1 to indicate that a PING request should be issued on this
|
||||
channel. If 0, process normally.
|
||||
*/
|
||||
|
||||
unsigned xfer_started : 1; /*!< Flag to indicate whether the transfer has been started. Set to 1 if
|
||||
it has been started, 0 otherwise.
|
||||
*/
|
||||
unsigned halting : 1; /*!< Set to 1 if the host channel has been halted, but the core is not
|
||||
finished flushing queued requests. Otherwise 0.
|
||||
*/
|
||||
unsigned short_rw : 1; /*!< When Tx, means termination needed.
|
||||
When Rx, indicate Short Read */
|
||||
/* Split settings for the host channel */
|
||||
unsigned split : 2; /*!< Split: 0-Non Split, 1-SSPLIT, 2&3 CSPLIT */
|
||||
|
||||
/*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/
|
||||
unsigned nyet_count;
|
||||
|
||||
/* nak monitor */
|
||||
unsigned nak_retry_r : 16;
|
||||
unsigned nak_retry : 16;
|
||||
#define nak_retry_max 40000
|
||||
unsigned nak_countdown : 8;
|
||||
unsigned nak_countdown_r: 8;
|
||||
#define nak_countdown_max 1
|
||||
|
||||
uint16_t wait_for_sof;
|
||||
ifxhcd_control_phase_e control_phase; /*!< Current phase for control transfers (Setup, Data, or Status). */
|
||||
uint32_t ssplit_out_xfer_count; /*!< How many bytes transferred during SSPLIT OUT */
|
||||
#ifdef __DEBUG__
|
||||
uint32_t start_hcchar_val;
|
||||
#endif
|
||||
#ifdef __HC_XFER_TIMEOUT__
|
||||
hc_xfer_info_t hc_xfer_info;
|
||||
struct timer_list hc_xfer_timer;
|
||||
#endif
|
||||
uint32_t hcchar;
|
||||
|
||||
/* Split settings for the host channel */
|
||||
uint8_t hub_addr; /*!< Address of high speed hub */
|
||||
uint8_t port_addr; /*!< Port of the low/full speed device */
|
||||
#ifdef __EN_ISOC__
|
||||
uint8_t isoc_xact_pos; /*!< Split transaction position */
|
||||
#endif
|
||||
} ifxhcd_hc_t;
|
||||
|
||||
|
||||
/*!
|
||||
\brief This structure holds the state of the HCD, including the non-periodic and
|
||||
periodic schedules.
|
||||
*/
|
||||
typedef struct ifxhcd_hcd
|
||||
{
|
||||
struct device *dev;
|
||||
struct hc_driver hc_driver;
|
||||
ifxusb_core_if_t core_if; /*!< Pointer to the core interface structure. */
|
||||
struct usb_hcd *syshcd;
|
||||
|
||||
volatile union ifxhcd_internal_flags
|
||||
{
|
||||
uint32_t d32;
|
||||
struct
|
||||
{
|
||||
unsigned port_connect_status_change : 1;
|
||||
unsigned port_connect_status : 1;
|
||||
unsigned port_reset_change : 1;
|
||||
unsigned port_enable_change : 1;
|
||||
unsigned port_suspend_change : 1;
|
||||
unsigned port_over_current_change : 1;
|
||||
unsigned reserved : 27;
|
||||
} b;
|
||||
} flags; /*!< Internal HCD Flags */
|
||||
|
||||
struct ifxhcd_hc ifxhc[MAX_EPS_CHANNELS]; /*!< Array of pointers to the host channel descriptors. Allows accessing
|
||||
a host channel descriptor given the host channel number. This is
|
||||
useful in interrupt handlers.
|
||||
*/
|
||||
struct list_head free_hc_list; /*!< Free host channels in the controller. This is a list of ifxhcd_hc_t items. */
|
||||
uint8_t *status_buf; /*!< Buffer to use for any data received during the status phase of a
|
||||
control transfer. Normally no data is transferred during the status
|
||||
phase. This buffer is used as a bit bucket.
|
||||
*/
|
||||
#define IFXHCD_STATUS_BUF_SIZE 64
|
||||
|
||||
struct list_head epqh_np_active; // with URBD, with HC
|
||||
struct list_head epqh_np_ready; // with URBD, No HC
|
||||
|
||||
struct list_head epqh_intr_active; // with URBD, with HC
|
||||
struct list_head epqh_intr_ready; // with URBD, no pass, No HC
|
||||
|
||||
#ifdef __EN_ISOC__
|
||||
struct list_head epqh_isoc_active; // with URBD, with HC
|
||||
struct list_head epqh_isoc_ready; // with URBD, no pass, No HC
|
||||
#endif
|
||||
|
||||
/*== AVM/BC 20101111 URB Complete List ==*/
|
||||
struct list_head urbd_complete_list;
|
||||
|
||||
struct list_head epqh_stdby;
|
||||
|
||||
/* AVM/BC 20101111 flags removed */
|
||||
//unsigned process_channels_in_use : 1;
|
||||
//unsigned select_eps_in_use : 1;
|
||||
|
||||
struct tasklet_struct select_eps; /*!< Tasket to do a reset */
|
||||
uint32_t lastframe;
|
||||
spinlock_t lock;
|
||||
#ifdef __USE_TIMER_4_SOF__
|
||||
struct hrtimer hr_timer;
|
||||
#endif
|
||||
} ifxhcd_hcd_t;
|
||||
|
||||
/* Gets the ifxhcd_hcd from a struct usb_hcd */
|
||||
static inline ifxhcd_hcd_t *syshcd_to_ifxhcd(struct usb_hcd *syshcd)
|
||||
{
|
||||
return (ifxhcd_hcd_t *)(syshcd->hcd_priv[0]);
|
||||
}
|
||||
|
||||
/* Gets the struct usb_hcd that contains a ifxhcd_hcd_t. */
|
||||
static inline struct usb_hcd *ifxhcd_to_syshcd(ifxhcd_hcd_t *ifxhcd)
|
||||
{
|
||||
return (struct usb_hcd *)(ifxhcd->syshcd);
|
||||
}
|
||||
|
||||
/*! \brief HCD Create/Destroy Functions */
|
||||
/*@{*/
|
||||
extern int ifxhcd_init (ifxhcd_hcd_t *_ifxhcd);
|
||||
extern void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd);
|
||||
/*@}*/
|
||||
|
||||
/*! \brief Linux HC Driver API Functions */
|
||||
/*@{*/
|
||||
extern int ifxhcd_start(struct usb_hcd *hcd);
|
||||
extern void ifxhcd_stop (struct usb_hcd *hcd);
|
||||
extern int ifxhcd_get_frame_number(struct usb_hcd *hcd);
|
||||
|
||||
|
||||
/*!
|
||||
\brief This function does the setup for a data transfer for a host channel and
|
||||
starts the transfer. May be called in either Slave mode or DMA mode. In
|
||||
Slave mode, the caller must ensure that there is sufficient space in the
|
||||
request queue and Tx Data FIFO.
|
||||
|
||||
For an OUT transfer in Slave mode, it loads a data packet into the
|
||||
appropriate FIFO. If necessary, additional data packets will be loaded in
|
||||
the Host ISR.
|
||||
|
||||
For an IN transfer in Slave mode, a data packet is requested. The data
|
||||
packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
|
||||
additional data packets are requested in the Host ISR.
|
||||
|
||||
For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
|
||||
register along with a packet count of 1 and the channel is enabled. This
|
||||
causes a single PING transaction to occur. Other fields in HCTSIZ are
|
||||
simply set to 0 since no data transfer occurs in this case.
|
||||
|
||||
For a PING transfer in DMA mode, the HCTSIZ register is initialized with
|
||||
all the information required to perform the subsequent data transfer. In
|
||||
addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
|
||||
controller performs the entire PING protocol, then starts the data
|
||||
transfer.
|
||||
|
||||
@param _ifxhc Information needed to initialize the host channel. The xfer_len
|
||||
value may be reduced to accommodate the max widths of the XferSize and
|
||||
PktCnt fields in the HCTSIZn register. The multi_count value may be changed
|
||||
to reflect the final xfer_len value.
|
||||
*/
|
||||
extern void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
|
||||
|
||||
//extern int ifxhcd_urb_enqueue(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep, struct urb *_urb, gfp_t mem_flags);
|
||||
//extern int ifxhcd_urb_dequeue(struct usb_hcd *_syshcd, struct urb *_urb);
|
||||
extern irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd);
|
||||
int ifxhcd_urb_enqueue( struct usb_hcd *_syshcd,
|
||||
/*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/
|
||||
struct urb *_urb,
|
||||
gfp_t _mem_flags);
|
||||
int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd,
|
||||
struct urb *_urb, int status /* Parameter neu in 2.6.28 */);
|
||||
|
||||
extern void ifxhcd_endpoint_disable(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep);
|
||||
|
||||
extern int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf);
|
||||
extern int ifxhcd_hub_control( struct usb_hcd *_syshcd,
|
||||
u16 _typeReq,
|
||||
u16 _wValue,
|
||||
u16 _wIndex,
|
||||
char *_buf,
|
||||
u16 _wLength);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! \brief Transaction Execution Functions */
|
||||
/*@{*/
|
||||
extern void ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! \brief Deferred Transaction Execution Functions */
|
||||
/*@{*/
|
||||
|
||||
/*== AVM/BC 20101111 URB Complete List ==*/
|
||||
extern void defer_ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status);
|
||||
|
||||
/*!
|
||||
\brief Clears the transfer state for a host channel. This function is normally
|
||||
called after a transfer is done and the host channel is being released.
|
||||
*/
|
||||
extern void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
|
||||
|
||||
/*!
|
||||
\brief Attempts to halt a host channel. This function should only be called in
|
||||
Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
|
||||
normal circumstances in DMA mode, the controller halts the channel when the
|
||||
transfer is complete or a condition occurs that requires application
|
||||
intervention.
|
||||
|
||||
In slave mode, checks for a free request queue entry, then sets the Channel
|
||||
Enable and Channel Disable bits of the Host Channel Characteristics
|
||||
register of the specified channel to intiate the halt. If there is no free
|
||||
request queue entry, sets only the Channel Disable bit of the HCCHARn
|
||||
register to flush requests for this channel. In the latter case, sets a
|
||||
flag to indicate that the host channel needs to be halted when a request
|
||||
queue slot is open.
|
||||
|
||||
In DMA mode, always sets the Channel Enable and Channel Disable bits of the
|
||||
HCCHARn register. The controller ensures there is space in the request
|
||||
queue before submitting the halt request.
|
||||
|
||||
Some time may elapse before the core flushes any posted requests for this
|
||||
host channel and halts. The Channel Halted interrupt handler completes the
|
||||
deactivation of the host channel.
|
||||
*/
|
||||
extern void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if,
|
||||
ifxhcd_hc_t *_ifxhc,
|
||||
ifxhcd_halt_status_e _halt_status);
|
||||
|
||||
/*!
|
||||
\brief Prepares a host channel for transferring packets to/from a specific
|
||||
endpoint. The HCCHARn register is set up with the characteristics specified
|
||||
in _ifxhc. Host channel interrupts that may need to be serviced while this
|
||||
transfer is in progress are enabled.
|
||||
*/
|
||||
extern void ifxhcd_hc_init(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc);
|
||||
|
||||
/*!
|
||||
\brief This function is called to handle the disconnection of host port.
|
||||
*/
|
||||
int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd);
|
||||
/*@}*/
|
||||
|
||||
/*! \brief Interrupt Handler Functions */
|
||||
/*@{*/
|
||||
extern irqreturn_t ifxhcd_oc_irq(int _irq, void *_dev);
|
||||
|
||||
extern int32_t ifxhcd_handle_oc_intr(ifxhcd_hcd_t *_ifxhcd);
|
||||
extern int32_t ifxhcd_handle_intr (ifxhcd_hcd_t *_ifxhcd);
|
||||
/*@}*/
|
||||
|
||||
|
||||
/*! \brief Schedule Queue Functions */
|
||||
/*@{*/
|
||||
extern ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb);
|
||||
extern void ifxhcd_epqh_free ( ifxhcd_epqh_t *_epqh);
|
||||
extern void select_eps (ifxhcd_hcd_t *_ifxhcd);
|
||||
extern void process_channels(ifxhcd_hcd_t *_ifxhcd);
|
||||
extern void process_channels_sub(ifxhcd_hcd_t *_ifxhcd);
|
||||
extern void complete_channel(ifxhcd_hcd_t *_ifxhcd, ifxhcd_hc_t *_ifxhc, ifxhcd_urbd_t *_urbd);
|
||||
extern void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
|
||||
extern void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
|
||||
extern void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh);
|
||||
extern void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh);
|
||||
extern int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb);
|
||||
/*@}*/
|
||||
|
||||
/*! \brief Gets the usb_host_endpoint associated with an URB. */
|
||||
static inline struct usb_host_endpoint *ifxhcd_urb_to_endpoint(struct urb *_urb)
|
||||
{
|
||||
struct usb_device *dev = _urb->dev;
|
||||
int ep_num = usb_pipeendpoint(_urb->pipe);
|
||||
|
||||
return (usb_pipein(_urb->pipe))?(dev->ep_in[ep_num]):(dev->ep_out[ep_num]);
|
||||
}
|
||||
|
||||
/*!
|
||||
* \brief Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
|
||||
* qualified with its direction (possible 32 endpoints per device).
|
||||
*/
|
||||
#define ifxhcd_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
|
||||
((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
|
||||
|
||||
|
||||
/* AVM/WK: not needed?
|
||||
|
||||
extern struct usb_device *usb_alloc_dev (struct usb_device *parent, struct usb_bus *, unsigned port);
|
||||
extern int usb_add_hcd (struct usb_hcd *syshcd, unsigned int irqnum, unsigned long irqflags);
|
||||
extern void usb_remove_hcd (struct usb_hcd *syshcd);
|
||||
extern struct usb_hcd *usb_create_hcd (const struct hc_driver *driver, struct device *dev, char *bus_name);
|
||||
extern void usb_hcd_giveback_urb (struct usb_hcd *syshcd, struct urb *urb);
|
||||
extern void usb_put_hcd (struct usb_hcd *syshcd);
|
||||
extern long usb_calc_bus_time (int speed, int is_input, int isoc, int bytecount);
|
||||
|
||||
*/
|
||||
/** Internal Functions */
|
||||
void ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd);
|
||||
extern char *syserr(int errno);
|
||||
|
||||
/*@}*//*IFXUSB_HCD*/
|
||||
|
||||
#endif // __IFXHCD_H__
|
||||
549
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_es.c
Normal file
549
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_es.c
Normal file
@@ -0,0 +1,549 @@
|
||||
/*****************************************************************************
|
||||
** FILE NAME : ifxhcd_es.c
|
||||
** PROJECT : IFX USB sub-system V3
|
||||
** MODULES : IFX USB sub-system Host and Device driver
|
||||
** SRC VERSION : 1.0
|
||||
** DATE : 1/Jan/2009
|
||||
** AUTHOR : Chen, Howard
|
||||
** DESCRIPTION : The file contain function to enable host mode USB-IF Electrical Test function.
|
||||
*****************************************************************************/
|
||||
|
||||
/*!
|
||||
\file ifxhcd_es.c
|
||||
\ingroup IFXUSB_DRIVER_V3
|
||||
\brief The file contain function to enable host mode USB-IF Electrical Test function.
|
||||
*/
|
||||
|
||||
#include <linux/version.h>
|
||||
#include "ifxusb_version.h"
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <linux/errno.h>
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include "ifxusb_plat.h"
|
||||
#include "ifxusb_regs.h"
|
||||
#include "ifxusb_cif.h"
|
||||
#include "ifxhcd.h"
|
||||
|
||||
|
||||
#ifdef __WITH_HS_ELECT_TST__
|
||||
/*
|
||||
* Quick and dirty hack to implement the HS Electrical Test
|
||||
* SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
|
||||
*
|
||||
* This code was copied from our userspace app "hset". It sends a
|
||||
* Get Device Descriptor control sequence in two parts, first the
|
||||
* Setup packet by itself, followed some time later by the In and
|
||||
* Ack packets. Rather than trying to figure out how to add this
|
||||
* functionality to the normal driver code, we just hijack the
|
||||
* hardware, using these two function to drive the hardware
|
||||
* directly.
|
||||
*/
|
||||
|
||||
|
||||
void do_setup(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
|
||||
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
||||
ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
|
||||
ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0];
|
||||
uint32_t *data_fifo = _core_if->data_fifo[0];
|
||||
|
||||
gint_data_t gintsts;
|
||||
hctsiz_data_t hctsiz;
|
||||
hcchar_data_t hcchar;
|
||||
haint_data_t haint;
|
||||
hcint_data_t hcint;
|
||||
|
||||
|
||||
/* Enable HAINTs */
|
||||
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
|
||||
|
||||
/* Enable HCINTs */
|
||||
ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/*
|
||||
* Send Setup packet (Get Device Descriptor)
|
||||
*/
|
||||
|
||||
/* Make sure channel is disabled */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
if (hcchar.b.chen) {
|
||||
//fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
|
||||
hcchar.b.chdis = 1;
|
||||
// hcchar.b.chen = 1;
|
||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
//sleep(1);
|
||||
mdelay(1000);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//if (hcchar.b.chen) {
|
||||
// fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
|
||||
//}
|
||||
}
|
||||
|
||||
/* Set HCTSIZ */
|
||||
hctsiz.d32 = 0;
|
||||
hctsiz.b.xfersize = 8;
|
||||
hctsiz.b.pktcnt = 1;
|
||||
hctsiz.b.pid = IFXUSB_HC_PID_SETUP;
|
||||
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
|
||||
|
||||
/* Set HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
|
||||
hcchar.b.epdir = 0;
|
||||
hcchar.b.epnum = 0;
|
||||
hcchar.b.mps = 8;
|
||||
hcchar.b.chen = 1;
|
||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
|
||||
/* Fill FIFO with Setup data for Get Device Descriptor */
|
||||
ifxusb_wreg(data_fifo++, 0x01000680);
|
||||
ifxusb_wreg(data_fifo++, 0x00080000);
|
||||
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for host channel interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.hcintr == 0);
|
||||
|
||||
//fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Disable HCINTs */
|
||||
ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
|
||||
|
||||
/* Disable HAINTs */
|
||||
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
}
|
||||
|
||||
void do_in_ack(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
|
||||
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
||||
ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
|
||||
ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0];
|
||||
uint32_t *data_fifo = _core_if->data_fifo[0];
|
||||
|
||||
gint_data_t gintsts;
|
||||
hctsiz_data_t hctsiz;
|
||||
hcchar_data_t hcchar;
|
||||
haint_data_t haint;
|
||||
hcint_data_t hcint;
|
||||
grxsts_data_t grxsts;
|
||||
|
||||
/* Enable HAINTs */
|
||||
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
|
||||
|
||||
/* Enable HCINTs */
|
||||
ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/*
|
||||
* Receive Control In packet
|
||||
*/
|
||||
|
||||
/* Make sure channel is disabled */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
if (hcchar.b.chen) {
|
||||
//fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
|
||||
hcchar.b.chdis = 1;
|
||||
hcchar.b.chen = 1;
|
||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
//sleep(1);
|
||||
mdelay(1000);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//if (hcchar.b.chen) {
|
||||
// fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
|
||||
//}
|
||||
}
|
||||
|
||||
/* Set HCTSIZ */
|
||||
hctsiz.d32 = 0;
|
||||
hctsiz.b.xfersize = 8;
|
||||
hctsiz.b.pktcnt = 1;
|
||||
hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
|
||||
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
|
||||
|
||||
/* Set HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
|
||||
hcchar.b.epdir = 1;
|
||||
hcchar.b.epnum = 0;
|
||||
hcchar.b.mps = 8;
|
||||
hcchar.b.chen = 1;
|
||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for receive status queue interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.rxstsqlvl == 0);
|
||||
|
||||
//fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Read RXSTS */
|
||||
grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
|
||||
//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
|
||||
|
||||
/* Clear RXSTSQLVL in GINTSTS */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.rxstsqlvl = 1;
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
switch (grxsts.hb.pktsts) {
|
||||
case IFXUSB_HSTS_DATA_UPDT:
|
||||
/* Read the data into the host buffer */
|
||||
if (grxsts.hb.bcnt > 0) {
|
||||
int i;
|
||||
int word_count = (grxsts.hb.bcnt + 3) / 4;
|
||||
|
||||
for (i = 0; i < word_count; i++) {
|
||||
(void)ifxusb_rreg(data_fifo++);
|
||||
}
|
||||
}
|
||||
|
||||
//fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.hb.bcnt);
|
||||
break;
|
||||
|
||||
default:
|
||||
//fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
|
||||
break;
|
||||
}
|
||||
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for receive status queue interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.rxstsqlvl == 0);
|
||||
|
||||
//fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Read RXSTS */
|
||||
grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
|
||||
//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
|
||||
|
||||
/* Clear RXSTSQLVL in GINTSTS */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.rxstsqlvl = 1;
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
switch (grxsts.hb.pktsts) {
|
||||
case IFXUSB_HSTS_XFER_COMP:
|
||||
break;
|
||||
|
||||
default:
|
||||
//fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
|
||||
break;
|
||||
}
|
||||
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for host channel interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.hcintr == 0);
|
||||
|
||||
//fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
// usleep(100000);
|
||||
// mdelay(100);
|
||||
mdelay(1);
|
||||
|
||||
/*
|
||||
* Send handshake packet
|
||||
*/
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/* Make sure channel is disabled */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
if (hcchar.b.chen) {
|
||||
//fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
|
||||
hcchar.b.chdis = 1;
|
||||
hcchar.b.chen = 1;
|
||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
//sleep(1);
|
||||
mdelay(1000);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//if (hcchar.b.chen) {
|
||||
// fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
|
||||
//}
|
||||
}
|
||||
|
||||
/* Set HCTSIZ */
|
||||
hctsiz.d32 = 0;
|
||||
hctsiz.b.xfersize = 0;
|
||||
hctsiz.b.pktcnt = 1;
|
||||
hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
|
||||
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
|
||||
|
||||
/* Set HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
|
||||
hcchar.b.epdir = 0;
|
||||
hcchar.b.epnum = 0;
|
||||
hcchar.b.mps = 8;
|
||||
hcchar.b.chen = 1;
|
||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for host channel interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.hcintr == 0);
|
||||
|
||||
//fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Disable HCINTs */
|
||||
ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
|
||||
|
||||
/* Disable HAINTs */
|
||||
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
}
|
||||
#endif //__WITH_HS_ELECT_TST__
|
||||
|
||||
3742
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_intr.c
Normal file
3742
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_intr.c
Normal file
File diff suppressed because it is too large
Load Diff
418
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_queue.c
Normal file
418
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_queue.c
Normal file
@@ -0,0 +1,418 @@
|
||||
/*****************************************************************************
|
||||
** FILE NAME : ifxhcd_queue.c
|
||||
** PROJECT : IFX USB sub-system V3
|
||||
** MODULES : IFX USB sub-system Host and Device driver
|
||||
** SRC VERSION : 1.0
|
||||
** DATE : 1/Jan/2009
|
||||
** AUTHOR : Chen, Howard
|
||||
** DESCRIPTION : This file contains the functions to manage Queue Heads and Queue
|
||||
** Transfer Descriptors.
|
||||
*****************************************************************************/
|
||||
|
||||
/*!
|
||||
\file ifxhcd_queue.c
|
||||
\ingroup IFXUSB_DRIVER_V3
|
||||
\brief This file contains the functions to manage Queue Heads and Queue
|
||||
Transfer Descriptors.
|
||||
*/
|
||||
#include <linux/version.h>
|
||||
#include "ifxusb_version.h"
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include "ifxusb_plat.h"
|
||||
#include "ifxusb_regs.h"
|
||||
#include "ifxusb_cif.h"
|
||||
#include "ifxhcd.h"
|
||||
|
||||
#ifdef __EPQD_DESTROY_TIMEOUT__
|
||||
#define epqh_self_destroy_timeout 5
|
||||
static void eqph_destroy_func(unsigned long _ptr)
|
||||
{
|
||||
ifxhcd_epqh_t *epqh=(ifxhcd_epqh_t *)_ptr;
|
||||
if(epqh)
|
||||
{
|
||||
ifxhcd_epqh_free (epqh);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#define SCHEDULE_SLOP 10
|
||||
|
||||
/*!
|
||||
\brief This function allocates and initializes a EPQH.
|
||||
|
||||
\param _ifxhcd The HCD state structure for the USB Host controller.
|
||||
\param[in] _urb Holds the information about the device/endpoint that we need
|
||||
to initialize the EPQH.
|
||||
|
||||
\return Returns pointer to the newly allocated EPQH, or NULL on error.
|
||||
*/
|
||||
ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb)
|
||||
{
|
||||
ifxhcd_epqh_t *epqh;
|
||||
|
||||
hprt0_data_t hprt0;
|
||||
struct usb_host_endpoint *sysep = ifxhcd_urb_to_endpoint(_urb);
|
||||
|
||||
/* Allocate memory */
|
||||
// epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_KERNEL);
|
||||
epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_ATOMIC);
|
||||
|
||||
if(epqh == NULL)
|
||||
return NULL;
|
||||
|
||||
memset (epqh, 0, sizeof (ifxhcd_epqh_t));
|
||||
|
||||
epqh->sysep=sysep;
|
||||
|
||||
/* Initialize EPQH */
|
||||
switch (usb_pipetype(_urb->pipe))
|
||||
{
|
||||
case PIPE_CONTROL : epqh->ep_type = IFXUSB_EP_TYPE_CTRL; break;
|
||||
case PIPE_BULK : epqh->ep_type = IFXUSB_EP_TYPE_BULK; break;
|
||||
case PIPE_ISOCHRONOUS: epqh->ep_type = IFXUSB_EP_TYPE_ISOC; break;
|
||||
case PIPE_INTERRUPT : epqh->ep_type = IFXUSB_EP_TYPE_INTR; break;
|
||||
}
|
||||
|
||||
//epqh->data_toggle = IFXUSB_HC_PID_DATA0;
|
||||
|
||||
epqh->mps = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
|
||||
|
||||
hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if);
|
||||
|
||||
INIT_LIST_HEAD(&epqh->urbd_list);
|
||||
INIT_LIST_HEAD(&epqh->epqh_list_entry);
|
||||
epqh->hc = NULL;
|
||||
|
||||
epqh->dump_buf = ifxusb_alloc_buf(epqh->mps, 0);
|
||||
|
||||
/* FS/LS Enpoint on HS Hub
|
||||
* NOT virtual root hub */
|
||||
epqh->need_split = 0;
|
||||
epqh->pkt_count_limit=0;
|
||||
if(epqh->ep_type == IFXUSB_EP_TYPE_BULK && !(usb_pipein(_urb->pipe)) )
|
||||
epqh->pkt_count_limit=4;
|
||||
if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED &&
|
||||
((_urb->dev->speed == USB_SPEED_LOW) ||
|
||||
(_urb->dev->speed == USB_SPEED_FULL)) &&
|
||||
(_urb->dev->tt) && (_urb->dev->tt->hub->devnum != 1))
|
||||
{
|
||||
IFX_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
|
||||
usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
|
||||
_urb->dev->ttport);
|
||||
epqh->need_split = 1;
|
||||
epqh->pkt_count_limit=1;
|
||||
}
|
||||
|
||||
if (epqh->ep_type == IFXUSB_EP_TYPE_INTR ||
|
||||
epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
|
||||
{
|
||||
/* Compute scheduling parameters once and save them. */
|
||||
epqh->interval = _urb->interval;
|
||||
if(epqh->need_split)
|
||||
epqh->interval *= 8;
|
||||
}
|
||||
|
||||
epqh->period_counter=0;
|
||||
epqh->is_active=0;
|
||||
|
||||
#ifdef __EPQD_DESTROY_TIMEOUT__
|
||||
/* Start a timer for this transfer. */
|
||||
init_timer(&epqh->destroy_timer);
|
||||
epqh->destroy_timer.function = eqph_destroy_func;
|
||||
epqh->destroy_timer.data = (unsigned long)(epqh);
|
||||
#endif
|
||||
|
||||
#ifdef __DEBUG__
|
||||
IFX_DEBUGPL(DBG_HCD , "IFXUSB HCD EPQH Initialized\n");
|
||||
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - epqh = %p\n", epqh);
|
||||
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Device Address = %d EP %d, %s\n",
|
||||
_urb->dev->devnum,
|
||||
usb_pipeendpoint(_urb->pipe),
|
||||
usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
|
||||
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Speed = %s\n",
|
||||
({ char *speed; switch (_urb->dev->speed) {
|
||||
case USB_SPEED_LOW: speed = "low" ; break;
|
||||
case USB_SPEED_FULL: speed = "full"; break;
|
||||
case USB_SPEED_HIGH: speed = "high"; break;
|
||||
default: speed = "?"; break;
|
||||
}; speed;}));
|
||||
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Type = %s\n",
|
||||
({
|
||||
char *type; switch (epqh->ep_type)
|
||||
{
|
||||
case IFXUSB_EP_TYPE_ISOC: type = "isochronous"; break;
|
||||
case IFXUSB_EP_TYPE_INTR: type = "interrupt" ; break;
|
||||
case IFXUSB_EP_TYPE_CTRL: type = "control" ; break;
|
||||
case IFXUSB_EP_TYPE_BULK: type = "bulk" ; break;
|
||||
default: type = "?"; break;
|
||||
};
|
||||
type;
|
||||
}));
|
||||
if (epqh->ep_type == IFXUSB_EP_TYPE_INTR)
|
||||
IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - interval = %d\n", epqh->interval);
|
||||
#endif
|
||||
|
||||
return epqh;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\brief Free the EPQH. EPQH should already be removed from a list.
|
||||
URBD list should already be empty if called from URB Dequeue.
|
||||
|
||||
\param[in] _epqh The EPQH to free.
|
||||
*/
|
||||
void ifxhcd_epqh_free (ifxhcd_epqh_t *_epqh)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if(_epqh->sysep) _epqh->sysep->hcpriv=NULL;
|
||||
_epqh->sysep=NULL;
|
||||
|
||||
if(!_epqh)
|
||||
return;
|
||||
|
||||
/* Free each QTD in the QTD list */
|
||||
local_irq_save (flags);
|
||||
if (!list_empty(&_epqh->urbd_list))
|
||||
IFX_WARN("%s() invalid epqh state\n",__func__);
|
||||
|
||||
#if defined(__UNALIGNED_BUFFER_ADJ__)
|
||||
if(_epqh->aligned_buf)
|
||||
ifxusb_free_buf(_epqh->aligned_buf);
|
||||
if(_epqh->aligned_setup)
|
||||
ifxusb_free_buf(_epqh->aligned_setup);
|
||||
#endif
|
||||
|
||||
if (!list_empty(&_epqh->epqh_list_entry))
|
||||
list_del_init(&_epqh->epqh_list_entry);
|
||||
|
||||
#ifdef __EPQD_DESTROY_TIMEOUT__
|
||||
del_timer(&_epqh->destroy_timer);
|
||||
#endif
|
||||
if(_epqh->dump_buf)
|
||||
ifxusb_free_buf(_epqh->dump_buf);
|
||||
_epqh->dump_buf=0;
|
||||
|
||||
|
||||
kfree (_epqh);
|
||||
local_irq_restore (flags);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief This function adds a EPQH to
|
||||
|
||||
\return 0 if successful, negative error code otherwise.
|
||||
*/
|
||||
void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
|
||||
{
|
||||
unsigned long flags;
|
||||
local_irq_save(flags);
|
||||
if (list_empty(&_epqh->epqh_list_entry))
|
||||
{
|
||||
#ifdef __EN_ISOC__
|
||||
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
|
||||
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
|
||||
else
|
||||
#endif
|
||||
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
|
||||
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
|
||||
else
|
||||
list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
|
||||
_epqh->is_active=0;
|
||||
}
|
||||
else if(!_epqh->is_active)
|
||||
{
|
||||
#ifdef __EN_ISOC__
|
||||
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
|
||||
else
|
||||
#endif
|
||||
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
|
||||
else
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
|
||||
}
|
||||
#ifdef __EPQD_DESTROY_TIMEOUT__
|
||||
del_timer(&_epqh->destroy_timer);
|
||||
#endif
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
|
||||
{
|
||||
unsigned long flags;
|
||||
local_irq_save(flags);
|
||||
if (list_empty(&_epqh->epqh_list_entry))
|
||||
IFX_WARN("%s() invalid epqh state\n",__func__);
|
||||
#ifdef __EN_ISOC__
|
||||
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active);
|
||||
else
|
||||
#endif
|
||||
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active);
|
||||
else
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_active);
|
||||
_epqh->is_active=1;
|
||||
#ifdef __EPQD_DESTROY_TIMEOUT__
|
||||
del_timer(&_epqh->destroy_timer);
|
||||
#endif
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh)
|
||||
{
|
||||
unsigned long flags;
|
||||
local_irq_save(flags);
|
||||
|
||||
if (list_empty(&_epqh->urbd_list))
|
||||
{
|
||||
if(_epqh->ep_type == IFXUSB_EP_TYPE_ISOC || _epqh->ep_type == IFXUSB_EP_TYPE_INTR)
|
||||
{
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_stdby);
|
||||
}
|
||||
else
|
||||
{
|
||||
list_del_init(&_epqh->epqh_list_entry);
|
||||
#ifdef __EPQD_DESTROY_TIMEOUT__
|
||||
del_timer(&_epqh->destroy_timer);
|
||||
_epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout);
|
||||
add_timer(&_epqh->destroy_timer );
|
||||
#endif
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef __EN_ISOC__
|
||||
if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC)
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready);
|
||||
else
|
||||
#endif
|
||||
if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR)
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready);
|
||||
else
|
||||
list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready);
|
||||
}
|
||||
_epqh->is_active=0;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
||||
void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh)
|
||||
{
|
||||
unsigned long flags;
|
||||
if(_epqh->ep_type != IFXUSB_EP_TYPE_ISOC && _epqh->ep_type != IFXUSB_EP_TYPE_INTR)
|
||||
return;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
if (list_empty(&_epqh->epqh_list_entry))
|
||||
IFX_WARN("%s() invalid epqh state\n",__func__);
|
||||
if (!list_empty(&_epqh->urbd_list))
|
||||
IFX_WARN("%s() invalid epqh state(not empty)\n",__func__);
|
||||
|
||||
_epqh->is_active=0;
|
||||
list_del_init(&_epqh->epqh_list_entry);
|
||||
#ifdef __EPQD_DESTROY_TIMEOUT__
|
||||
del_timer(&_epqh->destroy_timer);
|
||||
_epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout);
|
||||
add_timer(&_epqh->destroy_timer );
|
||||
#endif
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
||||
int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb)
|
||||
{
|
||||
ifxhcd_urbd_t *urbd;
|
||||
struct usb_host_endpoint *sysep;
|
||||
ifxhcd_epqh_t *epqh;
|
||||
unsigned long flags;
|
||||
/* == AVM/WK 20100714 retval correctly initialized ==*/
|
||||
int retval = -ENOMEM;
|
||||
|
||||
/*== AVM/BC 20100630 - Spinlock ==*/
|
||||
//local_irq_save(flags);
|
||||
SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags);
|
||||
|
||||
// urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_KERNEL);
|
||||
urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_ATOMIC);
|
||||
if (urbd != NULL) /* Initializes a QTD structure.*/
|
||||
{
|
||||
retval = 0;
|
||||
memset (urbd, 0, sizeof (ifxhcd_urbd_t));
|
||||
|
||||
sysep = ifxhcd_urb_to_endpoint(_urb);
|
||||
epqh = (ifxhcd_epqh_t *)sysep->hcpriv;
|
||||
if (epqh == NULL)
|
||||
{
|
||||
epqh = ifxhcd_epqh_create (_ifxhcd, _urb);
|
||||
if (epqh == NULL)
|
||||
{
|
||||
retval = -ENOSPC;
|
||||
kfree(urbd);
|
||||
//local_irq_restore (flags);
|
||||
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
|
||||
return retval;
|
||||
}
|
||||
sysep->hcpriv = epqh;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&urbd->urbd_list_entry);
|
||||
|
||||
/*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/
|
||||
retval = usb_hcd_link_urb_to_ep(ifxhcd_to_syshcd(_ifxhcd), _urb);
|
||||
|
||||
if (unlikely(retval)){
|
||||
kfree(urbd);
|
||||
kfree(epqh);
|
||||
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
list_add_tail(&urbd->urbd_list_entry, &epqh->urbd_list);
|
||||
urbd->urb = _urb;
|
||||
_urb->hcpriv = urbd;
|
||||
|
||||
urbd->epqh=epqh;
|
||||
urbd->is_in=usb_pipein(_urb->pipe) ? 1 : 0;;
|
||||
|
||||
urbd->xfer_len=_urb->transfer_buffer_length;
|
||||
#define URB_NO_SETUP_DMA_MAP 0
|
||||
|
||||
if(urbd->xfer_len>0)
|
||||
{
|
||||
if(_urb->transfer_flags && URB_NO_TRANSFER_DMA_MAP)
|
||||
urbd->xfer_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->transfer_dma));
|
||||
else
|
||||
urbd->xfer_buff = (uint8_t *) _urb->transfer_buffer;
|
||||
}
|
||||
if(epqh->ep_type == IFXUSB_EP_TYPE_CTRL)
|
||||
{
|
||||
if(_urb->transfer_flags && URB_NO_SETUP_DMA_MAP)
|
||||
urbd->setup_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->setup_dma));
|
||||
else
|
||||
urbd->setup_buff = (uint8_t *) _urb->setup_packet;
|
||||
}
|
||||
}
|
||||
//local_irq_restore (flags);
|
||||
SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
1458
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif.c
Normal file
1458
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif.c
Normal file
File diff suppressed because it is too large
Load Diff
665
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif.h
Normal file
665
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif.h
Normal file
@@ -0,0 +1,665 @@
|
||||
/*****************************************************************************
|
||||
** FILE NAME : ifxusb_cif.h
|
||||
** PROJECT : IFX USB sub-system V3
|
||||
** MODULES : IFX USB sub-system Host and Device driver
|
||||
** SRC VERSION : 1.0
|
||||
** DATE : 1/Jan/2009
|
||||
** AUTHOR : Chen, Howard
|
||||
** DESCRIPTION : The Core Interface provides basic services for accessing and
|
||||
** managing the IFX USB hardware. These services are used by both the
|
||||
** Host Controller Driver and the Peripheral Controller Driver.
|
||||
** FUNCTIONS :
|
||||
** COMPILER : gcc
|
||||
** REFERENCE : IFX hardware ref handbook for each plateforms
|
||||
** COPYRIGHT :
|
||||
** Version Control Section **
|
||||
** $Author$
|
||||
** $Date$
|
||||
** $Revisions$
|
||||
** $Log$ Revision history
|
||||
*****************************************************************************/
|
||||
|
||||
/*!
|
||||
\defgroup IFXUSB_DRIVER_V3 IFX USB SS Project
|
||||
\brief IFX USB subsystem V3.x
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFXUSB_CIF Core Interface APIs
|
||||
\ingroup IFXUSB_DRIVER_V3
|
||||
\brief The Core Interface provides basic services for accessing and
|
||||
managing the IFXUSB hardware. These services are used by both the
|
||||
Host Controller Driver and the Peripheral Controller Driver.
|
||||
*/
|
||||
|
||||
|
||||
/*!
|
||||
\file ifxusb_cif.h
|
||||
\ingroup IFXUSB_DRIVER_V3
|
||||
\brief This file contains the interface to the IFX USB Core.
|
||||
*/
|
||||
|
||||
#if !defined(__IFXUSB_CIF_H__)
|
||||
#define __IFXUSB_CIF_H__
|
||||
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <asm/param.h>
|
||||
|
||||
#include "ifxusb_plat.h"
|
||||
#include "ifxusb_regs.h"
|
||||
|
||||
#ifdef __DEBUG__
|
||||
#include "linux/timer.h"
|
||||
#endif
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define IFXUSB_PARAM_SPEED_HIGH 0
|
||||
#define IFXUSB_PARAM_SPEED_FULL 1
|
||||
|
||||
#define IFXUSB_EP_SPEED_LOW 0
|
||||
#define IFXUSB_EP_SPEED_FULL 1
|
||||
#define IFXUSB_EP_SPEED_HIGH 2
|
||||
|
||||
#define IFXUSB_EP_TYPE_CTRL 0
|
||||
#define IFXUSB_EP_TYPE_ISOC 1
|
||||
#define IFXUSB_EP_TYPE_BULK 2
|
||||
#define IFXUSB_EP_TYPE_INTR 3
|
||||
|
||||
#define IFXUSB_HC_PID_DATA0 0
|
||||
#define IFXUSB_HC_PID_DATA2 1
|
||||
#define IFXUSB_HC_PID_DATA1 2
|
||||
#define IFXUSB_HC_PID_MDATA 3
|
||||
#define IFXUSB_HC_PID_SETUP 3
|
||||
|
||||
|
||||
/*!
|
||||
\addtogroup IFXUSB_CIF
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
\struct ifxusb_params
|
||||
\brief IFXUSB Parameters structure.
|
||||
This structure is used for both importing from insmod stage and run-time storage.
|
||||
These parameters define how the IFXUSB controller should be configured.
|
||||
*/
|
||||
typedef struct ifxusb_params
|
||||
{
|
||||
int32_t dma_burst_size; /*!< The DMA Burst size (applicable only for Internal DMA
|
||||
Mode). 0(for single), 1(incr), 4(incr4), 8(incr8) 16(incr16)
|
||||
*/
|
||||
/* Translate this to GAHBCFG values */
|
||||
int32_t speed; /*!< Specifies the maximum speed of operation in host and device mode.
|
||||
The actual speed depends on the speed of the attached device and
|
||||
the value of phy_type. The actual speed depends on the speed of the
|
||||
attached device.
|
||||
0 - High Speed (default)
|
||||
1 - Full Speed
|
||||
*/
|
||||
|
||||
int32_t data_fifo_size; /*!< Total number of dwords in the data FIFO memory. This
|
||||
memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
|
||||
Tx FIFOs.
|
||||
32 to 32768
|
||||
*/
|
||||
#ifdef __IS_DEVICE__
|
||||
int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in device mode.
|
||||
16 to 32768
|
||||
*/
|
||||
|
||||
|
||||
int32_t tx_fifo_size[MAX_EPS_CHANNELS]; /*!< Number of dwords in each of the Tx FIFOs in device mode.
|
||||
4 to 768
|
||||
*/
|
||||
#ifdef __DED_FIFO__
|
||||
int32_t thr_ctl; /*!< Threshold control on/off */
|
||||
int32_t tx_thr_length; /*!< Threshold length for Tx */
|
||||
int32_t rx_thr_length; /*!< Threshold length for Rx*/
|
||||
#endif
|
||||
#else //__IS_HOST__
|
||||
int32_t host_channels; /*!< The number of host channel registers to use.
|
||||
1 to 16
|
||||
*/
|
||||
|
||||
int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in host mode.
|
||||
16 to 32768
|
||||
*/
|
||||
|
||||
int32_t nperio_tx_fifo_size;/*!< Number of dwords in the non-periodic Tx FIFO in host mode.
|
||||
16 to 32768
|
||||
*/
|
||||
|
||||
int32_t perio_tx_fifo_size; /*!< Number of dwords in the host periodic Tx FIFO.
|
||||
16 to 32768
|
||||
*/
|
||||
#endif //__IS_HOST__
|
||||
|
||||
int32_t max_transfer_size; /*!< The maximum transfer size supported in bytes.
|
||||
2047 to 65,535
|
||||
*/
|
||||
|
||||
int32_t max_packet_count; /*!< The maximum number of packets in a transfer.
|
||||
15 to 511 (default 511)
|
||||
*/
|
||||
int32_t phy_utmi_width; /*!< Specifies the UTMI+ Data Width.
|
||||
8 or 16 bits (default 16)
|
||||
*/
|
||||
|
||||
int32_t turn_around_time_hs; /*!< Specifies the Turn-Around time at HS*/
|
||||
int32_t turn_around_time_fs; /*!< Specifies the Turn-Around time at FS*/
|
||||
|
||||
int32_t timeout_cal_hs; /*!< Specifies the Timeout_Calibration at HS*/
|
||||
int32_t timeout_cal_fs; /*!< Specifies the Timeout_Calibration at FS*/
|
||||
} ifxusb_params_t;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/*!
|
||||
\struct ifxusb_core_if
|
||||
\brief The ifx_core_if structure contains information needed to manage
|
||||
the IFX USB controller acting in either host or device mode. It
|
||||
represents the programming view of the controller as a whole.
|
||||
*/
|
||||
typedef struct ifxusb_core_if
|
||||
{
|
||||
ifxusb_params_t params; /*!< Run-time Parameters */
|
||||
|
||||
uint8_t core_no; /*!< core number (used as id when multi-core case */
|
||||
char *core_name; /*!< core name used for registration and informative purpose*/
|
||||
int irq; /*!< irq number this core is hooked */
|
||||
|
||||
/*****************************************************************
|
||||
* Structures and pointers to physical register interface.
|
||||
*****************************************************************/
|
||||
/** Core Global registers starting at offset 000h. */
|
||||
ifxusb_core_global_regs_t *core_global_regs; /*!< pointer to Core Global Registers, offset at 000h */
|
||||
|
||||
/** Host-specific registers */
|
||||
#ifdef __IS_HOST__
|
||||
/** Host Global Registers starting at offset 400h.*/
|
||||
ifxusb_host_global_regs_t *host_global_regs; /*!< pointer to Host Global Registers, offset at 400h */
|
||||
#define IFXUSB_HOST_GLOBAL_REG_OFFSET 0x400
|
||||
/** Host Port 0 Control and Status Register */
|
||||
volatile uint32_t *hprt0; /*!< pointer to HPRT0 Registers, offset at 440h */
|
||||
#define IFXUSB_HOST_PORT_REGS_OFFSET 0x440
|
||||
/** Host Channel Specific Registers at offsets 500h-5FCh. */
|
||||
ifxusb_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; /*!< pointer to Host-Channel n Registers, offset at 500h */
|
||||
#define IFXUSB_HOST_CHAN_REGS_OFFSET 0x500
|
||||
#define IFXUSB_CHAN_REGS_OFFSET 0x20
|
||||
#endif
|
||||
|
||||
/** Device-specific registers */
|
||||
#ifdef __IS_DEVICE__
|
||||
/** Device Global Registers starting at offset 800h */
|
||||
ifxusb_device_global_regs_t *dev_global_regs; /*!< pointer to Device Global Registers, offset at 800h */
|
||||
#define IFXUSB_DEV_GLOBAL_REG_OFFSET 0x800
|
||||
|
||||
/** Device Logical IN Endpoint-Specific Registers 900h-AFCh */
|
||||
ifxusb_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; /*!< pointer to Device IN-EP Registers, offset at 900h */
|
||||
#define IFXUSB_DEV_IN_EP_REG_OFFSET 0x900
|
||||
#define IFXUSB_EP_REG_OFFSET 0x20
|
||||
/** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
|
||||
ifxusb_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];/*!< pointer to Device OUT-EP Registers, offset at 900h */
|
||||
#define IFXUSB_DEV_OUT_EP_REG_OFFSET 0xB00
|
||||
#endif
|
||||
|
||||
/** Power and Clock Gating Control Register */
|
||||
volatile uint32_t *pcgcctl; /*!< pointer to Power and Clock Gating Control Registers, offset at E00h */
|
||||
#define IFXUSB_PCGCCTL_OFFSET 0xE00
|
||||
|
||||
/** Push/pop addresses for endpoints or host channels.*/
|
||||
uint32_t *data_fifo[MAX_EPS_CHANNELS]; /*!< pointer to FIFO access windows, offset at 1000h */
|
||||
#define IFXUSB_DATA_FIFO_OFFSET 0x1000
|
||||
#define IFXUSB_DATA_FIFO_SIZE 0x1000
|
||||
|
||||
uint32_t *data_fifo_dbg; /*!< pointer to FIFO debug windows, offset at 1000h */
|
||||
|
||||
/** Hardware Configuration -- stored here for convenience.*/
|
||||
hwcfg1_data_t hwcfg1; /*!< preserved Hardware Configuration 1 */
|
||||
hwcfg2_data_t hwcfg2; /*!< preserved Hardware Configuration 2 */
|
||||
hwcfg3_data_t hwcfg3; /*!< preserved Hardware Configuration 3 */
|
||||
hwcfg4_data_t hwcfg4; /*!< preserved Hardware Configuration 3 */
|
||||
uint32_t snpsid; /*!< preserved SNPSID */
|
||||
|
||||
/*****************************************************************
|
||||
* Run-time informations.
|
||||
*****************************************************************/
|
||||
/* Set to 1 if the core PHY interface bits in USBCFG have been initialized. */
|
||||
uint8_t phy_init_done; /*!< indicated PHY is initialized. */
|
||||
|
||||
#ifdef __IS_HOST__
|
||||
uint8_t queuing_high_bandwidth; /*!< Host mode, Queueing High Bandwidth. */
|
||||
#endif
|
||||
} ifxusb_core_if_t;
|
||||
|
||||
/*@}*//*IFXUSB_CIF*/
|
||||
|
||||
|
||||
/*!
|
||||
\fn void *ifxusb_alloc_buf(size_t size, int clear)
|
||||
\brief This function is called to allocate buffer of specified size.
|
||||
The allocated buffer is mapped into DMA accessable address.
|
||||
\param size Size in BYTE to be allocated
|
||||
\param clear 0: don't do clear after buffer allocated, other: do clear to zero
|
||||
\return 0/NULL: Fail; uncached pointer of allocated buffer
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void *ifxusb_alloc_buf(size_t size, int clear);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_free_buf(void *vaddr)
|
||||
\brief This function is called to free allocated buffer.
|
||||
\param vaddr the uncached pointer of the buffer
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_free_buf(void *vaddr);
|
||||
|
||||
/*!
|
||||
\fn int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
|
||||
int _irq,
|
||||
uint32_t _reg_base_addr,
|
||||
uint32_t _fifo_base_addr,
|
||||
uint32_t _fifo_dbg_addr)
|
||||
\brief This function is called to initialize the IFXUSB CSR data
|
||||
structures. The register addresses in the device and host
|
||||
structures are initialized from the base address supplied by the
|
||||
caller. The calling function must make the OS calls to get the
|
||||
base address of the IFXUSB controller registers.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\param _irq irq number
|
||||
\param _reg_base_addr Base address of IFXUSB core registers
|
||||
\param _fifo_base_addr Fifo base address
|
||||
\param _fifo_dbg_addr Fifo debug address
|
||||
\return 0: success;
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
|
||||
int _irq,
|
||||
uint32_t _reg_base_addr,
|
||||
uint32_t _fifo_base_addr,
|
||||
uint32_t _fifo_dbg_addr);
|
||||
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if)
|
||||
\brief This function free the mapped address in the IFXUSB CSR data structures.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if )
|
||||
\brief This function enbles the controller's Global Interrupt in the AHB Config register.
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
extern void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if );
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if )
|
||||
\brief This function disables the controller's Global Interrupt in the AHB Config register.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if );
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num )
|
||||
\brief Flush a Tx FIFO.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO )
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num );
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if )
|
||||
\brief Flush Rx FIFO.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if );
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if )
|
||||
\brief Flush ALL Rx and Tx FIFO.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if );
|
||||
|
||||
|
||||
/*!
|
||||
\fn int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if)
|
||||
\brief Do core a soft reset of the core. Be careful with this because it
|
||||
resets all the internal state machines of the core.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if);
|
||||
|
||||
|
||||
/*!
|
||||
\brief Turn on the USB Core Power
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_power_on (ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_power_off (ifxusb_core_if_t *_core_if)
|
||||
\brief Turn off the USB Core Power
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_power_off (ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if)
|
||||
\brief Turn on the USB PHY Power
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if)
|
||||
\brief Turn off the USB PHY Power
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_hard_reset(ifxusb_core_if_t *_core_if)
|
||||
\brief Reset on the USB Core RCU
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_hard_reset(ifxusb_core_if_t *_core_if);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifdef __IS_HOST__
|
||||
/*!
|
||||
\fn void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
|
||||
\brief This function initializes the IFXUSB controller registers for Host mode.
|
||||
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
|
||||
request queues.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\param _params parameters to be set
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if)
|
||||
\brief This function enables the Host mode interrupts.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if)
|
||||
\brief This function disables the Host mode interrupts.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if);
|
||||
|
||||
#if defined(__IS_TWINPASS__)
|
||||
extern void ifxusb_enable_afe_oc(void);
|
||||
#endif
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_vbus_init(ifxusb_core_if_t *_core_if)
|
||||
\brief This function init the VBUS control.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_vbus_init(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_vbus_free(ifxusb_core_if_t *_core_if)
|
||||
\brief This function free the VBUS control.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_vbus_free(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_vbus_on(ifxusb_core_if_t *_core_if)
|
||||
\brief Turn on the USB 5V VBus Power
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_vbus_on(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_vbus_off(ifxusb_core_if_t *_core_if)
|
||||
\brief Turn off the USB 5V VBus Power
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_vbus_off(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn int ifxusb_vbus(ifxusb_core_if_t *_core_if)
|
||||
\brief Read Current VBus status
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern int ifxusb_vbus(ifxusb_core_if_t *_core_if);
|
||||
|
||||
#if defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
|
||||
/*!
|
||||
\fn void ifxusb_oc_int_on(void)
|
||||
\brief Turn on the OC interrupt
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_oc_int_on(void);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_oc_int_off(void)
|
||||
\brief Turn off the OC interrupt
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_oc_int_off(void);
|
||||
#endif //defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
|
||||
#endif
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
/*!
|
||||
\fn void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if)
|
||||
\brief This function enables the Device mode interrupts.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if)
|
||||
\brief Gets the current USB frame number. This is the frame number from the last SOF packet.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in)
|
||||
\brief Set the EP STALL.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\param _epno EP number
|
||||
\param _is_in 1: is IN transfer
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in)
|
||||
\brief Set the EP STALL.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\param _epno EP number
|
||||
\param _ep_type EP Type
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
|
||||
\brief This function initializes the IFXUSB controller registers for Device mode.
|
||||
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
|
||||
request queues.
|
||||
This function validate the imported parameters and store the result in the CIF structure.
|
||||
After
|
||||
\param _core_if Pointer of core_if structure
|
||||
\param _params structure of inported parameters
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params);
|
||||
#endif
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#if defined(__GADGET_LED__) || defined(__HOST_LED__)
|
||||
/*!
|
||||
\fn void ifxusb_led_init(ifxusb_core_if_t *_core_if)
|
||||
\brief This function init the LED control.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_led_init(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_led_free(ifxusb_core_if_t *_core_if)
|
||||
\brief This function free the LED control.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_led_free(ifxusb_core_if_t *_core_if);
|
||||
|
||||
/*!
|
||||
\fn void ifxusb_led(ifxusb_core_if_t *_core_if)
|
||||
\brief This function trigger the LED access.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\ingroup IFXUSB_CIF
|
||||
*/
|
||||
extern void ifxusb_led(ifxusb_core_if_t *_core_if);
|
||||
#endif
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/* internal routines for debugging */
|
||||
extern void ifxusb_dump_msg(const u8 *buf, unsigned int length);
|
||||
extern void ifxusb_dump_spram(ifxusb_core_if_t *_core_if);
|
||||
extern void ifxusb_dump_registers(ifxusb_core_if_t *_core_if);
|
||||
extern void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
static inline uint32_t ifxusb_read_core_intr(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
return (ifxusb_rreg(&_core_if->core_global_regs->gintsts) &
|
||||
(ifxusb_rreg(&_core_if->core_global_regs->gintmsk)
|
||||
#ifdef __USE_TIMER_4_SOF__
|
||||
| IFXUSB_SOF_INTR_MASK
|
||||
#endif
|
||||
));
|
||||
}
|
||||
|
||||
static inline uint32_t ifxusb_read_otg_intr (ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
return (ifxusb_rreg (&_core_if->core_global_regs->gotgint));
|
||||
}
|
||||
|
||||
static inline uint32_t ifxusb_mode(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
return (ifxusb_rreg( &_core_if->core_global_regs->gintsts ) & 0x1);
|
||||
}
|
||||
static inline uint8_t ifxusb_is_device_mode(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
return (ifxusb_mode(_core_if) != 1);
|
||||
}
|
||||
static inline uint8_t ifxusb_is_host_mode(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
return (ifxusb_mode(_core_if) == 1);
|
||||
}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifdef __IS_HOST__
|
||||
static inline uint32_t ifxusb_read_hprt0(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
hprt0_data_t hprt0;
|
||||
hprt0.d32 = ifxusb_rreg(_core_if->hprt0);
|
||||
hprt0.b.prtena = 0;
|
||||
hprt0.b.prtconndet = 0;
|
||||
hprt0.b.prtenchng = 0;
|
||||
hprt0.b.prtovrcurrchng = 0;
|
||||
return hprt0.d32;
|
||||
}
|
||||
|
||||
static inline uint32_t ifxusb_read_host_all_channels_intr (ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
return (ifxusb_rreg (&_core_if->host_global_regs->haint));
|
||||
}
|
||||
|
||||
static inline uint32_t ifxusb_read_host_channel_intr (ifxusb_core_if_t *_core_if, int hc_num)
|
||||
{
|
||||
return (ifxusb_rreg (&_core_if->hc_regs[hc_num]->hcint));
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
static inline uint32_t ifxusb_read_dev_all_in_ep_intr(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
uint32_t v;
|
||||
v = ifxusb_rreg(&_core_if->dev_global_regs->daint) &
|
||||
ifxusb_rreg(&_core_if->dev_global_regs->daintmsk);
|
||||
return (v & 0xffff);
|
||||
}
|
||||
|
||||
static inline uint32_t ifxusb_read_dev_all_out_ep_intr(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
uint32_t v;
|
||||
v = ifxusb_rreg(&_core_if->dev_global_regs->daint) &
|
||||
ifxusb_rreg(&_core_if->dev_global_regs->daintmsk);
|
||||
return ((v & 0xffff0000) >> 16);
|
||||
}
|
||||
|
||||
static inline uint32_t ifxusb_read_dev_in_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num)
|
||||
{
|
||||
uint32_t v;
|
||||
v = ifxusb_rreg(&_core_if->in_ep_regs[_ep_num]->diepint) &
|
||||
ifxusb_rreg(&_core_if->dev_global_regs->diepmsk);
|
||||
return v;
|
||||
}
|
||||
|
||||
static inline uint32_t ifxusb_read_dev_out_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num)
|
||||
{
|
||||
uint32_t v;
|
||||
v = ifxusb_rreg(&_core_if->out_ep_regs[_ep_num]->doepint) &
|
||||
ifxusb_rreg(&_core_if->dev_global_regs->doepmsk);
|
||||
return v;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
extern void ifxusb_attr_create (void *_dev);
|
||||
|
||||
extern void ifxusb_attr_remove (void *_dev);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#endif // !defined(__IFXUSB_CIF_H__)
|
||||
|
||||
|
||||
458
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif_d.c
Normal file
458
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif_d.c
Normal file
@@ -0,0 +1,458 @@
|
||||
/*****************************************************************************
|
||||
** FILE NAME : ifxusb_cif_d.c
|
||||
** PROJECT : IFX USB sub-system V3
|
||||
** MODULES : IFX USB sub-system Host and Device driver
|
||||
** SRC VERSION : 1.0
|
||||
** DATE : 1/Jan/2009
|
||||
** AUTHOR : Chen, Howard
|
||||
** DESCRIPTION : The Core Interface provides basic services for accessing and
|
||||
** managing the IFX USB hardware. These services are used by the
|
||||
** Peripheral Controller Driver only.
|
||||
*****************************************************************************/
|
||||
|
||||
/*!
|
||||
\file ifxusb_cif_d.c
|
||||
\ingroup IFXUSB_DRIVER_V3
|
||||
\brief This file contains the interface to the IFX USB Core.
|
||||
*/
|
||||
|
||||
#include <linux/version.h>
|
||||
#include "ifxusb_version.h"
|
||||
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/unaligned.h>
|
||||
|
||||
#ifdef __DEBUG__
|
||||
#include <linux/jiffies.h>
|
||||
#endif
|
||||
|
||||
#include "ifxusb_plat.h"
|
||||
#include "ifxusb_regs.h"
|
||||
#include "ifxusb_cif.h"
|
||||
|
||||
#include "ifxpcd.h"
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\brief Initializes the DevSpd field of the DCFG register depending on the PHY type
|
||||
and the enumeration speed of the device.
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
void ifxusb_dev_init_spd(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
uint32_t val;
|
||||
dcfg_data_t dcfg;
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
if (_core_if->params.speed == IFXUSB_PARAM_SPEED_FULL)
|
||||
/* High speed PHY running at full speed */
|
||||
val = 0x1;
|
||||
else
|
||||
/* High speed PHY running at high speed and full speed*/
|
||||
val = 0x0;
|
||||
|
||||
IFX_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
|
||||
dcfg.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dcfg);
|
||||
dcfg.b.devspd = val;
|
||||
ifxusb_wreg(&_core_if->dev_global_regs->dcfg, dcfg.d32);
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief This function enables the Device mode interrupts.
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
gint_data_t intr_mask ={ .d32 = 0};
|
||||
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__);
|
||||
|
||||
/* Clear any pending OTG Interrupts */
|
||||
ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF);
|
||||
|
||||
/* Clear any pending interrupts */
|
||||
ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF);
|
||||
|
||||
/* Enable the interrupts in the GINTMSK.*/
|
||||
intr_mask.b.modemismatch = 1;
|
||||
intr_mask.b.conidstschng = 1;
|
||||
intr_mask.b.wkupintr = 1;
|
||||
intr_mask.b.disconnect = 1;
|
||||
intr_mask.b.usbsuspend = 1;
|
||||
|
||||
intr_mask.b.usbreset = 1;
|
||||
intr_mask.b.enumdone = 1;
|
||||
intr_mask.b.inepintr = 1;
|
||||
intr_mask.b.outepintr = 1;
|
||||
intr_mask.b.erlysuspend = 1;
|
||||
#ifndef __DED_FIFO__
|
||||
// intr_mask.b.epmismatch = 1;
|
||||
#endif
|
||||
|
||||
ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
|
||||
IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief Gets the current USB frame number. This is the frame number from the last SOF packet.
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
dsts_data_t dsts;
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
dsts.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dsts);
|
||||
/* read current frame/microfreme number from DSTS register */
|
||||
return dsts.b.soffn;
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief Set the EP STALL.
|
||||
*/
|
||||
void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in)
|
||||
{
|
||||
depctl_data_t depctl;
|
||||
volatile uint32_t *depctl_addr;
|
||||
|
||||
IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT"));
|
||||
|
||||
depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)):
|
||||
(&(_core_if->out_ep_regs[_epno]->doepctl));
|
||||
depctl.d32 = ifxusb_rreg(depctl_addr);
|
||||
depctl.b.stall = 1;
|
||||
|
||||
if (_is_in && depctl.b.epena)
|
||||
depctl.b.epdis = 1;
|
||||
|
||||
ifxusb_wreg(depctl_addr, depctl.d32);
|
||||
IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr));
|
||||
return;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief Clear the EP STALL.
|
||||
*/
|
||||
void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in)
|
||||
{
|
||||
depctl_data_t depctl;
|
||||
volatile uint32_t *depctl_addr;
|
||||
|
||||
IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT"));
|
||||
|
||||
depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)):
|
||||
(&(_core_if->out_ep_regs[_epno]->doepctl));
|
||||
|
||||
depctl.d32 = ifxusb_rreg(depctl_addr);
|
||||
/* clear the stall bits */
|
||||
depctl.b.stall = 0;
|
||||
|
||||
/*
|
||||
* USB Spec 9.4.5: For endpoints using data toggle, regardless
|
||||
* of whether an endpoint has the Halt feature set, a
|
||||
* ClearFeature(ENDPOINT_HALT) request always results in the
|
||||
* data toggle being reinitialized to DATA0.
|
||||
*/
|
||||
if (_ep_type == IFXUSB_EP_TYPE_INTR || _ep_type == IFXUSB_EP_TYPE_BULK)
|
||||
depctl.b.setd0pid = 1; /* DATA0 */
|
||||
|
||||
ifxusb_wreg(depctl_addr, depctl.d32);
|
||||
IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr));
|
||||
return;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief This function initializes the IFXUSB controller registers for Device mode.
|
||||
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
|
||||
request queues.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\param _params parameters to be set
|
||||
*/
|
||||
void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
|
||||
{
|
||||
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
||||
|
||||
gusbcfg_data_t usbcfg ={.d32 = 0};
|
||||
gahbcfg_data_t ahbcfg ={.d32 = 0};
|
||||
dcfg_data_t dcfg ={.d32 = 0};
|
||||
grstctl_t resetctl ={.d32 = 0};
|
||||
gotgctl_data_t gotgctl ={.d32 = 0};
|
||||
|
||||
uint32_t dir;
|
||||
int i;
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if);
|
||||
|
||||
/* Copy Params */
|
||||
_core_if->params.dma_burst_size = _params->dma_burst_size;
|
||||
_core_if->params.speed = _params->speed;
|
||||
if(_params->max_transfer_size < 2048 || _params->max_transfer_size > ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1) )
|
||||
_core_if->params.max_transfer_size = ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1);
|
||||
else
|
||||
_core_if->params.max_transfer_size = _params->max_transfer_size;
|
||||
|
||||
if(_params->max_packet_count < 16 || _params->max_packet_count > ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1) )
|
||||
_core_if->params.max_packet_count= ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
|
||||
else
|
||||
_core_if->params.max_packet_count= _params->max_packet_count;
|
||||
_core_if->params.phy_utmi_width = _params->phy_utmi_width;
|
||||
_core_if->params.turn_around_time_hs = _params->turn_around_time_hs;
|
||||
_core_if->params.turn_around_time_fs = _params->turn_around_time_fs;
|
||||
_core_if->params.timeout_cal_hs = _params->timeout_cal_hs;
|
||||
_core_if->params.timeout_cal_fs = _params->timeout_cal_fs;
|
||||
|
||||
#ifdef __DED_FIFO__
|
||||
_core_if->params.thr_ctl = _params->thr_ctl;
|
||||
_core_if->params.tx_thr_length = _params->tx_thr_length;
|
||||
_core_if->params.rx_thr_length = _params->rx_thr_length;
|
||||
#endif
|
||||
|
||||
/* Reset the Controller */
|
||||
do
|
||||
{
|
||||
while(ifxusb_core_soft_reset( _core_if ))
|
||||
ifxusb_hard_reset(_core_if);
|
||||
} while (ifxusb_is_host_mode(_core_if));
|
||||
|
||||
usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
|
||||
#if 0
|
||||
#if defined(__DED_FIFO__)
|
||||
usbcfg.b.ForceDevMode = 1;
|
||||
usbcfg.b.ForceHstMode = 0;
|
||||
#endif
|
||||
#endif
|
||||
usbcfg.b.term_sel_dl_pulse = 0;
|
||||
ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32);
|
||||
|
||||
/* This programming sequence needs to happen in FS mode before any other
|
||||
* programming occurs */
|
||||
/* High speed PHY. */
|
||||
if (!_core_if->phy_init_done)
|
||||
{
|
||||
_core_if->phy_init_done = 1;
|
||||
/* HS PHY parameters. These parameters are preserved
|
||||
* during soft reset so only program the first time. Do
|
||||
* a soft reset immediately after setting phyif. */
|
||||
usbcfg.b.ulpi_utmi_sel = 0; //UTMI+
|
||||
usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0;
|
||||
ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
|
||||
/* Reset after setting the PHY parameters */
|
||||
ifxusb_core_soft_reset( _core_if );
|
||||
}
|
||||
|
||||
/* Program the GAHBCFG Register.*/
|
||||
switch (_core_if->params.dma_burst_size)
|
||||
{
|
||||
case 0 :
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE;
|
||||
break;
|
||||
case 1 :
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR;
|
||||
break;
|
||||
case 4 :
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4;
|
||||
break;
|
||||
case 8 :
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8;
|
||||
break;
|
||||
case 16:
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16;
|
||||
break;
|
||||
}
|
||||
ahbcfg.b.dmaenable = 1;
|
||||
ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32);
|
||||
|
||||
/* Program the GUSBCFG register. */
|
||||
usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg );
|
||||
usbcfg.b.hnpcap = 0;
|
||||
usbcfg.b.srpcap = 0;
|
||||
ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
|
||||
|
||||
/* Restart the Phy Clock */
|
||||
ifxusb_wreg(_core_if->pcgcctl, 0);
|
||||
|
||||
/* Device configuration register */
|
||||
ifxusb_dev_init_spd(_core_if);
|
||||
dcfg.d32 = ifxusb_rreg( &_core_if->dev_global_regs->dcfg);
|
||||
dcfg.b.perfrint = IFXUSB_DCFG_FRAME_INTERVAL_80;
|
||||
#if defined(__DED_FIFO__)
|
||||
#if defined(__DESC_DMA__)
|
||||
dcfg.b.descdma = 1;
|
||||
#else
|
||||
dcfg.b.descdma = 0;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
ifxusb_wreg( &_core_if->dev_global_regs->dcfg, dcfg.d32 );
|
||||
|
||||
/* Configure data FIFO sizes */
|
||||
_core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
|
||||
_core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz);
|
||||
IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
|
||||
IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size);
|
||||
|
||||
_core_if->params.tx_fifo_size[0]= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16;
|
||||
|
||||
#ifdef __DED_FIFO__
|
||||
for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
|
||||
_core_if->params.tx_fifo_size[i] =
|
||||
ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]) >> 16;
|
||||
#else
|
||||
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
|
||||
_core_if->params.tx_fifo_size[i+1] =
|
||||
ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
|
||||
#endif
|
||||
|
||||
#ifdef __DEBUG__
|
||||
#ifdef __DED_FIFO__
|
||||
for (i=0; i <= _core_if->hwcfg4.b.num_in_eps; i++)
|
||||
IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i]);
|
||||
#else
|
||||
IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.tx_fifo_size[0]);
|
||||
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
|
||||
IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i+1]);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
{
|
||||
fifosize_data_t txfifosize;
|
||||
if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size)
|
||||
_core_if->params.data_fifo_size = _params->data_fifo_size;
|
||||
|
||||
|
||||
if(_params->rx_fifo_size >=0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size)
|
||||
_core_if->params.rx_fifo_size = _params->rx_fifo_size;
|
||||
if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size)
|
||||
_core_if->params.rx_fifo_size = _core_if->params.data_fifo_size;
|
||||
ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size);
|
||||
|
||||
for (i=0; i < MAX_EPS_CHANNELS; i++)
|
||||
if(_params->tx_fifo_size[i] >=0 && _params->tx_fifo_size[i] < _core_if->params.tx_fifo_size[i])
|
||||
_core_if->params.tx_fifo_size[i] = _params->tx_fifo_size[i];
|
||||
|
||||
txfifosize.b.startaddr = _core_if->params.rx_fifo_size;
|
||||
#ifdef __DED_FIFO__
|
||||
if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
|
||||
_core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
|
||||
txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
|
||||
ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
|
||||
txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
|
||||
for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
|
||||
{
|
||||
if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i] > _core_if->params.data_fifo_size)
|
||||
_core_if->params.tx_fifo_size[i]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
|
||||
txfifosize.b.depth=_core_if->params.tx_fifo_size[i];
|
||||
ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i-1], txfifosize.d32);
|
||||
txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i];
|
||||
}
|
||||
#else
|
||||
if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
|
||||
_core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
|
||||
txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
|
||||
ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
|
||||
txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
|
||||
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
|
||||
{
|
||||
if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i+1] > _core_if->params.data_fifo_size)
|
||||
_core_if->params.tx_fifo_size[i+1]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
|
||||
//txfifosize.b.depth=_core_if->params.tx_fifo_size[i+1];
|
||||
ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i], txfifosize.d32);
|
||||
txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i+1];
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __DEBUG__
|
||||
{
|
||||
fifosize_data_t fifosize;
|
||||
IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
|
||||
|
||||
IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X Sz=0x%06X\n", 0,ifxusb_rreg(&global_regs->grxfsiz));
|
||||
#ifdef __DED_FIFO__
|
||||
fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
|
||||
IFX_DEBUGPL(DBG_CIL, " Tx[00] FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
|
||||
for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
|
||||
{
|
||||
fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]);
|
||||
IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth);
|
||||
}
|
||||
#else
|
||||
fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
|
||||
IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
|
||||
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
|
||||
{
|
||||
fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]);
|
||||
IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clear Host Set HNP Enable in the OTG Control Register */
|
||||
gotgctl.b.hstsethnpen = 1;
|
||||
ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0);
|
||||
|
||||
/* Flush the FIFOs */
|
||||
ifxusb_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */
|
||||
ifxusb_flush_rx_fifo(_core_if);
|
||||
|
||||
/* Flush the Learning Queue. */
|
||||
resetctl.b.intknqflsh = 1;
|
||||
ifxusb_wreg( &global_regs->grstctl, resetctl.d32);
|
||||
|
||||
/* Clear all pending Device Interrupts */
|
||||
ifxusb_wreg( &_core_if->dev_global_regs->diepmsk , 0 );
|
||||
ifxusb_wreg( &_core_if->dev_global_regs->doepmsk , 0 );
|
||||
ifxusb_wreg( &_core_if->dev_global_regs->daint , 0xFFFFFFFF );
|
||||
ifxusb_wreg( &_core_if->dev_global_regs->daintmsk, 0 );
|
||||
|
||||
dir=_core_if->hwcfg1.d32;
|
||||
for (i=0; i <= _core_if->hwcfg2.b.num_dev_ep ; i++,dir>>=2)
|
||||
{
|
||||
depctl_data_t depctl;
|
||||
if((dir&0x03)==0 || (dir&0x03) ==1)
|
||||
{
|
||||
depctl.d32 = ifxusb_rreg(&_core_if->in_ep_regs[i]->diepctl);
|
||||
if (depctl.b.epena)
|
||||
{
|
||||
depctl.d32 = 0;
|
||||
depctl.b.epdis = 1;
|
||||
depctl.b.snak = 1;
|
||||
}
|
||||
else
|
||||
depctl.d32 = 0;
|
||||
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepctl, depctl.d32);
|
||||
#ifndef __DESC_DMA__
|
||||
ifxusb_wreg( &_core_if->in_ep_regs[i]->dieptsiz, 0);
|
||||
#endif
|
||||
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepdma, 0);
|
||||
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepint, 0xFF);
|
||||
}
|
||||
|
||||
if((dir&0x03)==0 || (dir&0x03) ==2)
|
||||
{
|
||||
depctl.d32 = ifxusb_rreg(&_core_if->out_ep_regs[i]->doepctl);
|
||||
if (depctl.b.epena)
|
||||
{
|
||||
depctl.d32 = 0;
|
||||
depctl.b.epdis = 1;
|
||||
depctl.b.snak = 1;
|
||||
}
|
||||
else
|
||||
depctl.d32 = 0;
|
||||
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepctl, depctl.d32);
|
||||
#ifndef __DESC_DMA__
|
||||
ifxusb_wreg( &_core_if->out_ep_regs[i]->doeptsiz, 0);
|
||||
#endif
|
||||
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepdma, 0);
|
||||
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepint, 0xFF);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
846
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif_h.c
Normal file
846
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_cif_h.c
Normal file
@@ -0,0 +1,846 @@
|
||||
/*****************************************************************************
|
||||
** FILE NAME : ifxusb_cif_h.c
|
||||
** PROJECT : IFX USB sub-system V3
|
||||
** MODULES : IFX USB sub-system Host and Device driver
|
||||
** SRC VERSION : 1.0
|
||||
** DATE : 1/Jan/2009
|
||||
** AUTHOR : Chen, Howard
|
||||
** DESCRIPTION : The Core Interface provides basic services for accessing and
|
||||
** managing the IFX USB hardware. These services are used by the
|
||||
** Host Controller Driver only.
|
||||
*****************************************************************************/
|
||||
|
||||
/*!
|
||||
\file ifxusb_cif_h.c
|
||||
\ingroup IFXUSB_DRIVER_V3
|
||||
\brief This file contains the interface to the IFX USB Core.
|
||||
*/
|
||||
#include <linux/version.h>
|
||||
#include "ifxusb_version.h"
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/unaligned.h>
|
||||
|
||||
#ifdef __DEBUG__
|
||||
#include <linux/jiffies.h>
|
||||
#endif
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#if defined(__UEIP__)
|
||||
// #include <asm/ifx/ifx_board.h>
|
||||
#endif
|
||||
|
||||
//#include <asm/ifx/ifx_gpio.h>
|
||||
#if defined(__UEIP__)
|
||||
// #include <asm/ifx/ifx_led.h>
|
||||
#endif
|
||||
|
||||
#include "ifxusb_plat.h"
|
||||
#include "ifxusb_regs.h"
|
||||
#include "ifxusb_cif.h"
|
||||
|
||||
#include "ifxhcd.h"
|
||||
|
||||
#if !defined(__UEIP__)
|
||||
#undef __USING_LED_AS_GPIO__
|
||||
#endif
|
||||
|
||||
|
||||
/*!
|
||||
\brief This function enables the Host mode interrupts.
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
gint_data_t intr_mask ={ .d32 = 0};
|
||||
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
||||
|
||||
IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__);
|
||||
|
||||
/* Clear any pending OTG Interrupts */
|
||||
ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF);
|
||||
|
||||
/* Clear any pending interrupts */
|
||||
ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF);
|
||||
|
||||
/* Enable the interrupts in the GINTMSK.*/
|
||||
|
||||
/* Common interrupts */
|
||||
intr_mask.b.modemismatch = 1;
|
||||
intr_mask.b.conidstschng = 1;
|
||||
intr_mask.b.wkupintr = 1;
|
||||
intr_mask.b.disconnect = 1;
|
||||
intr_mask.b.usbsuspend = 1;
|
||||
|
||||
/* Host interrupts */
|
||||
intr_mask.b.sofintr = 1;
|
||||
intr_mask.b.portintr = 1;
|
||||
intr_mask.b.hcintr = 1;
|
||||
|
||||
ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
|
||||
IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief This function disables the Host mode interrupts.
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
||||
|
||||
IFX_DEBUGPL(DBG_CILV, "%s()\n", __func__);
|
||||
|
||||
#if 1
|
||||
ifxusb_wreg( &global_regs->gintmsk, 0);
|
||||
#else
|
||||
/* Common interrupts */
|
||||
{
|
||||
gint_data_t intr_mask ={.d32 = 0};
|
||||
intr_mask.b.modemismatch = 1;
|
||||
intr_mask.b.rxstsqlvl = 1;
|
||||
intr_mask.b.conidstschng = 1;
|
||||
intr_mask.b.wkupintr = 1;
|
||||
intr_mask.b.disconnect = 1;
|
||||
intr_mask.b.usbsuspend = 1;
|
||||
|
||||
/* Host interrupts */
|
||||
intr_mask.b.sofintr = 1;
|
||||
intr_mask.b.portintr = 1;
|
||||
intr_mask.b.hcintr = 1;
|
||||
intr_mask.b.ptxfempty = 1;
|
||||
intr_mask.b.nptxfempty = 1;
|
||||
ifxusb_mreg(&global_regs->gintmsk, intr_mask.d32, 0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief This function initializes the IFXUSB controller registers for Host mode.
|
||||
This function flushes the Tx and Rx FIFOs and it flushes any entries in the
|
||||
request queues.
|
||||
\param _core_if Pointer of core_if structure
|
||||
\param _params parameters to be set
|
||||
*/
|
||||
void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
|
||||
{
|
||||
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
||||
|
||||
gusbcfg_data_t usbcfg ={.d32 = 0};
|
||||
gahbcfg_data_t ahbcfg ={.d32 = 0};
|
||||
gotgctl_data_t gotgctl ={.d32 = 0};
|
||||
|
||||
int i;
|
||||
|
||||
IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if);
|
||||
|
||||
/* Copy Params */
|
||||
|
||||
_core_if->params.dma_burst_size = _params->dma_burst_size;
|
||||
_core_if->params.speed = _params->speed;
|
||||
_core_if->params.max_transfer_size = _params->max_transfer_size;
|
||||
_core_if->params.max_packet_count = _params->max_packet_count;
|
||||
_core_if->params.phy_utmi_width = _params->phy_utmi_width;
|
||||
_core_if->params.turn_around_time_hs = _params->turn_around_time_hs;
|
||||
_core_if->params.turn_around_time_fs = _params->turn_around_time_fs;
|
||||
_core_if->params.timeout_cal_hs = _params->timeout_cal_hs;
|
||||
_core_if->params.timeout_cal_fs = _params->timeout_cal_fs;
|
||||
|
||||
/* Reset the Controller */
|
||||
do
|
||||
{
|
||||
while(ifxusb_core_soft_reset( _core_if ))
|
||||
ifxusb_hard_reset(_core_if);
|
||||
} while (ifxusb_is_device_mode(_core_if));
|
||||
|
||||
usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
|
||||
// usbcfg.b.ulpi_ext_vbus_drv = 1;
|
||||
usbcfg.b.term_sel_dl_pulse = 0;
|
||||
ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32);
|
||||
|
||||
/* This programming sequence needs to happen in FS mode before any other
|
||||
* programming occurs */
|
||||
/* High speed PHY. */
|
||||
if (!_core_if->phy_init_done)
|
||||
{
|
||||
_core_if->phy_init_done = 1;
|
||||
/* HS PHY parameters. These parameters are preserved
|
||||
* during soft reset so only program the first time. Do
|
||||
* a soft reset immediately after setting phyif. */
|
||||
usbcfg.b.ulpi_utmi_sel = 0; //UTMI+
|
||||
usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0;
|
||||
ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
|
||||
/* Reset after setting the PHY parameters */
|
||||
ifxusb_core_soft_reset( _core_if );
|
||||
}
|
||||
|
||||
usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
|
||||
// usbcfg.b.ulpi_fsls = 0;
|
||||
// usbcfg.b.ulpi_clk_sus_m = 0;
|
||||
ifxusb_wreg(&global_regs->gusbcfg, usbcfg.d32);
|
||||
|
||||
/* Program the GAHBCFG Register.*/
|
||||
switch (_core_if->params.dma_burst_size)
|
||||
{
|
||||
case 0 :
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE;
|
||||
break;
|
||||
case 1 :
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR;
|
||||
break;
|
||||
case 4 :
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4;
|
||||
break;
|
||||
case 8 :
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8;
|
||||
break;
|
||||
case 16:
|
||||
ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16;
|
||||
break;
|
||||
}
|
||||
ahbcfg.b.dmaenable = 1;
|
||||
ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32);
|
||||
|
||||
/* Program the GUSBCFG register. */
|
||||
usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg );
|
||||
usbcfg.b.hnpcap = 0;
|
||||
usbcfg.b.srpcap = 0;
|
||||
ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
|
||||
|
||||
/* Restart the Phy Clock */
|
||||
ifxusb_wreg(_core_if->pcgcctl, 0);
|
||||
|
||||
/* Initialize Host Configuration Register */
|
||||
{
|
||||
hcfg_data_t hcfg;
|
||||
hcfg.d32 = ifxusb_rreg(&_core_if->host_global_regs->hcfg);
|
||||
hcfg.b.fslspclksel = IFXUSB_HCFG_30_60_MHZ;
|
||||
if (_params->speed == IFXUSB_PARAM_SPEED_FULL)
|
||||
hcfg.b.fslssupp = 1;
|
||||
ifxusb_wreg(&_core_if->host_global_regs->hcfg, hcfg.d32);
|
||||
}
|
||||
|
||||
_core_if->params.host_channels=(_core_if->hwcfg2.b.num_host_chan + 1);
|
||||
|
||||
if(_params->host_channels>0 && _params->host_channels < _core_if->params.host_channels)
|
||||
_core_if->params.host_channels = _params->host_channels;
|
||||
|
||||
/* Configure data FIFO sizes */
|
||||
_core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
|
||||
_core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz);
|
||||
_core_if->params.nperio_tx_fifo_size= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16;
|
||||
_core_if->params.perio_tx_fifo_size = ifxusb_rreg(&global_regs->hptxfsiz) >> 16;
|
||||
IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
|
||||
IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size);
|
||||
IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.nperio_tx_fifo_size);
|
||||
IFX_DEBUGPL(DBG_CIL, " PTx FIFO Size=0x%06X\n", _core_if->params.perio_tx_fifo_size);
|
||||
|
||||
{
|
||||
fifosize_data_t txfifosize;
|
||||
if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size)
|
||||
_core_if->params.data_fifo_size = _params->data_fifo_size;
|
||||
|
||||
if( _params->rx_fifo_size >= 0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size)
|
||||
_core_if->params.rx_fifo_size = _params->rx_fifo_size;
|
||||
if( _params->nperio_tx_fifo_size >=0 && _params->nperio_tx_fifo_size < _core_if->params.nperio_tx_fifo_size)
|
||||
_core_if->params.nperio_tx_fifo_size = _params->nperio_tx_fifo_size;
|
||||
if( _params->perio_tx_fifo_size >=0 && _params->perio_tx_fifo_size < _core_if->params.perio_tx_fifo_size)
|
||||
_core_if->params.perio_tx_fifo_size = _params->perio_tx_fifo_size;
|
||||
|
||||
if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size)
|
||||
_core_if->params.rx_fifo_size = _core_if->params.data_fifo_size;
|
||||
ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size);
|
||||
txfifosize.b.startaddr = _core_if->params.rx_fifo_size;
|
||||
|
||||
if(txfifosize.b.startaddr + _core_if->params.nperio_tx_fifo_size > _core_if->params.data_fifo_size)
|
||||
_core_if->params.nperio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr;
|
||||
txfifosize.b.depth=_core_if->params.nperio_tx_fifo_size;
|
||||
ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
|
||||
txfifosize.b.startaddr += _core_if->params.nperio_tx_fifo_size;
|
||||
|
||||
if(txfifosize.b.startaddr + _core_if->params.perio_tx_fifo_size > _core_if->params.data_fifo_size)
|
||||
_core_if->params.perio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr;
|
||||
txfifosize.b.depth=_core_if->params.perio_tx_fifo_size;
|
||||
ifxusb_wreg( &global_regs->hptxfsiz, txfifosize.d32);
|
||||
txfifosize.b.startaddr += _core_if->params.perio_tx_fifo_size;
|
||||
}
|
||||
|
||||
#ifdef __DEBUG__
|
||||
{
|
||||
fifosize_data_t fifosize;
|
||||
IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
|
||||
|
||||
fifosize.d32=ifxusb_rreg(&global_regs->grxfsiz);
|
||||
IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
|
||||
fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
|
||||
IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
|
||||
fifosize.d32=ifxusb_rreg(&global_regs->hptxfsiz);
|
||||
IFX_DEBUGPL(DBG_CIL, " PTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clear Host Set HNP Enable in the OTG Control Register */
|
||||
gotgctl.b.hstsethnpen = 1;
|
||||
ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0);
|
||||
|
||||
/* Flush the FIFOs */
|
||||
ifxusb_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */
|
||||
ifxusb_flush_rx_fifo(_core_if);
|
||||
|
||||
for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++)
|
||||
{
|
||||
hcchar_data_t hcchar;
|
||||
hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
|
||||
hcchar.b.chen = 0;
|
||||
hcchar.b.chdis = 1;
|
||||
hcchar.b.epdir = 0;
|
||||
ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32);
|
||||
}
|
||||
/* Halt all channels to put them into a known state. */
|
||||
for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++)
|
||||
{
|
||||
hcchar_data_t hcchar;
|
||||
int count = 0;
|
||||
|
||||
hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
|
||||
hcchar.b.chen = 1;
|
||||
hcchar.b.chdis = 1;
|
||||
hcchar.b.epdir = 0;
|
||||
ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32);
|
||||
|
||||
IFX_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
|
||||
do{
|
||||
hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar);
|
||||
if (++count > 1000)
|
||||
{
|
||||
IFX_ERROR("%s: Unable to clear halt on channel %d\n", __func__, i);
|
||||
break;
|
||||
}
|
||||
} while (hcchar.b.chen);
|
||||
}
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#if defined(__UEIP__)
|
||||
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
|
||||
int ifxusb_vbus_status =-1;
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
|
||||
int ifxusb_vbus1_status =-1;
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
|
||||
int ifxusb_vbus2_status =-1;
|
||||
#endif
|
||||
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
|
||||
static void *g_usb_vbus_trigger = NULL;
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
|
||||
static void *g_usb_vbus1_trigger = NULL;
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
|
||||
static void *g_usb_vbus2_trigger = NULL;
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
int ifxusb_vbus_gpio_inited=0;
|
||||
#endif
|
||||
|
||||
#else //defined(__UEIP__)
|
||||
int ifxusb_vbus_gpio_inited=0;
|
||||
#endif
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void ifxusb_vbus_init(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
#if defined(__UEIP__)
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
|
||||
if ( !g_usb_vbus_trigger )
|
||||
{
|
||||
ifx_led_trigger_register("USB_VBUS", &g_usb_vbus_trigger);
|
||||
if ( g_usb_vbus_trigger != NULL )
|
||||
{
|
||||
struct ifx_led_trigger_attrib attrib = {0};
|
||||
attrib.delay_on = 0;
|
||||
attrib.delay_off = 0;
|
||||
attrib.timeout = 0;
|
||||
attrib.def_value = 0;
|
||||
attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
|
||||
IFX_DEBUGP("Reg USB power!!\n");
|
||||
ifx_led_trigger_set_attrib(g_usb_vbus_trigger, &attrib);
|
||||
ifxusb_vbus_status =0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
|
||||
if(_core_if->core_no==0 && !g_usb_vbus1_trigger )
|
||||
{
|
||||
ifx_led_trigger_register("USB_VBUS1", &g_usb_vbus1_trigger);
|
||||
if ( g_usb_vbus1_trigger != NULL )
|
||||
{
|
||||
struct ifx_led_trigger_attrib attrib = {0};
|
||||
attrib.delay_on = 0;
|
||||
attrib.delay_off = 0;
|
||||
attrib.timeout = 0;
|
||||
attrib.def_value = 0;
|
||||
attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
|
||||
IFX_DEBUGP("Reg USB1 power!!\n");
|
||||
ifx_led_trigger_set_attrib(g_usb_vbus1_trigger, &attrib);
|
||||
ifxusb_vbus1_status =0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
|
||||
if(_core_if->core_no==1 && !g_usb_vbus2_trigger )
|
||||
{
|
||||
ifx_led_trigger_register("USB_VBUS2", &g_usb_vbus2_trigger);
|
||||
if ( g_usb_vbus2_trigger != NULL )
|
||||
{
|
||||
struct ifx_led_trigger_attrib attrib = {0};
|
||||
attrib.delay_on = 0;
|
||||
attrib.delay_off = 0;
|
||||
attrib.timeout = 0;
|
||||
attrib.def_value = 0;
|
||||
attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
|
||||
IFX_DEBUGP("Reg USB2 power!!\n");
|
||||
ifx_led_trigger_set_attrib(g_usb_vbus2_trigger, &attrib);
|
||||
ifxusb_vbus2_status =0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
/* == 20100712 AVM/WK use gpio_inited as bitmask == */
|
||||
if(ifxusb_vbus_gpio_inited == 0)
|
||||
{
|
||||
if(!ifx_gpio_register(IFX_GPIO_MODULE_USB))
|
||||
{
|
||||
IFX_DEBUGP("Register USB VBus through GPIO OK!!\n");
|
||||
#ifdef IFX_GPIO_USB_VBUS
|
||||
ifxusb_vbus_status =0;
|
||||
#endif //IFX_GPIO_USB_VBUS
|
||||
#ifdef IFX_GPIO_USB_VBUS1
|
||||
ifxusb_vbus1_status=0;
|
||||
#endif //IFX_GPIO_USB_VBUS1
|
||||
#ifdef IFX_GPIO_USB_VBUS2
|
||||
ifxusb_vbus2_status=0;
|
||||
#endif //IFX_GPIO_USB_VBUS2
|
||||
ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no);
|
||||
}
|
||||
else
|
||||
IFX_PRINT("Register USB VBus Failed!!\n");
|
||||
} else {
|
||||
ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no);
|
||||
}
|
||||
#endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
#endif //defined(__UEIP__)
|
||||
}
|
||||
|
||||
void ifxusb_vbus_free(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
#if defined(__UEIP__)
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
|
||||
if ( g_usb_vbus_trigger )
|
||||
{
|
||||
ifx_led_trigger_deregister(g_usb_vbus_trigger);
|
||||
g_usb_vbus_trigger = NULL;
|
||||
ifxusb_vbus_status =-1;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
|
||||
if(_core_if->core_no==0 && g_usb_vbus1_trigger )
|
||||
{
|
||||
ifx_led_trigger_deregister(g_usb_vbus1_trigger);
|
||||
g_usb_vbus1_trigger = NULL;
|
||||
ifxusb_vbus1_status =-1;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
|
||||
if(_core_if->core_no==1 && g_usb_vbus2_trigger )
|
||||
{
|
||||
ifx_led_trigger_deregister(g_usb_vbus2_trigger);
|
||||
g_usb_vbus2_trigger = NULL;
|
||||
ifxusb_vbus2_status =-1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
/* == 20100712 AVM/WK use gpio_inited as bitmask == */
|
||||
if((ifxusb_vbus_gpio_inited & (1<<_core_if->core_no)) == ifxusb_vbus_gpio_inited)
|
||||
{
|
||||
ifx_gpio_deregister(IFX_GPIO_MODULE_USB);
|
||||
#ifdef IFX_GPIO_USB_VBUS
|
||||
ifxusb_vbus_status =-1;
|
||||
#endif //IFX_GPIO_USB_VBUS
|
||||
#ifdef IFX_GPIO_USB_VBUS1
|
||||
ifxusb_vbus1_status=-1;
|
||||
#endif //IFX_GPIO_USB_VBUS1
|
||||
#ifdef IFX_GPIO_USB_VBUS2
|
||||
ifxusb_vbus2_status=-1;
|
||||
#endif //IFX_GPIO_USB_VBUS2
|
||||
}
|
||||
ifxusb_vbus_gpio_inited &= ~(1<<_core_if->core_no);
|
||||
#endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
#endif //defined(__UEIP__)
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief Turn on the USB 5V VBus Power
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
void ifxusb_vbus_on(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
IFX_DEBUGP("SENDING VBus POWER UP\n");
|
||||
#if defined(__UEIP__)
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
|
||||
if ( g_usb_vbus_trigger && ifxusb_vbus_status==0)
|
||||
{
|
||||
ifx_led_trigger_activate(g_usb_vbus_trigger);
|
||||
IFX_DEBUGP("Enable USB power!!\n");
|
||||
ifxusb_vbus_status=1;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
|
||||
if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==0)
|
||||
{
|
||||
ifx_led_trigger_activate(g_usb_vbus1_trigger);
|
||||
IFX_DEBUGP("Enable USB1 power!!\n");
|
||||
ifxusb_vbus1_status=1;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
|
||||
if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==0)
|
||||
{
|
||||
ifx_led_trigger_activate(g_usb_vbus2_trigger);
|
||||
IFX_DEBUGP("Enable USB2 power!!\n");
|
||||
ifxusb_vbus2_status=1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
if(ifxusb_vbus_gpio_inited)
|
||||
{
|
||||
#if defined(IFX_GPIO_USB_VBUS)
|
||||
if(ifxusb_vbus_status==0)
|
||||
{
|
||||
ifx_gpio_output_set(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB);
|
||||
ifxusb_vbus_status=1;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_GPIO_USB_VBUS1)
|
||||
if(_core_if->core_no==0 && ifxusb_vbus1_status==0)
|
||||
{
|
||||
ifx_gpio_output_set(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB);
|
||||
ifxusb_vbus1_status=1;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_GPIO_USB_VBUS2)
|
||||
if(_core_if->core_no==1 && ifxusb_vbus2_status==0)
|
||||
{
|
||||
ifx_gpio_output_set(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB);
|
||||
ifxusb_vbus2_status=1;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
#else
|
||||
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
||||
ifxusb_vbus_status=1;
|
||||
//usb_set_vbus_on();
|
||||
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
||||
#if defined(__IS_AMAZON_SE__)
|
||||
set_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT);
|
||||
ifxusb_vbus_status=1;
|
||||
#endif //defined(__IS_AMAZON_SE__)
|
||||
#if defined(__IS_AR9__)
|
||||
if(_core_if->core_no==0)
|
||||
{
|
||||
if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0)
|
||||
{
|
||||
IFX_PRINT("Can't enable USB1 5.5V power!!\n");
|
||||
return;
|
||||
}
|
||||
bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_set_dir_out(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_set_pudsel(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_set_puden(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_set_output(1, 13, PORT_MODULE_USB);
|
||||
IFX_DEBUGP("Enable USB1 power!!\n");
|
||||
ifxusb_vbus1_status=1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0)
|
||||
{
|
||||
IFX_PRINT("Can't enable USB2 5.5V power!!\n");
|
||||
return;
|
||||
}
|
||||
bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_set_dir_out(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_set_pudsel(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_set_puden(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_set_output(3, 4, PORT_MODULE_USB);
|
||||
IFX_DEBUGP("Enable USB2 power!!\n");
|
||||
ifxusb_vbus2_status=1;
|
||||
}
|
||||
#endif //defined(__IS_AR9__)
|
||||
#if defined(__IS_VR9__)
|
||||
if(_core_if->core_no==0)
|
||||
{
|
||||
ifxusb_vbus1_status=1;
|
||||
}
|
||||
else
|
||||
{
|
||||
ifxusb_vbus2_status=1;
|
||||
}
|
||||
#endif //defined(__IS_VR9__)
|
||||
#endif //defined(__UEIP__)
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief Turn off the USB 5V VBus Power
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
void ifxusb_vbus_off(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
IFX_DEBUGP("SENDING VBus POWER OFF\n");
|
||||
|
||||
#if defined(__UEIP__)
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
|
||||
if ( g_usb_vbus_trigger && ifxusb_vbus_status==1)
|
||||
{
|
||||
ifx_led_trigger_deactivate(g_usb_vbus_trigger);
|
||||
IFX_DEBUGP("Disable USB power!!\n");
|
||||
ifxusb_vbus_status=0;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
|
||||
if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==1)
|
||||
{
|
||||
ifx_led_trigger_deactivate(g_usb_vbus1_trigger);
|
||||
IFX_DEBUGP("Disable USB1 power!!\n");
|
||||
ifxusb_vbus1_status=0;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
|
||||
if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==1)
|
||||
{
|
||||
ifx_led_trigger_deactivate(g_usb_vbus2_trigger);
|
||||
IFX_DEBUGP("Disable USB2 power!!\n");
|
||||
ifxusb_vbus2_status=0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
if(ifxusb_vbus_gpio_inited)
|
||||
{
|
||||
#if defined(IFX_GPIO_USB_VBUS)
|
||||
if(ifxusb_vbus_status==1)
|
||||
{
|
||||
ifx_gpio_output_clear(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB);
|
||||
ifxusb_vbus_status=0;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_GPIO_USB_VBUS1)
|
||||
if(_core_if->core_no==0 && ifxusb_vbus1_status==1)
|
||||
{
|
||||
ifx_gpio_output_clear(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB);
|
||||
ifxusb_vbus1_status=0;
|
||||
}
|
||||
#endif
|
||||
#if defined(IFX_GPIO_USB_VBUS2)
|
||||
if(_core_if->core_no==1 && ifxusb_vbus2_status==1)
|
||||
{
|
||||
ifx_gpio_output_clear(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB);
|
||||
ifxusb_vbus2_status=0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2)
|
||||
#else
|
||||
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
||||
ifxusb_vbus_status=0;
|
||||
//usb_set_vbus_on();
|
||||
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
||||
#if defined(__IS_AMAZON_SE__)
|
||||
clear_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT);
|
||||
ifxusb_vbus_status=0;
|
||||
#endif //defined(__IS_AMAZON_SE__)
|
||||
#if defined(__IS_AR9__)
|
||||
if(_core_if->core_no==0)
|
||||
{
|
||||
if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) {
|
||||
IFX_PRINT("Can't Disable USB1 5.5V power!!\n");
|
||||
return;
|
||||
}
|
||||
bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_set_dir_out(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_set_pudsel(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_set_puden(1, 13, PORT_MODULE_USB);
|
||||
bsp_port_clear_output(1, 13, PORT_MODULE_USB);
|
||||
IFX_DEBUGP("Disable USB1 power!!\n");
|
||||
ifxusb_vbus1_status=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) {
|
||||
IFX_PRINT("Can't Disable USB2 5.5V power!!\n");
|
||||
return;
|
||||
}
|
||||
bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_set_dir_out(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_set_pudsel(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_set_puden(3, 4, PORT_MODULE_USB);
|
||||
bsp_port_clear_output(3, 4, PORT_MODULE_USB);
|
||||
IFX_DEBUGP("Disable USB2 power!!\n");
|
||||
|
||||
ifxusb_vbus2_status=0;
|
||||
}
|
||||
#endif //defined(__IS_AR9__)
|
||||
#if defined(__IS_VR9__)
|
||||
if(_core_if->core_no==0)
|
||||
{
|
||||
ifxusb_vbus1_status=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ifxusb_vbus2_status=0;
|
||||
}
|
||||
#endif //defined(__IS_VR9__)
|
||||
#endif //defined(__UEIP__)
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\brief Read Current VBus status
|
||||
\param _core_if Pointer of core_if structure
|
||||
*/
|
||||
int ifxusb_vbus(ifxusb_core_if_t *_core_if)
|
||||
{
|
||||
#if defined(__UEIP__)
|
||||
#if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS)
|
||||
return (ifxusb_vbus_status);
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1)
|
||||
if(_core_if->core_no==0)
|
||||
return (ifxusb_vbus1_status);
|
||||
#endif
|
||||
|
||||
#if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2)
|
||||
if(_core_if->core_no==1)
|
||||
return (ifxusb_vbus2_status);
|
||||
#endif
|
||||
#else //defined(__UEIP__)
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if defined(__UEIP__)
|
||||
#else
|
||||
#if defined(__IS_TWINPASS__)
|
||||
#define ADSL_BASE 0x20000
|
||||
#define CRI_BASE 0x31F00
|
||||
#define CRI_CCR0 CRI_BASE + 0x00
|
||||
#define CRI_CCR1 CRI_BASE + 0x01*4
|
||||
#define CRI_CDC0 CRI_BASE + 0x02*4
|
||||
#define CRI_CDC1 CRI_BASE + 0x03*4
|
||||
#define CRI_RST CRI_BASE + 0x04*4
|
||||
#define CRI_MASK0 CRI_BASE + 0x05*4
|
||||
#define CRI_MASK1 CRI_BASE + 0x06*4
|
||||
#define CRI_MASK2 CRI_BASE + 0x07*4
|
||||
#define CRI_STATUS0 CRI_BASE + 0x08*4
|
||||
#define CRI_STATUS1 CRI_BASE + 0x09*4
|
||||
#define CRI_STATUS2 CRI_BASE + 0x0A*4
|
||||
#define CRI_AMASK0 CRI_BASE + 0x0B*4
|
||||
#define CRI_AMASK1 CRI_BASE + 0x0C*4
|
||||
#define CRI_UPDCTL CRI_BASE + 0x0D*4
|
||||
#define CRI_MADST CRI_BASE + 0x0E*4
|
||||
// 0x0f is missing
|
||||
#define CRI_EVENT0 CRI_BASE + 0x10*4
|
||||
#define CRI_EVENT1 CRI_BASE + 0x11*4
|
||||
#define CRI_EVENT2 CRI_BASE + 0x12*4
|
||||
|
||||
#define IRI_I_ENABLE 0x32000
|
||||
#define STY_SMODE 0x3c004
|
||||
#define AFE_TCR_0 0x3c0dc
|
||||
#define AFE_ADDR_ADDR 0x3c0e8
|
||||
#define AFE_RDATA_ADDR 0x3c0ec
|
||||
#define AFE_WDATA_ADDR 0x3c0f0
|
||||
#define AFE_CONFIG 0x3c0f4
|
||||
#define AFE_SERIAL_CFG 0x3c0fc
|
||||
|
||||
#define DFE_BASE_ADDR 0xBE116000
|
||||
//#define DFE_BASE_ADDR 0x9E116000
|
||||
|
||||
#define MEI_FR_ARCINT_C (DFE_BASE_ADDR + 0x0000001C)
|
||||
#define MEI_DBG_WADDR_C (DFE_BASE_ADDR + 0x00000024)
|
||||
#define MEI_DBG_RADDR_C (DFE_BASE_ADDR + 0x00000028)
|
||||
#define MEI_DBG_DATA_C (DFE_BASE_ADDR + 0x0000002C)
|
||||
#define MEI_DBG_DECO_C (DFE_BASE_ADDR + 0x00000030)
|
||||
#define MEI_DBG_MASTER_C (DFE_BASE_ADDR + 0x0000003C)
|
||||
|
||||
static void WriteARCmem(uint32_t addr, uint32_t data)
|
||||
{
|
||||
writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
|
||||
writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C );
|
||||
writel(addr ,(volatile uint32_t *)MEI_DBG_WADDR_C );
|
||||
writel(data ,(volatile uint32_t *)MEI_DBG_DATA_C );
|
||||
while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){};
|
||||
writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
|
||||
IFX_DEBUGP("WriteARCmem %08x %08x\n",addr,data);
|
||||
};
|
||||
|
||||
static uint32_t ReadARCmem(uint32_t addr)
|
||||
{
|
||||
u32 data;
|
||||
writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
|
||||
writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C );
|
||||
writel(addr ,(volatile uint32_t *)MEI_DBG_RADDR_C );
|
||||
while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){};
|
||||
data = ifxusb_rreg((volatile uint32_t *)MEI_DBG_DATA_C );
|
||||
writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
|
||||
IFX_DEBUGP("ReadARCmem %08x %08x\n",addr,data);
|
||||
return data;
|
||||
};
|
||||
|
||||
void ifxusb_enable_afe_oc(void)
|
||||
{
|
||||
/* Start the clock */
|
||||
WriteARCmem(CRI_UPDCTL ,0x00000008);
|
||||
WriteARCmem(CRI_CCR0 ,0x00000014);
|
||||
WriteARCmem(CRI_CCR1 ,0x00000500);
|
||||
WriteARCmem(AFE_CONFIG ,0x000001c8);
|
||||
WriteARCmem(AFE_SERIAL_CFG,0x00000016); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge
|
||||
WriteARCmem(AFE_TCR_0 ,0x00000002);
|
||||
//Take afe out of reset
|
||||
WriteARCmem(AFE_CONFIG ,0x000000c0);
|
||||
WriteARCmem(IRI_I_ENABLE ,0x00000101);
|
||||
WriteARCmem(STY_SMODE ,0x00001980);
|
||||
|
||||
ReadARCmem(CRI_UPDCTL );
|
||||
ReadARCmem(CRI_CCR0 );
|
||||
ReadARCmem(CRI_CCR1 );
|
||||
ReadARCmem(AFE_CONFIG );
|
||||
ReadARCmem(AFE_SERIAL_CFG); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge
|
||||
ReadARCmem(AFE_TCR_0 );
|
||||
ReadARCmem(AFE_CONFIG );
|
||||
ReadARCmem(IRI_I_ENABLE );
|
||||
ReadARCmem(STY_SMODE );
|
||||
}
|
||||
#endif //defined(__IS_TWINPASS__)
|
||||
#endif //defined(__UEIP__)
|
||||
|
||||
|
||||
1385
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_ctl.c
Normal file
1385
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_ctl.c
Normal file
File diff suppressed because it is too large
Load Diff
970
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_driver.c
Normal file
970
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_driver.c
Normal file
@@ -0,0 +1,970 @@
|
||||
/*****************************************************************************
|
||||
** FILE NAME : ifxusb_driver.c
|
||||
** PROJECT : IFX USB sub-system V3
|
||||
** MODULES : IFX USB sub-system Host and Device driver
|
||||
** SRC VERSION : 1.0
|
||||
** DATE : 1/Jan/2009
|
||||
** AUTHOR : Chen, Howard
|
||||
** DESCRIPTION : The provides the initialization and cleanup entry
|
||||
** points for the IFX USB driver. This module can be
|
||||
** dynamically loaded with insmod command or built-in
|
||||
** with kernel. When loaded or executed the ifxusb_driver_init
|
||||
** function is called. When the module is removed (using rmmod),
|
||||
** the ifxusb_driver_cleanup function is called.
|
||||
*****************************************************************************/
|
||||
|
||||
/*!
|
||||
\file ifxusb_driver.c
|
||||
\brief This file contains the loading/unloading interface to the Linux driver.
|
||||
*/
|
||||
|
||||
#include <linux/version.h>
|
||||
#include "ifxusb_version.h"
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/stat.h> /* permission constants */
|
||||
#include <linux/gpio.h>
|
||||
#include <lantiq_soc.h>
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
|
||||
#include <linux/irq.h>
|
||||
#endif
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
|
||||
#include <asm/irq.h>
|
||||
#endif
|
||||
|
||||
#include "ifxusb_plat.h"
|
||||
|
||||
#include "ifxusb_cif.h"
|
||||
|
||||
#ifdef __IS_HOST__
|
||||
#include "ifxhcd.h"
|
||||
|
||||
#define USB_DRIVER_DESC "IFX USB HCD driver"
|
||||
const char ifxusb_driver_name[] = "ifxusb_hcd";
|
||||
|
||||
#ifdef __IS_DUAL__
|
||||
ifxhcd_hcd_t ifxusb_hcd_1;
|
||||
ifxhcd_hcd_t ifxusb_hcd_2;
|
||||
const char ifxusb_hcd_name_1[] = "ifxusb_hcd_1";
|
||||
const char ifxusb_hcd_name_2[] = "ifxusb_hcd_2";
|
||||
#else
|
||||
ifxhcd_hcd_t ifxusb_hcd;
|
||||
const char ifxusb_hcd_name[] = "ifxusb_hcd";
|
||||
#endif
|
||||
|
||||
#if defined(__DO_OC_INT__)
|
||||
static unsigned int oc_int_installed=0;
|
||||
static ifxhcd_hcd_t *oc_int_id=NULL;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
#include "ifxpcd.h"
|
||||
|
||||
#define USB_DRIVER_DESC "IFX USB PCD driver"
|
||||
const char ifxusb_driver_name[] = "ifxusb_pcd";
|
||||
|
||||
ifxpcd_pcd_t ifxusb_pcd;
|
||||
const char ifxusb_pcd_name[] = "ifxusb_pcd";
|
||||
#endif
|
||||
|
||||
/* Global Debug Level Mask. */
|
||||
#ifdef __IS_HOST__
|
||||
uint32_t h_dbg_lvl = 0x00;
|
||||
#endif
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
uint32_t d_dbg_lvl = 0x00;
|
||||
#endif
|
||||
|
||||
ifxusb_params_t ifxusb_module_params;
|
||||
|
||||
static void parse_parms(void);
|
||||
|
||||
|
||||
#include <lantiq_irq.h>
|
||||
#define IFX_USB0_IR (INT_NUM_IM1_IRL0 + 22)
|
||||
#define IFX_USB1_IR (INT_NUM_IM2_IRL0 + 19)
|
||||
|
||||
/*!
|
||||
\brief This function is called when a driver is unregistered. This happens when
|
||||
the rmmod command is executed. The device may or may not be electrically
|
||||
present. If it is present, the driver stops device processing. Any resources
|
||||
used on behalf of this device are freed.
|
||||
*/
|
||||
static int ifxusb_driver_remove(struct platform_device *_dev)
|
||||
{
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
#ifdef __IS_HOST__
|
||||
#if defined(__DO_OC_INT__)
|
||||
#if defined(__DO_OC_INT_ENABLE__)
|
||||
ifxusb_oc_int_off();
|
||||
#endif
|
||||
|
||||
if(oc_int_installed && oc_int_id)
|
||||
free_irq((unsigned int)IFXUSB_OC_IRQ, oc_int_id );
|
||||
oc_int_installed=0;
|
||||
oc_int_id=NULL;
|
||||
#endif
|
||||
|
||||
#if defined(__IS_DUAL__)
|
||||
ifxhcd_remove(&ifxusb_hcd_1);
|
||||
ifxusb_core_if_remove(&ifxusb_hcd_1.core_if );
|
||||
ifxhcd_remove(&ifxusb_hcd_2);
|
||||
ifxusb_core_if_remove(&ifxusb_hcd_2.core_if );
|
||||
#else
|
||||
ifxhcd_remove(&ifxusb_hcd);
|
||||
ifxusb_core_if_remove(&ifxusb_hcd.core_if );
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
ifxpcd_remove();
|
||||
ifxusb_core_if_remove(&ifxusb_pcd.core_if );
|
||||
#endif
|
||||
|
||||
/* Remove the device attributes */
|
||||
|
||||
ifxusb_attr_remove(&_dev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* Function to setup the structures to control one usb core running as host*/
|
||||
#ifdef __IS_HOST__
|
||||
/*!
|
||||
\brief inlined by ifxusb_driver_probe(), handling host mode probing. Run at each host core.
|
||||
*/
|
||||
static inline int ifxusb_driver_probe_h(ifxhcd_hcd_t *_hcd,
|
||||
int _irq,
|
||||
uint32_t _iobase,
|
||||
uint32_t _fifomem,
|
||||
uint32_t _fifodbg
|
||||
)
|
||||
{
|
||||
int retval = 0;
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
|
||||
#ifdef __DEV_NEW__
|
||||
ifxusb_power_off (&_hcd->core_if);
|
||||
ifxusb_phy_power_off (&_hcd->core_if); // Test
|
||||
mdelay(500);
|
||||
#endif //__DEV_NEW__
|
||||
ifxusb_power_on (&_hcd->core_if);
|
||||
mdelay(50);
|
||||
ifxusb_phy_power_on (&_hcd->core_if); // Test
|
||||
mdelay(50);
|
||||
ifxusb_hard_reset(&_hcd->core_if);
|
||||
retval =ifxusb_core_if_init(&_hcd->core_if,
|
||||
_irq,
|
||||
_iobase,
|
||||
_fifomem,
|
||||
_fifodbg);
|
||||
if(retval)
|
||||
return retval;
|
||||
|
||||
ifxusb_host_core_init(&_hcd->core_if,&ifxusb_module_params);
|
||||
|
||||
ifxusb_disable_global_interrupts( &_hcd->core_if);
|
||||
|
||||
/* The driver is now initialized and need to be registered into Linux USB sub-system */
|
||||
|
||||
retval = ifxhcd_init(_hcd); // hook the hcd into usb ss
|
||||
|
||||
if (retval != 0)
|
||||
{
|
||||
IFX_ERROR("_hcd_init failed\n");
|
||||
return retval;
|
||||
}
|
||||
|
||||
//ifxusb_enable_global_interrupts( _hcd->core_if ); // this should be done at hcd_start , including hcd_interrupt
|
||||
return 0;
|
||||
}
|
||||
#endif //__IS_HOST__
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
/*!
|
||||
\brief inlined by ifxusb_driver_probe(), handling device mode probing.
|
||||
*/
|
||||
static inline int ifxusb_driver_probe_d(ifxpcd_pcd_t *_pcd,
|
||||
int _irq,
|
||||
uint32_t _iobase,
|
||||
uint32_t _fifomem,
|
||||
uint32_t _fifodbg
|
||||
)
|
||||
{
|
||||
int retval = 0;
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
#ifdef __DEV_NEW__
|
||||
ifxusb_power_off (&_pcd->core_if);
|
||||
ifxusb_phy_power_off (&_pcd->core_if); // Test
|
||||
mdelay(500);
|
||||
#endif // __DEV_NEW__
|
||||
ifxusb_power_on (&_pcd->core_if);
|
||||
mdelay(50);
|
||||
ifxusb_phy_power_on (&_pcd->core_if); // Test
|
||||
mdelay(50);
|
||||
ifxusb_hard_reset(&_pcd->core_if);
|
||||
retval =ifxusb_core_if_init(&_pcd->core_if,
|
||||
_irq,
|
||||
_iobase,
|
||||
_fifomem,
|
||||
_fifodbg);
|
||||
if(retval)
|
||||
return retval;
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
ifxusb_dev_core_init(&_pcd->core_if,&ifxusb_module_params);
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
ifxusb_disable_global_interrupts( &_pcd->core_if);
|
||||
|
||||
/* The driver is now initialized and need to be registered into
|
||||
Linux USB Gadget sub-system
|
||||
*/
|
||||
retval = ifxpcd_init();
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
|
||||
if (retval != 0)
|
||||
{
|
||||
IFX_ERROR("_pcd_init failed\n");
|
||||
return retval;
|
||||
}
|
||||
//ifxusb_enable_global_interrupts( _pcd->core_if ); // this should be done at gadget bind or start
|
||||
return 0;
|
||||
}
|
||||
#endif //__IS_DEVICE__
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\brief This function is called by module management in 2.6 kernel or by ifxusb_driver_init with 2.4 kernel
|
||||
It is to probe and setup IFXUSB core(s).
|
||||
*/
|
||||
static int ifxusb_driver_probe(struct platform_device *_dev)
|
||||
{
|
||||
int retval = 0;
|
||||
int *pins = _dev->dev.platform_data;
|
||||
if (ltq_is_vr9()) {
|
||||
gpio_request(6, "id1");
|
||||
gpio_request(9, "id2");
|
||||
gpio_direction_input(6);
|
||||
gpio_direction_input(9);
|
||||
}
|
||||
if (pins) {
|
||||
if (pins[0]) {
|
||||
gpio_request(pins[0], "vbus1");
|
||||
gpio_direction_output(pins[0], 1);
|
||||
}
|
||||
if (pins[1] && ltq_is_vr9()) {
|
||||
gpio_request(pins[1], "vbus2");
|
||||
gpio_direction_output(pins[1], 1);
|
||||
}
|
||||
}
|
||||
// Parsing and store the parameters
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
parse_parms();
|
||||
|
||||
#ifdef __IS_HOST__
|
||||
#if defined(__IS_DUAL__)
|
||||
memset(&ifxusb_hcd_1, 0, sizeof(ifxhcd_hcd_t));
|
||||
memset(&ifxusb_hcd_2, 0, sizeof(ifxhcd_hcd_t));
|
||||
|
||||
ifxusb_hcd_1.core_if.core_no=0;
|
||||
ifxusb_hcd_2.core_if.core_no=1;
|
||||
ifxusb_hcd_1.core_if.core_name=(char *)ifxusb_hcd_name_1;
|
||||
ifxusb_hcd_2.core_if.core_name=(char *)ifxusb_hcd_name_2;
|
||||
|
||||
ifxusb_hcd_1.dev=&_dev->dev;
|
||||
ifxusb_hcd_2.dev=&_dev->dev;
|
||||
|
||||
retval = ifxusb_driver_probe_h(&ifxusb_hcd_1,
|
||||
IFX_USB0_IR,
|
||||
IFXUSB1_IOMEM_BASE,
|
||||
IFXUSB1_FIFOMEM_BASE,
|
||||
IFXUSB1_FIFODBG_BASE
|
||||
);
|
||||
if(retval)
|
||||
goto ifxusb_driver_probe_fail;
|
||||
|
||||
retval = ifxusb_driver_probe_h(&ifxusb_hcd_2,
|
||||
IFX_USB1_IR,
|
||||
IFXUSB2_IOMEM_BASE,
|
||||
IFXUSB2_FIFOMEM_BASE,
|
||||
IFXUSB2_FIFODBG_BASE
|
||||
);
|
||||
if(retval)
|
||||
goto ifxusb_driver_probe_fail;
|
||||
|
||||
#elif defined(__IS_FIRST__)
|
||||
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
|
||||
|
||||
ifxusb_hcd.core_if.core_no=0;
|
||||
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
|
||||
|
||||
ifxusb_hcd.dev=&_dev->dev;
|
||||
|
||||
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
|
||||
IFX_USB0_IR,
|
||||
IFXUSB1_IOMEM_BASE,
|
||||
IFXUSB1_FIFOMEM_BASE,
|
||||
IFXUSB1_FIFODBG_BASE
|
||||
);
|
||||
if(retval)
|
||||
goto ifxusb_driver_probe_fail;
|
||||
|
||||
#elif defined(__IS_SECOND__)
|
||||
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
|
||||
|
||||
ifxusb_hcd.core_if.core_no=1;
|
||||
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
|
||||
|
||||
ifxusb_hcd.dev=&_dev->dev;
|
||||
|
||||
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
|
||||
IFX_USB1_IR,
|
||||
IFXUSB2_IOMEM_BASE,
|
||||
IFXUSB2_FIFOMEM_BASE,
|
||||
IFXUSB2_FIFODBG_BASE
|
||||
);
|
||||
if(retval)
|
||||
goto ifxusb_driver_probe_fail;
|
||||
|
||||
#else
|
||||
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
|
||||
|
||||
ifxusb_hcd.core_if.core_no=0;
|
||||
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
|
||||
|
||||
ifxusb_hcd.dev=&_dev->dev;
|
||||
|
||||
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
|
||||
IFXUSB_IRQ,
|
||||
IFXUSB_IOMEM_BASE,
|
||||
IFXUSB_FIFOMEM_BASE,
|
||||
IFXUSB_FIFODBG_BASE
|
||||
);
|
||||
if(retval)
|
||||
goto ifxusb_driver_probe_fail;
|
||||
#endif
|
||||
|
||||
#if defined(__DO_OC_INT__)
|
||||
IFXUSB_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for irq%d\n", IFXUSB_OC_IRQ);
|
||||
#if defined(__IS_DUAL__)
|
||||
request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq,
|
||||
// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd_1);
|
||||
IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd_1);
|
||||
oc_int_id=&ifxusb_hcd_1;
|
||||
#else
|
||||
request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq,
|
||||
// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd);
|
||||
IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd);
|
||||
oc_int_id=&ifxusb_hcd;
|
||||
#endif
|
||||
oc_int_installed=1;
|
||||
|
||||
#if defined(__DO_OC_INT_ENABLE__)
|
||||
ifxusb_oc_int_on();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
memset(&ifxusb_pcd, 0, sizeof(ifxpcd_pcd_t));
|
||||
ifxusb_pcd.core_if.core_name=(char *)&ifxusb_pcd_name[0];
|
||||
|
||||
ifxusb_pcd.dev=&_dev->dev;
|
||||
|
||||
#if defined(__IS_FIRST__)
|
||||
ifxusb_pcd.core_if.core_no=0;
|
||||
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
|
||||
IFXUSB1_IRQ,
|
||||
IFXUSB1_IOMEM_BASE,
|
||||
IFXUSB1_FIFOMEM_BASE,
|
||||
IFXUSB1_FIFODBG_BASE
|
||||
);
|
||||
#elif defined(__IS_SECOND__)
|
||||
ifxusb_pcd.core_if.core_no=1;
|
||||
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
|
||||
IFXUSB2_IRQ,
|
||||
IFXUSB2_IOMEM_BASE,
|
||||
IFXUSB2_FIFOMEM_BASE,
|
||||
IFXUSB2_FIFODBG_BASE
|
||||
);
|
||||
#else
|
||||
ifxusb_pcd.core_if.core_no=0;
|
||||
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
|
||||
IFXUSB_IRQ,
|
||||
IFXUSB_IOMEM_BASE,
|
||||
IFXUSB_FIFOMEM_BASE,
|
||||
IFXUSB_FIFODBG_BASE
|
||||
);
|
||||
#endif
|
||||
if(retval)
|
||||
goto ifxusb_driver_probe_fail;
|
||||
#endif
|
||||
|
||||
ifxusb_attr_create(&_dev->dev);
|
||||
|
||||
return 0;
|
||||
|
||||
ifxusb_driver_probe_fail:
|
||||
ifxusb_driver_remove(_dev);
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\brief This function is called when the ifxusb_driver is installed with the insmod command.
|
||||
*/
|
||||
|
||||
|
||||
static struct platform_driver ifxusb_driver = {
|
||||
.driver = {
|
||||
.name = ifxusb_driver_name,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = ifxusb_driver_probe,
|
||||
.remove = ifxusb_driver_remove,
|
||||
};
|
||||
|
||||
int __init ifxusb_driver_init(void)
|
||||
{
|
||||
int retval = 0;
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION);
|
||||
|
||||
retval = platform_driver_register(&ifxusb_driver);
|
||||
|
||||
if (retval < 0) {
|
||||
IFX_ERROR("%s retval=%d\n", __func__, retval);
|
||||
return retval;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
#if 0 // 2.4
|
||||
int __init ifxusb_driver_init(void)
|
||||
{
|
||||
int retval = 0;
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION);
|
||||
retval = ifxusb_driver_probe();
|
||||
|
||||
if (retval < 0) {
|
||||
IFX_ERROR("%s retval=%d\n", __func__, retval);
|
||||
return retval;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
#endif
|
||||
|
||||
module_init(ifxusb_driver_init);
|
||||
|
||||
|
||||
/*!
|
||||
\brief This function is called when the driver is removed from the kernel
|
||||
with the rmmod command. The driver unregisters itself with its bus
|
||||
driver.
|
||||
*/
|
||||
|
||||
void __exit ifxusb_driver_cleanup(void)
|
||||
{
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
|
||||
platform_driver_unregister(&ifxusb_driver);
|
||||
|
||||
IFX_PRINT("%s module removed\n", ifxusb_driver_name);
|
||||
}
|
||||
#if 0
|
||||
void __exit ifxusb_driver_cleanup(void)
|
||||
{
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
ifxusb_driver_remove();
|
||||
IFX_PRINT("%s module removed\n", ifxusb_driver_name);
|
||||
}
|
||||
#endif
|
||||
module_exit(ifxusb_driver_cleanup);
|
||||
|
||||
|
||||
|
||||
MODULE_DESCRIPTION(USB_DRIVER_DESC);
|
||||
MODULE_AUTHOR("Infineon");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
|
||||
|
||||
// Parameters set when loaded
|
||||
//static long dbg_lvl =0xFFFFFFFF;
|
||||
static long dbg_lvl =0;
|
||||
static short dma_burst_size =-1;
|
||||
static short speed =-1;
|
||||
static long data_fifo_size =-1;
|
||||
#ifdef __IS_DEVICE__
|
||||
static long rx_fifo_size =-1;
|
||||
#ifdef __DED_FIFO__
|
||||
static long tx_fifo_size_00 =-1;
|
||||
static long tx_fifo_size_01 =-1;
|
||||
static long tx_fifo_size_02 =-1;
|
||||
static long tx_fifo_size_03 =-1;
|
||||
static long tx_fifo_size_04 =-1;
|
||||
static long tx_fifo_size_05 =-1;
|
||||
static long tx_fifo_size_06 =-1;
|
||||
static long tx_fifo_size_07 =-1;
|
||||
static long tx_fifo_size_08 =-1;
|
||||
static long tx_fifo_size_09 =-1;
|
||||
static long tx_fifo_size_10 =-1;
|
||||
static long tx_fifo_size_11 =-1;
|
||||
static long tx_fifo_size_12 =-1;
|
||||
static long tx_fifo_size_13 =-1;
|
||||
static long tx_fifo_size_14 =-1;
|
||||
static long tx_fifo_size_15 =-1;
|
||||
static short thr_ctl=-1;
|
||||
static long tx_thr_length =-1;
|
||||
static long rx_thr_length =-1;
|
||||
#else
|
||||
static long nperio_tx_fifo_size =-1;
|
||||
static long perio_tx_fifo_size_01 =-1;
|
||||
static long perio_tx_fifo_size_02 =-1;
|
||||
static long perio_tx_fifo_size_03 =-1;
|
||||
static long perio_tx_fifo_size_04 =-1;
|
||||
static long perio_tx_fifo_size_05 =-1;
|
||||
static long perio_tx_fifo_size_06 =-1;
|
||||
static long perio_tx_fifo_size_07 =-1;
|
||||
static long perio_tx_fifo_size_08 =-1;
|
||||
static long perio_tx_fifo_size_09 =-1;
|
||||
static long perio_tx_fifo_size_10 =-1;
|
||||
static long perio_tx_fifo_size_11 =-1;
|
||||
static long perio_tx_fifo_size_12 =-1;
|
||||
static long perio_tx_fifo_size_13 =-1;
|
||||
static long perio_tx_fifo_size_14 =-1;
|
||||
static long perio_tx_fifo_size_15 =-1;
|
||||
#endif
|
||||
static short dev_endpoints =-1;
|
||||
#endif
|
||||
|
||||
#ifdef __IS_HOST__
|
||||
static long rx_fifo_size =-1;
|
||||
static long nperio_tx_fifo_size =-1;
|
||||
static long perio_tx_fifo_size =-1;
|
||||
static short host_channels =-1;
|
||||
#endif
|
||||
|
||||
static long max_transfer_size =-1;
|
||||
static long max_packet_count =-1;
|
||||
static long phy_utmi_width =-1;
|
||||
static long turn_around_time_hs =-1;
|
||||
static long turn_around_time_fs =-1;
|
||||
static long timeout_cal_hs =-1;
|
||||
static long timeout_cal_fs =-1;
|
||||
|
||||
/*!
|
||||
\brief Parsing the parameters taken when module load
|
||||
*/
|
||||
static void parse_parms(void)
|
||||
{
|
||||
|
||||
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
||||
#ifdef __IS_HOST__
|
||||
h_dbg_lvl=dbg_lvl;
|
||||
#endif
|
||||
#ifdef __IS_DEVICE__
|
||||
d_dbg_lvl=dbg_lvl;
|
||||
#endif
|
||||
|
||||
switch(dma_burst_size)
|
||||
{
|
||||
case 0:
|
||||
case 1:
|
||||
case 4:
|
||||
case 8:
|
||||
case 16:
|
||||
ifxusb_module_params.dma_burst_size=dma_burst_size;
|
||||
break;
|
||||
default:
|
||||
ifxusb_module_params.dma_burst_size=default_param_dma_burst_size;
|
||||
}
|
||||
|
||||
if(speed==0 || speed==1)
|
||||
ifxusb_module_params.speed=speed;
|
||||
else
|
||||
ifxusb_module_params.speed=default_param_speed;
|
||||
|
||||
if(max_transfer_size>=2048 && max_transfer_size<=65535)
|
||||
ifxusb_module_params.max_transfer_size=max_transfer_size;
|
||||
else
|
||||
ifxusb_module_params.max_transfer_size=default_param_max_transfer_size;
|
||||
|
||||
if(max_packet_count>=15 && max_packet_count<=511)
|
||||
ifxusb_module_params.max_packet_count=max_packet_count;
|
||||
else
|
||||
ifxusb_module_params.max_packet_count=default_param_max_packet_count;
|
||||
|
||||
switch(phy_utmi_width)
|
||||
{
|
||||
case 8:
|
||||
case 16:
|
||||
ifxusb_module_params.phy_utmi_width=phy_utmi_width;
|
||||
break;
|
||||
default:
|
||||
ifxusb_module_params.phy_utmi_width=default_param_phy_utmi_width;
|
||||
}
|
||||
|
||||
if(turn_around_time_hs>=0 && turn_around_time_hs<=7)
|
||||
ifxusb_module_params.turn_around_time_hs=turn_around_time_hs;
|
||||
else
|
||||
ifxusb_module_params.turn_around_time_hs=default_param_turn_around_time_hs;
|
||||
|
||||
if(turn_around_time_fs>=0 && turn_around_time_fs<=7)
|
||||
ifxusb_module_params.turn_around_time_fs=turn_around_time_fs;
|
||||
else
|
||||
ifxusb_module_params.turn_around_time_fs=default_param_turn_around_time_fs;
|
||||
|
||||
if(timeout_cal_hs>=0 && timeout_cal_hs<=7)
|
||||
ifxusb_module_params.timeout_cal_hs=timeout_cal_hs;
|
||||
else
|
||||
ifxusb_module_params.timeout_cal_hs=default_param_timeout_cal_hs;
|
||||
|
||||
if(timeout_cal_fs>=0 && timeout_cal_fs<=7)
|
||||
ifxusb_module_params.timeout_cal_fs=timeout_cal_fs;
|
||||
else
|
||||
ifxusb_module_params.timeout_cal_fs=default_param_timeout_cal_fs;
|
||||
|
||||
if(data_fifo_size>=32 && data_fifo_size<=32768)
|
||||
ifxusb_module_params.data_fifo_size=data_fifo_size;
|
||||
else
|
||||
ifxusb_module_params.data_fifo_size=default_param_data_fifo_size;
|
||||
|
||||
#ifdef __IS_HOST__
|
||||
if(host_channels>=1 && host_channels<=16)
|
||||
ifxusb_module_params.host_channels=host_channels;
|
||||
else
|
||||
ifxusb_module_params.host_channels=default_param_host_channels;
|
||||
|
||||
if(rx_fifo_size>=16 && rx_fifo_size<=32768)
|
||||
ifxusb_module_params.rx_fifo_size=rx_fifo_size;
|
||||
else
|
||||
ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size;
|
||||
|
||||
if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768)
|
||||
ifxusb_module_params.nperio_tx_fifo_size=nperio_tx_fifo_size;
|
||||
else
|
||||
ifxusb_module_params.nperio_tx_fifo_size=default_param_nperio_tx_fifo_size;
|
||||
|
||||
if(perio_tx_fifo_size>=16 && perio_tx_fifo_size<=32768)
|
||||
ifxusb_module_params.perio_tx_fifo_size=perio_tx_fifo_size;
|
||||
else
|
||||
ifxusb_module_params.perio_tx_fifo_size=default_param_perio_tx_fifo_size;
|
||||
#endif //__IS_HOST__
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
if(rx_fifo_size>=16 && rx_fifo_size<=32768)
|
||||
ifxusb_module_params.rx_fifo_size=rx_fifo_size;
|
||||
else
|
||||
ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size;
|
||||
#ifdef __DED_FIFO__
|
||||
if(tx_fifo_size_00>=16 && tx_fifo_size_00<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 0]=tx_fifo_size_00;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 0]=default_param_tx_fifo_size_00;
|
||||
if(tx_fifo_size_01>=0 && tx_fifo_size_01<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 1]=tx_fifo_size_01;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 1]=default_param_tx_fifo_size_01;
|
||||
if(tx_fifo_size_02>=0 && tx_fifo_size_02<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 2]=tx_fifo_size_02;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 2]=default_param_tx_fifo_size_02;
|
||||
if(tx_fifo_size_03>=0 && tx_fifo_size_03<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 3]=tx_fifo_size_03;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 3]=default_param_tx_fifo_size_03;
|
||||
if(tx_fifo_size_04>=0 && tx_fifo_size_04<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 4]=tx_fifo_size_04;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 4]=default_param_tx_fifo_size_04;
|
||||
if(tx_fifo_size_05>=0 && tx_fifo_size_05<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 5]=tx_fifo_size_05;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 5]=default_param_tx_fifo_size_05;
|
||||
if(tx_fifo_size_06>=0 && tx_fifo_size_06<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 6]=tx_fifo_size_06;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 6]=default_param_tx_fifo_size_06;
|
||||
if(tx_fifo_size_07>=0 && tx_fifo_size_07<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 7]=tx_fifo_size_07;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 7]=default_param_tx_fifo_size_07;
|
||||
if(tx_fifo_size_08>=0 && tx_fifo_size_08<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 8]=tx_fifo_size_08;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 8]=default_param_tx_fifo_size_08;
|
||||
if(tx_fifo_size_09>=0 && tx_fifo_size_09<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 9]=tx_fifo_size_09;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 9]=default_param_tx_fifo_size_09;
|
||||
if(tx_fifo_size_10>=0 && tx_fifo_size_10<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[10]=tx_fifo_size_10;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[10]=default_param_tx_fifo_size_10;
|
||||
if(tx_fifo_size_11>=0 && tx_fifo_size_11<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[11]=tx_fifo_size_11;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[11]=default_param_tx_fifo_size_11;
|
||||
if(tx_fifo_size_12>=0 && tx_fifo_size_12<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[12]=tx_fifo_size_12;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[12]=default_param_tx_fifo_size_12;
|
||||
if(tx_fifo_size_13>=0 && tx_fifo_size_13<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[13]=tx_fifo_size_13;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[13]=default_param_tx_fifo_size_13;
|
||||
if(tx_fifo_size_14>=0 && tx_fifo_size_14<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[14]=tx_fifo_size_14;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[14]=default_param_tx_fifo_size_14;
|
||||
if(tx_fifo_size_15>=0 && tx_fifo_size_15<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[15]=tx_fifo_size_15;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[15]=default_param_tx_fifo_size_15;
|
||||
if(thr_ctl==0 || thr_ctl==1)
|
||||
ifxusb_module_params.thr_ctl=thr_ctl;
|
||||
else
|
||||
ifxusb_module_params.thr_ctl=default_param_thr_ctl;
|
||||
if(tx_thr_length>=16 && tx_thr_length<=511)
|
||||
ifxusb_module_params.tx_thr_length=tx_thr_length;
|
||||
else
|
||||
ifxusb_module_params.tx_thr_length=default_param_tx_thr_length;
|
||||
if(rx_thr_length>=16 && rx_thr_length<=511)
|
||||
ifxusb_module_params.rx_thr_length=rx_thr_length;
|
||||
else
|
||||
ifxusb_module_params.rx_thr_length=default_param_rx_thr_length;
|
||||
#else //__DED_FIFO__
|
||||
if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 0]=nperio_tx_fifo_size;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 0]=default_param_nperio_tx_fifo_size;
|
||||
if(perio_tx_fifo_size_01>=0 && perio_tx_fifo_size_01<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 1]=perio_tx_fifo_size_01;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 1]=default_param_perio_tx_fifo_size_01;
|
||||
if(perio_tx_fifo_size_02>=0 && perio_tx_fifo_size_02<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 2]=perio_tx_fifo_size_02;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 2]=default_param_perio_tx_fifo_size_02;
|
||||
if(perio_tx_fifo_size_03>=0 && perio_tx_fifo_size_03<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 3]=perio_tx_fifo_size_03;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 3]=default_param_perio_tx_fifo_size_03;
|
||||
if(perio_tx_fifo_size_04>=0 && perio_tx_fifo_size_04<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 4]=perio_tx_fifo_size_04;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 4]=default_param_perio_tx_fifo_size_04;
|
||||
if(perio_tx_fifo_size_05>=0 && perio_tx_fifo_size_05<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 5]=perio_tx_fifo_size_05;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 5]=default_param_perio_tx_fifo_size_05;
|
||||
if(perio_tx_fifo_size_06>=0 && perio_tx_fifo_size_06<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 6]=perio_tx_fifo_size_06;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 6]=default_param_perio_tx_fifo_size_06;
|
||||
if(perio_tx_fifo_size_07>=0 && perio_tx_fifo_size_07<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 7]=perio_tx_fifo_size_07;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 7]=default_param_perio_tx_fifo_size_07;
|
||||
if(perio_tx_fifo_size_08>=0 && perio_tx_fifo_size_08<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 8]=perio_tx_fifo_size_08;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 8]=default_param_perio_tx_fifo_size_08;
|
||||
if(perio_tx_fifo_size_09>=0 && perio_tx_fifo_size_09<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[ 9]=perio_tx_fifo_size_09;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[ 9]=default_param_perio_tx_fifo_size_09;
|
||||
if(perio_tx_fifo_size_10>=0 && perio_tx_fifo_size_10<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[10]=perio_tx_fifo_size_10;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[10]=default_param_perio_tx_fifo_size_10;
|
||||
if(perio_tx_fifo_size_11>=0 && perio_tx_fifo_size_11<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[11]=perio_tx_fifo_size_11;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[11]=default_param_perio_tx_fifo_size_11;
|
||||
if(perio_tx_fifo_size_12>=0 && perio_tx_fifo_size_12<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[12]=perio_tx_fifo_size_12;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[12]=default_param_perio_tx_fifo_size_12;
|
||||
if(perio_tx_fifo_size_13>=0 && perio_tx_fifo_size_13<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[13]=perio_tx_fifo_size_13;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[13]=default_param_perio_tx_fifo_size_13;
|
||||
if(perio_tx_fifo_size_14>=0 && perio_tx_fifo_size_14<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[14]=perio_tx_fifo_size_14;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[14]=default_param_perio_tx_fifo_size_14;
|
||||
if(perio_tx_fifo_size_15>=0 && perio_tx_fifo_size_15<=32768)
|
||||
ifxusb_module_params.tx_fifo_size[15]=perio_tx_fifo_size_15;
|
||||
else
|
||||
ifxusb_module_params.tx_fifo_size[15]=default_param_perio_tx_fifo_size_15;
|
||||
#endif //__DED_FIFO__
|
||||
#endif //__IS_DEVICE__
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
module_param(dbg_lvl, long, 0444);
|
||||
MODULE_PARM_DESC(dbg_lvl, "Debug level.");
|
||||
|
||||
module_param(dma_burst_size, short, 0444);
|
||||
MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 0, 1, 4, 8, 16");
|
||||
|
||||
module_param(speed, short, 0444);
|
||||
MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
|
||||
|
||||
module_param(data_fifo_size, long, 0444);
|
||||
MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
|
||||
|
||||
#ifdef __IS_DEVICE__
|
||||
module_param(rx_fifo_size, long, 0444);
|
||||
MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
|
||||
|
||||
#ifdef __DED_FIFO__
|
||||
module_param(tx_fifo_size_00, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_00, "Number of words in the Tx FIFO #00 16-32768");
|
||||
module_param(tx_fifo_size_01, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_01, "Number of words in the Tx FIFO #01 0-32768");
|
||||
module_param(tx_fifo_size_02, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_02, "Number of words in the Tx FIFO #02 0-32768");
|
||||
module_param(tx_fifo_size_03, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_03, "Number of words in the Tx FIFO #03 0-32768");
|
||||
module_param(tx_fifo_size_04, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_04, "Number of words in the Tx FIFO #04 0-32768");
|
||||
module_param(tx_fifo_size_05, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_05, "Number of words in the Tx FIFO #05 0-32768");
|
||||
module_param(tx_fifo_size_06, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_06, "Number of words in the Tx FIFO #06 0-32768");
|
||||
module_param(tx_fifo_size_07, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_07, "Number of words in the Tx FIFO #07 0-32768");
|
||||
module_param(tx_fifo_size_08, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_08, "Number of words in the Tx FIFO #08 0-32768");
|
||||
module_param(tx_fifo_size_09, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_09, "Number of words in the Tx FIFO #09 0-32768");
|
||||
module_param(tx_fifo_size_10, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_10, "Number of words in the Tx FIFO #10 0-32768");
|
||||
module_param(tx_fifo_size_11, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_11, "Number of words in the Tx FIFO #11 0-32768");
|
||||
module_param(tx_fifo_size_12, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_12, "Number of words in the Tx FIFO #12 0-32768");
|
||||
module_param(tx_fifo_size_13, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_13, "Number of words in the Tx FIFO #13 0-32768");
|
||||
module_param(tx_fifo_size_14, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_14, "Number of words in the Tx FIFO #14 0-32768");
|
||||
module_param(tx_fifo_size_15, long, 0444);
|
||||
MODULE_PARM_DESC(tx_fifo_size_15, "Number of words in the Tx FIFO #15 0-32768");
|
||||
|
||||
module_param(thr_ctl, short, 0444);
|
||||
MODULE_PARM_DESC(thr_ctl, "0=Without 1=With Theshold Ctrl");
|
||||
|
||||
module_param(tx_thr_length, long, 0444);
|
||||
MODULE_PARM_DESC(tx_thr_length, "TX Threshold length");
|
||||
|
||||
module_param(rx_thr_length, long, 0444);
|
||||
MODULE_PARM_DESC(rx_thr_length, "RX Threshold length");
|
||||
|
||||
#else
|
||||
module_param(nperio_tx_fifo_size, long, 0444);
|
||||
MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
|
||||
|
||||
module_param(perio_tx_fifo_size_01, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_01, "Number of words in the periodic Tx FIFO #01 0-32768");
|
||||
module_param(perio_tx_fifo_size_02, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_02, "Number of words in the periodic Tx FIFO #02 0-32768");
|
||||
module_param(perio_tx_fifo_size_03, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_03, "Number of words in the periodic Tx FIFO #03 0-32768");
|
||||
module_param(perio_tx_fifo_size_04, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_04, "Number of words in the periodic Tx FIFO #04 0-32768");
|
||||
module_param(perio_tx_fifo_size_05, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_05, "Number of words in the periodic Tx FIFO #05 0-32768");
|
||||
module_param(perio_tx_fifo_size_06, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_06, "Number of words in the periodic Tx FIFO #06 0-32768");
|
||||
module_param(perio_tx_fifo_size_07, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_07, "Number of words in the periodic Tx FIFO #07 0-32768");
|
||||
module_param(perio_tx_fifo_size_08, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_08, "Number of words in the periodic Tx FIFO #08 0-32768");
|
||||
module_param(perio_tx_fifo_size_09, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_09, "Number of words in the periodic Tx FIFO #09 0-32768");
|
||||
module_param(perio_tx_fifo_size_10, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO #10 0-32768");
|
||||
module_param(perio_tx_fifo_size_11, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO #11 0-32768");
|
||||
module_param(perio_tx_fifo_size_12, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO #12 0-32768");
|
||||
module_param(perio_tx_fifo_size_13, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO #13 0-32768");
|
||||
module_param(perio_tx_fifo_size_14, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO #14 0-32768");
|
||||
module_param(perio_tx_fifo_size_15, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO #15 0-32768");
|
||||
#endif//__DED_FIFO__
|
||||
module_param(dev_endpoints, short, 0444);
|
||||
MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
|
||||
#endif
|
||||
|
||||
#ifdef __IS_HOST__
|
||||
module_param(rx_fifo_size, long, 0444);
|
||||
MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
|
||||
|
||||
module_param(nperio_tx_fifo_size, long, 0444);
|
||||
MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
|
||||
|
||||
module_param(perio_tx_fifo_size, long, 0444);
|
||||
MODULE_PARM_DESC(perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
|
||||
|
||||
module_param(host_channels, short, 0444);
|
||||
MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
|
||||
#endif
|
||||
|
||||
module_param(max_transfer_size, long, 0444);
|
||||
MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
|
||||
|
||||
module_param(max_packet_count, long, 0444);
|
||||
MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
|
||||
|
||||
module_param(phy_utmi_width, long, 0444);
|
||||
MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
|
||||
|
||||
module_param(turn_around_time_hs, long, 0444);
|
||||
MODULE_PARM_DESC(turn_around_time_hs, "Turn-Around time for HS");
|
||||
|
||||
module_param(turn_around_time_fs, long, 0444);
|
||||
MODULE_PARM_DESC(turn_around_time_fs, "Turn-Around time for FS");
|
||||
|
||||
module_param(timeout_cal_hs, long, 0444);
|
||||
MODULE_PARM_DESC(timeout_cal_hs, "Timeout Cal for HS");
|
||||
|
||||
module_param(timeout_cal_fs, long, 0444);
|
||||
MODULE_PARM_DESC(timeout_cal_fs, "Timeout Cal for FS");
|
||||
|
||||
|
||||
1018
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_plat.h
Normal file
1018
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_plat.h
Normal file
File diff suppressed because it is too large
Load Diff
1420
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_regs.h
Normal file
1420
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxusb_regs.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,5 @@
|
||||
|
||||
#ifndef IFXUSB_VERSION
|
||||
#define IFXUSB_VERSION "3.0alpha B100312"
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user