mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
[lantiq] move files/ -> files-3.3/
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34060 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
549
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_es.c
Normal file
549
target/linux/lantiq/files-3.3/drivers/usb/ifxhcd/ifxhcd_es.c
Normal file
@@ -0,0 +1,549 @@
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/*****************************************************************************
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** FILE NAME : ifxhcd_es.c
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** PROJECT : IFX USB sub-system V3
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** MODULES : IFX USB sub-system Host and Device driver
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** SRC VERSION : 1.0
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** DATE : 1/Jan/2009
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** AUTHOR : Chen, Howard
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** DESCRIPTION : The file contain function to enable host mode USB-IF Electrical Test function.
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*****************************************************************************/
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/*!
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\file ifxhcd_es.c
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\ingroup IFXUSB_DRIVER_V3
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\brief The file contain function to enable host mode USB-IF Electrical Test function.
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*/
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#include <linux/version.h>
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#include "ifxusb_version.h"
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/dma-mapping.h>
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#include "ifxusb_plat.h"
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#include "ifxusb_regs.h"
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#include "ifxusb_cif.h"
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#include "ifxhcd.h"
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#ifdef __WITH_HS_ELECT_TST__
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/*
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* Quick and dirty hack to implement the HS Electrical Test
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* SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
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*
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* This code was copied from our userspace app "hset". It sends a
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* Get Device Descriptor control sequence in two parts, first the
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* Setup packet by itself, followed some time later by the In and
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* Ack packets. Rather than trying to figure out how to add this
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* functionality to the normal driver code, we just hijack the
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* hardware, using these two function to drive the hardware
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* directly.
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*/
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void do_setup(ifxusb_core_if_t *_core_if)
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{
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ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
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ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
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ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0];
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uint32_t *data_fifo = _core_if->data_fifo[0];
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gint_data_t gintsts;
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hctsiz_data_t hctsiz;
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hcchar_data_t hcchar;
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haint_data_t haint;
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hcint_data_t hcint;
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/* Enable HAINTs */
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ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
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/* Enable HCINTs */
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ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
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/* Read GINTSTS */
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
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/* Read HAINT */
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haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
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//fprintf(stderr, "HAINT: %08x\n", haint.d32);
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/* Read HCINT */
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hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
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//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
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/* Read HCCHAR */
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
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/* Clear HCINT */
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ifxusb_wreg(&hc_regs->hcint, hcint.d32);
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/* Clear HAINT */
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ifxusb_wreg(&hc_global_regs->haint, haint.d32);
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/* Clear GINTSTS */
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ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
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/* Read GINTSTS */
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
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/*
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* Send Setup packet (Get Device Descriptor)
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*/
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/* Make sure channel is disabled */
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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if (hcchar.b.chen) {
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//fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
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hcchar.b.chdis = 1;
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// hcchar.b.chen = 1;
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ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
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//sleep(1);
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mdelay(1000);
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/* Read GINTSTS */
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
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/* Read HAINT */
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haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
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//fprintf(stderr, "HAINT: %08x\n", haint.d32);
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/* Read HCINT */
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hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
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//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
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/* Read HCCHAR */
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
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/* Clear HCINT */
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ifxusb_wreg(&hc_regs->hcint, hcint.d32);
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/* Clear HAINT */
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ifxusb_wreg(&hc_global_regs->haint, haint.d32);
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/* Clear GINTSTS */
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ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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//if (hcchar.b.chen) {
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// fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
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//}
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}
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/* Set HCTSIZ */
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hctsiz.d32 = 0;
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hctsiz.b.xfersize = 8;
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hctsiz.b.pktcnt = 1;
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hctsiz.b.pid = IFXUSB_HC_PID_SETUP;
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ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
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/* Set HCCHAR */
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
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hcchar.b.epdir = 0;
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hcchar.b.epnum = 0;
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hcchar.b.mps = 8;
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hcchar.b.chen = 1;
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ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
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/* Fill FIFO with Setup data for Get Device Descriptor */
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ifxusb_wreg(data_fifo++, 0x01000680);
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ifxusb_wreg(data_fifo++, 0x00080000);
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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//fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
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/* Wait for host channel interrupt */
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do {
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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} while (gintsts.b.hcintr == 0);
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//fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
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/* Disable HCINTs */
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ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
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/* Disable HAINTs */
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ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
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/* Read HAINT */
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haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
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//fprintf(stderr, "HAINT: %08x\n", haint.d32);
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/* Read HCINT */
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hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
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//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
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/* Read HCCHAR */
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
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/* Clear HCINT */
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ifxusb_wreg(&hc_regs->hcint, hcint.d32);
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/* Clear HAINT */
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ifxusb_wreg(&hc_global_regs->haint, haint.d32);
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/* Clear GINTSTS */
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ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
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/* Read GINTSTS */
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
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}
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void do_in_ack(ifxusb_core_if_t *_core_if)
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{
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ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
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ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs;
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ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0];
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uint32_t *data_fifo = _core_if->data_fifo[0];
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gint_data_t gintsts;
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hctsiz_data_t hctsiz;
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hcchar_data_t hcchar;
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haint_data_t haint;
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hcint_data_t hcint;
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grxsts_data_t grxsts;
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/* Enable HAINTs */
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ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001);
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/* Enable HCINTs */
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ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3);
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/* Read GINTSTS */
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
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/* Read HAINT */
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haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
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//fprintf(stderr, "HAINT: %08x\n", haint.d32);
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/* Read HCINT */
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hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
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//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
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/* Read HCCHAR */
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
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/* Clear HCINT */
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ifxusb_wreg(&hc_regs->hcint, hcint.d32);
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/* Clear HAINT */
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ifxusb_wreg(&hc_global_regs->haint, haint.d32);
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/* Clear GINTSTS */
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ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
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/* Read GINTSTS */
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
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/*
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* Receive Control In packet
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*/
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/* Make sure channel is disabled */
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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if (hcchar.b.chen) {
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//fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
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hcchar.b.chdis = 1;
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hcchar.b.chen = 1;
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ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
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//sleep(1);
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mdelay(1000);
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/* Read GINTSTS */
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gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
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/* Read HAINT */
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haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
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//fprintf(stderr, "HAINT: %08x\n", haint.d32);
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/* Read HCINT */
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hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
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//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
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/* Read HCCHAR */
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
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/* Clear HCINT */
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ifxusb_wreg(&hc_regs->hcint, hcint.d32);
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/* Clear HAINT */
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ifxusb_wreg(&hc_global_regs->haint, haint.d32);
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/* Clear GINTSTS */
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ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
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||||
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hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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||||
//if (hcchar.b.chen) {
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// fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
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||||
//}
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||||
}
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||||
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/* Set HCTSIZ */
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hctsiz.d32 = 0;
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||||
hctsiz.b.xfersize = 8;
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hctsiz.b.pktcnt = 1;
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||||
hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
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||||
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
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||||
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||||
/* Set HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
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||||
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
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||||
hcchar.b.epdir = 1;
|
||||
hcchar.b.epnum = 0;
|
||||
hcchar.b.mps = 8;
|
||||
hcchar.b.chen = 1;
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||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
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||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
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||||
//fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for receive status queue interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.rxstsqlvl == 0);
|
||||
|
||||
//fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Read RXSTS */
|
||||
grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
|
||||
//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
|
||||
|
||||
/* Clear RXSTSQLVL in GINTSTS */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.rxstsqlvl = 1;
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
switch (grxsts.hb.pktsts) {
|
||||
case IFXUSB_HSTS_DATA_UPDT:
|
||||
/* Read the data into the host buffer */
|
||||
if (grxsts.hb.bcnt > 0) {
|
||||
int i;
|
||||
int word_count = (grxsts.hb.bcnt + 3) / 4;
|
||||
|
||||
for (i = 0; i < word_count; i++) {
|
||||
(void)ifxusb_rreg(data_fifo++);
|
||||
}
|
||||
}
|
||||
|
||||
//fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.hb.bcnt);
|
||||
break;
|
||||
|
||||
default:
|
||||
//fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
|
||||
break;
|
||||
}
|
||||
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for receive status queue interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.rxstsqlvl == 0);
|
||||
|
||||
//fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Read RXSTS */
|
||||
grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp);
|
||||
//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
|
||||
|
||||
/* Clear RXSTSQLVL in GINTSTS */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.rxstsqlvl = 1;
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
switch (grxsts.hb.pktsts) {
|
||||
case IFXUSB_HSTS_XFER_COMP:
|
||||
break;
|
||||
|
||||
default:
|
||||
//fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
|
||||
break;
|
||||
}
|
||||
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for host channel interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.hcintr == 0);
|
||||
|
||||
//fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
// usleep(100000);
|
||||
// mdelay(100);
|
||||
mdelay(1);
|
||||
|
||||
/*
|
||||
* Send handshake packet
|
||||
*/
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/* Make sure channel is disabled */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
if (hcchar.b.chen) {
|
||||
//fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
|
||||
hcchar.b.chdis = 1;
|
||||
hcchar.b.chen = 1;
|
||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
//sleep(1);
|
||||
mdelay(1000);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//if (hcchar.b.chen) {
|
||||
// fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
|
||||
//}
|
||||
}
|
||||
|
||||
/* Set HCTSIZ */
|
||||
hctsiz.d32 = 0;
|
||||
hctsiz.b.xfersize = 0;
|
||||
hctsiz.b.pktcnt = 1;
|
||||
hctsiz.b.pid = IFXUSB_HC_PID_DATA1;
|
||||
ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32);
|
||||
|
||||
/* Set HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL;
|
||||
hcchar.b.epdir = 0;
|
||||
hcchar.b.epnum = 0;
|
||||
hcchar.b.mps = 8;
|
||||
hcchar.b.chen = 1;
|
||||
ifxusb_wreg(&hc_regs->hcchar, hcchar.d32);
|
||||
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Wait for host channel interrupt */
|
||||
do {
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
} while (gintsts.b.hcintr == 0);
|
||||
|
||||
//fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
|
||||
|
||||
/* Disable HCINTs */
|
||||
ifxusb_wreg(&hc_regs->hcintmsk, 0x0000);
|
||||
|
||||
/* Disable HAINTs */
|
||||
ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000);
|
||||
|
||||
/* Read HAINT */
|
||||
haint.d32 = ifxusb_rreg(&hc_global_regs->haint);
|
||||
//fprintf(stderr, "HAINT: %08x\n", haint.d32);
|
||||
|
||||
/* Read HCINT */
|
||||
hcint.d32 = ifxusb_rreg(&hc_regs->hcint);
|
||||
//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
|
||||
|
||||
/* Read HCCHAR */
|
||||
hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar);
|
||||
//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
|
||||
|
||||
/* Clear HCINT */
|
||||
ifxusb_wreg(&hc_regs->hcint, hcint.d32);
|
||||
|
||||
/* Clear HAINT */
|
||||
ifxusb_wreg(&hc_global_regs->haint, haint.d32);
|
||||
|
||||
/* Clear GINTSTS */
|
||||
ifxusb_wreg(&global_regs->gintsts, gintsts.d32);
|
||||
|
||||
/* Read GINTSTS */
|
||||
gintsts.d32 = ifxusb_rreg(&global_regs->gintsts);
|
||||
//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
|
||||
}
|
||||
#endif //__WITH_HS_ELECT_TST__
|
||||
|
||||
Reference in New Issue
Block a user