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[ar71xx] define some bits of the ethernet controller's registers

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13201 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2008-11-14 08:57:31 +00:00
parent 9db8a8bc5d
commit 10b1167329
4 changed files with 56 additions and 8 deletions
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4
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
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@@ -100,14 +100,14 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
ifctl &= ~(MAC_IFCTL_SPEED);
fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK;
fifo5 &= ~FIFO_CFG5_BM;
switch (ag->speed) {
case SPEED_1000:
mii_speed = MII_CTRL_SPEED_1000;
cfg2 |= MAC_CFG2_IF_1000;
pll = PLL_VAL_1000;
fifo5 |= FIFO_CFG5_BYTE_PER_CLK;
fifo5 |= FIFO_CFG5_BM;
break;
case SPEED_100:
mii_speed = MII_CTRL_SPEED_100;