mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-21 00:10:14 +03:00
fixes several compile errors, reserves memory for second core, adds u-boot env parsing for ifxmips
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11558 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
19f6dff761
commit
112576f704
@ -29,25 +29,28 @@
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#include <asm/bootinfo.h>
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#include <asm/bootinfo.h>
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#include <asm/ifxmips/ifxmips.h>
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#include <asm/ifxmips/ifxmips.h>
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static char buf[1024];
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static char buf[1024];
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u32 *prom_cp1_base = NULL;
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u32 prom_cp1_size = 0;
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void
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void
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prom_free_prom_memory (void)
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prom_free_prom_memory(void)
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{
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{
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}
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}
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void
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void
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prom_putchar (char c)
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prom_putchar(char c)
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{
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{
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while ((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
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while((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
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if (c == '\n')
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if(c == '\n')
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ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
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ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
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ifxmips_w32(c, IFXMIPS_ASC1_TBUF);
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ifxmips_w32(c, IFXMIPS_ASC1_TBUF);
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}
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}
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void
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void
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prom_printf (const char * fmt, ...)
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prom_printf(const char * fmt, ...)
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{
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{
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va_list args;
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va_list args;
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int l;
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int l;
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@ -58,17 +61,69 @@ prom_printf (const char * fmt, ...)
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va_end(args);
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va_end(args);
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buf_end = buf + l;
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buf_end = buf + l;
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for (p = buf; p < buf_end; p++)
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for(p = buf; p < buf_end; p++)
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{
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{
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prom_putchar(*p);
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prom_putchar(*p);
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}
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}
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}
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}
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u32 *prom_get_cp1_base(void)
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{
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return prom_cp1_base;
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}
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u32 prom_get_cp1_size(void)
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{
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return prom_cp1_size;
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}
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void __init
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void __init
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prom_init(void)
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prom_init(void)
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{
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{
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int argc = fw_arg0;
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char **argv = (char **) fw_arg1;
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char **envp = (char **) fw_arg2;
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int memsize = 16;
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int i;
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mips_machtype = MACH_INFINEON_IFXMIPS;
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mips_machtype = MACH_INFINEON_IFXMIPS;
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strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
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argv = (char**)KSEG1ADDR((unsigned long)argv);
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add_memory_region (0x00000000, 0x2000000, BOOT_MEM_RAM);
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arcs_cmdline[0] = '\0';
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for(i = 1; i < argc; i++)
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{
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char *a = (char*)KSEG1ADDR(argv[i]);
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if(!a)
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continue;
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if(strlen(arcs_cmdline) + strlen(a + 1) >= sizeof(arcs_cmdline))
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break;
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strcat(arcs_cmdline, a);
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strcat(arcs_cmdline, " ");
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}
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envp = (char**)KSEG1ADDR((unsigned long)envp);
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while(*envp)
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{
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char *e = (char*)KSEG1ADDR(*envp);
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if(!strncmp(e, "memsize=", 8))
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{
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e += 8;
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memsize = simple_strtoul(e, NULL, 10);
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}
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envp++;
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}
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prom_cp1_size = 2;
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memsize -= prom_cp1_size;
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prom_cp1_base = (u32*)(0xA0000000 + (memsize * 1024 * 1024));
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prom_printf(KERN_INFO "Using %dMB Ram and reserving %dMB for cp1\n", memsize, prom_cp1_size);
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memsize *= 1024 * 1024;
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if(!*arcs_cmdline)
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strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
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add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
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}
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}
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@ -129,7 +129,7 @@ detect_squashfs_partition (unsigned long start_offset){
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}
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}
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static int
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static int
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ifxmips_mtd_probe (void)
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ifxmips_mtd_probe (struct platform_device *dev)
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{
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{
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struct mtd_info *ifxmips_mtd = NULL;
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struct mtd_info *ifxmips_mtd = NULL;
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struct mtd_partition *parts = NULL;
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struct mtd_partition *parts = NULL;
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@ -88,7 +88,7 @@
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#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
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#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
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/* control */
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/* control */
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#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
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#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
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/* timer reload */
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/* timer reload */
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#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
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#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
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@ -103,12 +103,12 @@
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/*------------ RCU */
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/*------------ RCU */
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#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
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#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
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/* reset request */
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/* reset request */
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#define IFXMIPS_RCU_REQ ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
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#define IFXMIPS_RCU_RST ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
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#define IFXMIPS_RST_ALL 0x40000000
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#define IFXMIPS_RCU_RST_CPU1 (1 << 3)
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#define IFXMIPS_RCU_RST_ALL 0x40000000
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#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)
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#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)
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#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)
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#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)
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@ -440,6 +440,45 @@
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#define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
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#define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
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/*------------ DEU */
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#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100)
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#define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000))
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#define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008))
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#define IFXMIPS_DES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0010))
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#define IFXMIPS_DES_IHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0014))
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#define IFXMIPS_DES_ILR ((u32 *)(IFXMIPS_DEU_BASE + 0x0018))
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#define IFXMIPS_DES_K1HR ((u32 *)(IFXMIPS_DEU_BASE + 0x001C))
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#define IFXMIPS_DES_K1LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0020))
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#define IFXMIPS_DES_K3HR ((u32 *)(IFXMIPS_DEU_BASE + 0x0024))
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#define IFXMIPS_DES_K3LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0028))
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#define IFXMIPS_DES_IVHR ((u32 *)(IFXMIPS_DEU_BASE + 0x002C))
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#define IFXMIPS_DES_IVLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0030))
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#define IFXMIPS_DES_OHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0040))
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#define IFXMIPS_DES_OLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
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#define IFXMIPS_AES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
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#define IFXMIPS_AES_ID3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0054))
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#define IFXMIPS_AES_ID2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0058))
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#define IFXMIPS_AES_ID1R ((u32 *)(IFXMIPS_DEU_BASE + 0x005C))
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#define IFXMIPS_AES_ID0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0060))
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#define IFXMIPS_AES_K7R ((u32 *)(IFXMIPS_DEU_BASE + 0x0064))
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#define IFXMIPS_AES_K6R ((u32 *)(IFXMIPS_DEU_BASE + 0x0068))
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#define IFXMIPS_AES_K5R ((u32 *)(IFXMIPS_DEU_BASE + 0x006C))
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#define IFXMIPS_AES_K4R ((u32 *)(IFXMIPS_DEU_BASE + 0x0070))
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#define IFXMIPS_AES_K3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0074))
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#define IFXMIPS_AES_K2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0078))
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#define IFXMIPS_AES_K1R ((u32 *)(IFXMIPS_DEU_BASE + 0x007C))
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#define IFXMIPS_AES_K0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0080))
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#define IFXMIPS_AES_IV3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0084))
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#define IFXMIPS_AES_IV2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0088))
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#define IFXMIPS_AES_IV1R ((u32 *)(IFXMIPS_DEU_BASE + 0x008C))
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#define IFXMIPS_AES_IV0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0090))
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#define IFXMIPS_AES_0D3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0094))
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#define IFXMIPS_AES_0D2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0098))
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#define IFXMIPS_AES_OD1R ((u32 *)(IFXMIPS_DEU_BASE + 0x009C))
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#define IFXMIPS_AES_OD0R ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0))
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/*------------ FUSE */
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/*------------ FUSE */
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#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)
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#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)
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@ -448,6 +487,7 @@
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/*------------ MPS */
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/*------------ MPS */
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#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
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#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
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#define IFXMIPS_MPS_SRAM ((u32*)(KSEG1 + 0x1F200000))
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#define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
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#define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
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#define IFXMIPS_MPS_VC0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
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#define IFXMIPS_MPS_VC0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
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@ -139,24 +139,16 @@ struct gptu_ioctl_param {
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* Data Type
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* Data Type
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* ####################################
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* ####################################
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*/
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*/
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#if defined(__KERNEL__)
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typedef void (*timer_callback)(unsigned long arg);
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typedef void (*timer_callback)(unsigned long arg);
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#endif // defined(__KERNEL__)
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/*
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* ####################################
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* Declaration
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* ####################################
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*/
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#if defined(__KERNEL__)
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#if defined(__KERNEL__)
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extern int request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
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extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
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extern int free_timer(unsigned int);
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extern int ifxmips_free_timer(unsigned int);
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extern int start_timer(unsigned int, int);
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extern int ifxmips_start_timer(unsigned int, int);
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extern int stop_timer(unsigned int);
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extern int ifxmips_stop_timer(unsigned int);
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extern int reset_counter_flags(u32 timer, u32 flags);
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extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
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extern int get_count_value(unsigned int, unsigned long *);
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extern int ifxmips_get_count_value(unsigned int, unsigned long *);
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extern u32 cal_divider(unsigned long);
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extern u32 cal_divider(unsigned long);
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@ -0,0 +1,27 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
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*
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*/
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#ifndef _IFXPROM_H__
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#define _IFXPROM_H__
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void prom_printf(const char * fmt, ...);
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u32 *prom_get_cp1_base(void);
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u32 prom_get_cp1_size(void);
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#endif
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@ -28,14 +28,17 @@
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static inline int gpio_direction_input(unsigned gpio) {
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static inline int gpio_direction_input(unsigned gpio) {
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ifxmips_port_set_dir_in(0, gpio);
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ifxmips_port_set_dir_in(0, gpio);
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return 0;
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}
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}
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static inline int gpio_direction_output(unsigned gpio, int value) {
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static inline int gpio_direction_output(unsigned gpio, int value) {
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ifxmips_port_set_dir_out(0, gpio);
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ifxmips_port_set_dir_out(0, gpio);
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return 0;
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}
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}
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static inline int gpio_get_value(unsigned gpio) {
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static inline int gpio_get_value(unsigned gpio) {
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ifxmips_port_get_input(0, gpio);
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ifxmips_port_get_input(0, gpio);
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return 0;
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}
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}
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static inline void gpio_set_value(unsigned gpio, int value) {
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static inline void gpio_set_value(unsigned gpio, int value) {
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