mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 12:45:33 +02:00
amazon: work on pci controller
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19013 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
d575b44570
commit
12b06b0a8d
@ -138,6 +138,7 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
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# CONFIG_SIBYTE_SENTOSA is not set
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# CONFIG_SIBYTE_SENTOSA is not set
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# CONFIG_SIBYTE_SWARM is not set
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# CONFIG_SIBYTE_SWARM is not set
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# CONFIG_SLOW_WORK is not set
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# CONFIG_SLOW_WORK is not set
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CONFIG_SWAP_IO_SPACE=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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@ -36,7 +36,7 @@
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#endif
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#endif
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#define AMAZON_PCI_MEM_SIZE 0x00400000
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#define AMAZON_PCI_MEM_SIZE 0x00400000
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#define AMAZON_PCI_IO_BASE 0xb2400000
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#define AMAZON_PCI_IO_BASE 0xb2400000
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#define AMAZON_PCI_IO_SIZE 0x00002000
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#define AMAZON_PCI_IO_SIZE 0x00200000
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#define AMAZON_PCI_CFG_BUSNUM_SHF 16
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#define AMAZON_PCI_CFG_BUSNUM_SHF 16
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#define AMAZON_PCI_CFG_DEVNUM_SHF 11
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#define AMAZON_PCI_CFG_DEVNUM_SHF 11
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@ -45,27 +45,15 @@
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#define PCI_ACCESS_WRITE 1
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static inline u32 amazon_r32(u32 addr)
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{
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u32 *ptr = (u32 *) addr;
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return __raw_readl(ptr);
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}
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static inline void amazon_w32(u32 addr, u32 val)
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{
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u32 *ptr = (u32 *) addr;
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__raw_writel(val, ptr);
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}
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static struct resource pci_io_resource = {
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static struct resource pci_io_resource = {
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.name = "io pci IO space",
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.name = "io pci IO space",
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#if 0
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#if 1
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.start = AMAZON_PCI_IO_BASE,
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.start = AMAZON_PCI_IO_BASE,
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.end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
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.end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
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#endif
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#else
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.start = 0,
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.start = 0,
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.end = AMAZON_PCI_IO_SIZE - 1,
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.end = 0x00002000 - 1,
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#endif
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.flags = IORESOURCE_IO
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.flags = IORESOURCE_IO
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};
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};
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@ -76,15 +64,6 @@ static struct resource pci_mem_resource = {
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.flags = IORESOURCE_MEM
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.flags = IORESOURCE_MEM
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};
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};
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static inline u32 amazon_pci_swap(u32 val)
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{
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#ifdef CONFIG_AMAZON_PCI_HW_SWAP
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return swab32(val);
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#else
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return val;
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#endif
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}
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static int amazon_pci_config_access(unsigned char access_type,
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static int amazon_pci_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
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struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
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{
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{
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@ -92,31 +71,43 @@ static int amazon_pci_config_access(unsigned char access_type,
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u32 pci_addr;
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u32 pci_addr;
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u32 val;
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u32 val;
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int ret;
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int ret;
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/* Amazon support slot from 0 to 15 */
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/* Amazon support slot from 0 to 15 */
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/* devfn 0 & 0x20 is itself */
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/* devfn 0 & 0x20 is itself */
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if ((bus->number != 0) || (devfn == 0) || (devfn == 0x20))
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if ((bus->number != 0) || (devfn > 0x7f) || (devfn == 0) || (devfn == 0x20))
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return 1;
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return 1;
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pci_addr=AMAZON_PCI_CFG_BASE |
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local_irq_save(flags);
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pci_addr = AMAZON_PCI_CFG_BASE |
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bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
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bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
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devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
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devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
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(where & ~0x3);
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(where & ~0x3);
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local_irq_save(flags);
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if (access_type == PCI_ACCESS_WRITE)
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if (access_type == PCI_ACCESS_WRITE) {
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{
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val = amazon_pci_swap(*data);
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#ifdef CONFIG_SWAP_IO_SPACE
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val = swab32(*data);
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#endif
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ret = put_dbe(val, (u32 *)pci_addr);
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ret = put_dbe(val, (u32 *)pci_addr);
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} else {
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} else {
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ret = get_dbe(val, (u32 *)pci_addr);
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ret = get_dbe(val, (u32 *)pci_addr);
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*data = amazon_pci_swap(val);
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#ifdef CONFIG_SWAP_IO_SPACE
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*data = swab32(val);
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#else
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*data = val;
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#endif
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}
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}
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amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
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amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
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amazon_w32(STATUS_COMMAND_ADDR, amazon_r32(STATUS_COMMAND_ADDR));
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amazon_writel(amazon_readl(STATUS_COMMAND_ADDR), STATUS_COMMAND_ADDR);
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amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
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amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
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mb();
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local_irq_restore(flags);
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local_irq_restore(flags);
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if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
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return 1;
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return ret;
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return ret;
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}
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}
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@ -172,7 +163,9 @@ static struct pci_ops amazon_pci_ops = {
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static struct pci_controller amazon_pci_controller = {
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static struct pci_controller amazon_pci_controller = {
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.pci_ops = &amazon_pci_ops,
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.pci_ops = &amazon_pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_resource = &pci_mem_resource,
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.io_resource = &pci_io_resource
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.mem_offset = 0x00000000UL,
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.io_resource = &pci_io_resource,
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.io_offset = 0x00000000UL,
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};
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};
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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@ -237,13 +230,13 @@ int __init amazon_pci_init(void)
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{
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{
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u32 temp_buffer;
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u32 temp_buffer;
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#ifdef CONFIG_AMAZON_PCI_HW_SWAP
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#ifdef CONFIG_SWAP_IO_SPACE
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AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
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AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
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wmb();
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wmb();
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#endif
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#endif
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AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
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AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
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amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
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amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
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AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
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AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
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@ -271,15 +264,15 @@ int __init amazon_pci_init(void)
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
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AMAZON_PCI_REG32(BAR11_MASK) = 0x0f000008;
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AMAZON_PCI_REG32(BAR11_MASK) = 0x0c000008;
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AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
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AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
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AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
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AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
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amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
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amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
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//use 8 dw burse length
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//use 8 dw burse length
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AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
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AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
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amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE);
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amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE - 1);
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register_pci_controller(&amazon_pci_controller);
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register_pci_controller(&amazon_pci_controller);
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return 0;
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return 0;
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}
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}
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@ -155,6 +155,11 @@ void __init plat_mem_setup(void)
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amazon_writel(0x3fff, AMAZON_PMU_PWDCR);
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amazon_writel(0x3fff, AMAZON_PMU_PWDCR);
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//reenable trace capability
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//reenable trace capability
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part_no = readl(AMAZON_BCU_ECON);
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part_no = readl(AMAZON_BCU_ECON);
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ioport_resource.start = IOPORT_RESOURCE_START;
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ioport_resource.end = IOPORT_RESOURCE_END;
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iomem_resource.start = IOMEM_RESOURCE_START;
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iomem_resource.end = IOMEM_RESOURCE_END;
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}
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}
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static void amazon_machine_restart(char *command)
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static void amazon_machine_restart(char *command)
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@ -25,9 +25,14 @@
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other party has been advised of the possibility of such damages.
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other party has been advised of the possibility of such damages.
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******************************************************************************/
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******************************************************************************/
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#define amazon_readl(a) readl(((u32*)(a)))
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#define amazon_readl(a) __raw_readl(((u32*)(a)))
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#define amazon_writel(a,b) writel(a, ((u32*)(b)))
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#define amazon_writel(a,b) __raw_writel(a, ((u32*)(b)))
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#define amazon_writel_masked(a,b,c) writel((readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a)))
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#define amazon_writel_masked(a,b,c) __raw_writel((__raw_readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a)))
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#define IOPORT_RESOURCE_START 0x10000000
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#define IOPORT_RESOURCE_END 0xffffffff
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#define IOMEM_RESOURCE_START 0x10000000
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#define IOMEM_RESOURCE_END 0xffffffff
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/* check ADSL link status */
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/* check ADSL link status */
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#define AMAZON_CHECK_LINK
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#define AMAZON_CHECK_LINK
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@ -1,52 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Ralf Baechle
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*/
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#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
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#define __ASM_MACH_GENERIC_MANGLE_PORT_H
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#define __swizzle_addr_b(port) (port)
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#define __swizzle_addr_w(port) ((port) ^ 2)
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#define __swizzle_addr_l(port) (port)
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#define __swizzle_addr_q(port) (port)
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/*
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* Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
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* less sane hardware forces software to fiddle with this...
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*
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* Regardless, if the host bus endianness mismatches that of PCI/ISA, then
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* you can't have the numerical value of data and byte addresses within
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* multibyte quantities both preserved at the same time. Hence two
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* variations of functions: non-prefixed ones that preserve the value
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* and prefixed ones that preserve byte addresses. The latters are
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* typically used for moving raw data between a peripheral and memory (cf.
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* string I/O functions), hence the "__mem_" prefix.
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*/
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#if defined(CONFIG_SWAP_IO_SPACE)
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# define ioswabb(a,x) (x)
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# define __mem_ioswabb(a,x) (x)
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# define ioswabw(a,x) le16_to_cpu(x)
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# define __mem_ioswabw(a,x) (x)
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# define ioswabl(a,x) le32_to_cpu(x)
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# define __mem_ioswabl(a,x) (x)
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# define ioswabq(a,x) le64_to_cpu(x)
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# define __mem_ioswabq(a,x) (x)
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#else
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# define ioswabb(a,x) (x)
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# define __mem_ioswabb(a,x) (x)
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# define ioswabw(a,x) (x)
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# define __mem_ioswabw(a,x) cpu_to_le16(x)
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# define ioswabl(a,x) (x)
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# define __mem_ioswabl(a,x) cpu_to_le32(x)
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# define ioswabq(a,x) (x)
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# define __mem_ioswabq(a,x) cpu_to_le32(x)
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#endif
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#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
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@ -1,6 +1,6 @@
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--- a/arch/mips/Kconfig
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -60,6 +60,21 @@ config BCM47XX
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@@ -60,6 +60,22 @@ config BCM47XX
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help
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help
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Support for BCM47XX based boards
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Support for BCM47XX based boards
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@ -18,11 +18,12 @@
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+ select SYS_SUPPORTS_32BIT_KERNEL
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+ select SYS_SUPPORTS_32BIT_KERNEL
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+ select SYS_HAS_EARLY_PRINTK
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+ select SYS_HAS_EARLY_PRINTK
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+ select HW_HAS_PCI
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+ select HW_HAS_PCI
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+ select SWAP_IO_SPACE
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+
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+
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config MIPS_COBALT
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config MIPS_COBALT
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bool "Cobalt Server"
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bool "Cobalt Server"
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select CEVT_R4K
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select CEVT_R4K
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@@ -633,6 +648,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
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@@ -633,6 +649,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
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endchoice
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endchoice
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