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git://projects.qi-hardware.com/openwrt-xburst.git
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ar71xx: configure MII interface type from ar71xx_setup_phy_if_mode
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29010 3c298f89-4303-0410-b956-a3cf2f4a3e73
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4cc612872a
commit
13e0098939
@ -190,6 +190,22 @@ static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
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iounmap(base);
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}
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static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
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unsigned int mii_if)
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{
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void __iomem *base;
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u32 t;
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base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
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t = __raw_readl(base + reg);
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t &= ~(MII_CTRL_IF_MASK);
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t |= (mii_if & MII_CTRL_IF_MASK);
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__raw_writel(t, base + reg);
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iounmap(base);
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}
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void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
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{
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struct platform_device *mdio_dev;
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@ -588,6 +604,8 @@ static void __init ar71xx_init_eth_pll_data(unsigned int id)
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static int __init ar71xx_setup_phy_if_mode(unsigned int id,
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struct ag71xx_platform_data *pdata)
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{
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unsigned int mii_if;
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switch (id) {
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case 0:
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switch (ar71xx_soc) {
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@ -598,20 +616,21 @@ static int __init ar71xx_setup_phy_if_mode(unsigned int id,
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case AR71XX_SOC_AR9132:
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switch (pdata->phy_if_mode) {
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case PHY_INTERFACE_MODE_MII:
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pdata->mii_if = MII0_CTRL_IF_MII;
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mii_if = MII0_CTRL_IF_MII;
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break;
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case PHY_INTERFACE_MODE_GMII:
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pdata->mii_if = MII0_CTRL_IF_GMII;
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mii_if = MII0_CTRL_IF_GMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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pdata->mii_if = MII0_CTRL_IF_RGMII;
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mii_if = MII0_CTRL_IF_RGMII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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pdata->mii_if = MII0_CTRL_IF_RMII;
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mii_if = MII0_CTRL_IF_RMII;
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break;
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default:
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return -EINVAL;
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}
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ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
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break;
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case AR71XX_SOC_AR7240:
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@ -651,14 +670,15 @@ static int __init ar71xx_setup_phy_if_mode(unsigned int id,
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case AR71XX_SOC_AR9132:
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switch (pdata->phy_if_mode) {
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case PHY_INTERFACE_MODE_RMII:
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pdata->mii_if = MII1_CTRL_IF_RMII;
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mii_if = MII1_CTRL_IF_RMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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pdata->mii_if = MII1_CTRL_IF_RGMII;
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mii_if = MII1_CTRL_IF_RGMII;
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break;
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default:
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return -EINVAL;
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}
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ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
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break;
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case AR71XX_SOC_AR7240:
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@ -816,6 +816,8 @@ void ar71xx_flash_release(void);
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#define MII_REG_MII0_CTRL 0x00
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#define MII_REG_MII1_CTRL 0x04
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#define MII_CTRL_IF_MASK 3
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#define MII0_CTRL_IF_GMII 0
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#define MII0_CTRL_IF_MII 1
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#define MII0_CTRL_IF_RGMII 2
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