[ifxmips] add .32 patches

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21150 3c298f89-4303-0410-b956-a3cf2f4a3e73

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/Kconfig

@@ -0,0 +1,125 @@
+if IFXMIPS
+
+choice
+	prompt "Infineon SoC chip selection"
+	default SOC_DANUBE
+	help
+		Select Infineon MIPS SoC type.
+
+	config IFXMIPS_DANUBE
+		bool "Danube/Twinpass"
+		select SOC_DANUBE
+
+	config IFXMIPS_ASE
+		bool "Amazon-SE"
+		select SOC_ASE
+
+	config IFXMIPS_AR9
+		bool "AR9"
+		select SOC_AR9
+
+	config IFXMIPS_VR9
+		bool "VR9"
+		select SOC_VR9
+
+endchoice
+
+source "arch/mips/ifxmips/danube/Kconfig"
+
+config SOC_DANUBE
+	bool
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select CEVT_R4K
+	select CSRC_R4K
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_HAS_CPU_MIPS32_R2
+	select HAVE_STD_PC_SERIAL_PORT
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_MULTITHREADING
+	select SYS_HAS_EARLY_PRINTK
+	select HW_HAS_PCI
+	select ARCH_REQUIRE_GPIOLIB
+	select SWAP_IO_SPACE
+	select MIPS_MACHINE
+
+config SOC_ASE
+	bool
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select CEVT_R4K
+	select CSRC_R4K
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_HAS_CPU_MIPS32_R2
+	select HAVE_STD_PC_SERIAL_PORT
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_MULTITHREADING
+	select SYS_HAS_EARLY_PRINTK
+	select HW_HAS_PCI
+	select ARCH_REQUIRE_GPIOLIB
+	select SWAP_IO_SPACE
+	select MIPS_MACHINE
+
+config SOC_AR9
+	bool
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select CEVT_R4K
+	select CSRC_R4K
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_HAS_CPU_MIPS32_R2
+	select HAVE_STD_PC_SERIAL_PORT
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_MULTITHREADING
+	select SYS_HAS_EARLY_PRINTK
+	select HW_HAS_PCI
+	select ARCH_REQUIRE_GPIOLIB
+	select SWAP_IO_SPACE
+	select MIPS_MACHINE
+
+config SOC_VR9
+	bool
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select CEVT_R4K
+	select CSRC_R4K
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_HAS_CPU_MIPS32_R2
+	select HAVE_STD_PC_SERIAL_PORT
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_MULTITHREADING
+	select SYS_HAS_EARLY_PRINTK
+	select HW_HAS_PCI
+	select ARCH_REQUIRE_GPIOLIB
+	select SWAP_IO_SPACE
+	select MIPS_MACHINE
+
+if EARLY_PRINTK
+menu "Infineon SoC settings"
+
+choice
+	prompt "Early printk port"
+	help
+	  Choose which serial port is used, until the console driver is loaded
+
+config IFXMIPS_PROM_ASC0
+	bool "ASC0"
+
+config IFXMIPS_PROM_ASC1
+	bool "ASC1"
+
+endchoice
+
+config IFXMIPS_COMPAT
+	bool "Spinacer compatibility"
+	default y
+	help
+	  Enable this to get some legacy API. This is needed if you use Lantiq DSL and VOIP drivers.
+
+endmenu
+endif
+endif

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/Makefile

@@ -0,0 +1 @@
+obj-y := reset.o prom.o setup.o irq.o dma-core.o pmu.o board.o clock.o gpio.o timer.o dev-gpio-buttons.o

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/Kconfig

@@ -0,0 +1,29 @@
+if IFXMIPS_DANUBE
+
+config IFXMIPS_ARCAYDIAN_BRNBOOT
+	bool
+	default n
+
+menu "infineon SoC machine selection"
+
+config DANUBE_MACH_EASY50712
+	bool "Easy50712"
+	default y
+
+config DANUBE_MACH_EASY4010
+	bool "Easy4010"
+	default y
+
+config DANUBE_MACH_ARV4519
+	bool "ARV4519"
+	default y
+	select DANUBE_ARCAYDIAN_BRNBOOT
+
+config DANUBE_MACH_ARV452
+	bool "ARV452"
+	default y
+	select IFXMIPS_ARCAYDIAN_BRNBOOT
+
+endmenu
+
+endif

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/Makefile

@@ -0,0 +1,3 @@
+obj-y := dma-core.o irq.o ebu.o setup.o devices.o cgu.o
+obj-$(CONFIG_IFXMIPS_ARCAYDIAN_BRNBOOT) += arcaydian.o
+obj-$(CONFIG_DANUBE_MACH_ARV452) += mach-arv452.o

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/board.c

@@ -0,0 +1,457 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mtd/physmap.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/reboot.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+
+#define MAX_BOARD_NAME_LEN		32
+#define MAX_IFXMIPS_DEVS		9
+
+#define SYSTEM_DANUBE			"Danube"
+#define SYSTEM_DANUBE_CHIPID1	0x00129083
+#define SYSTEM_DANUBE_CHIPID2	0x0012B083
+
+#define SYSTEM_TWINPASS			"Twinpass"
+#define SYSTEM_TWINPASS_CHIPID	0x0012D083
+
+enum {
+	EASY50712,
+	EASY4010,
+	ARV4519,
+	ARV452,
+};
+
+extern int ifxmips_pci_external_clock;
+extern int ifxmips_pci_req_mask;
+
+static unsigned int chiprev;
+static int cmdline_mac;
+char board_name[MAX_BOARD_NAME_LEN + 1] = { 0 };
+
+struct ifxmips_board {
+	int type;
+	char name[32];
+	unsigned int system_type;
+	struct platform_device **devs;
+	struct resource reset_resource;
+	struct resource gpiodev_resource;
+	struct gpio_led *ifxmips_leds;
+	struct gpio_led *gpio_leds;
+	int pci_external_clock;
+	int pci_req_mask;
+	int num_devs;
+};
+
+DEFINE_SPINLOCK(ebu_lock);
+EXPORT_SYMBOL_GPL(ebu_lock);
+
+extern unsigned char ifxmips_ethaddr[6];
+static int ifxmips_brn;
+
+static struct gpio_led_platform_data ifxmips_led_data;
+
+static struct platform_device ifxmips_led = {
+	.id = 0,
+	.name = "ifxmips_led",
+	.dev = {
+		.platform_data = (void *) &ifxmips_led_data,
+	}
+};
+
+static struct platform_device ifxmips_gpio = {
+	.id = 0,
+	.name = "ifxmips_gpio",
+	.num_resources = 1,
+};
+
+static struct platform_device ifxmips_mii = {
+	.id = 0,
+	.name = "ifxmips_mii0",
+	.dev = {
+		.platform_data = ifxmips_ethaddr,
+	}
+};
+
+static struct platform_device ifxmips_wdt = {
+	.id = 0,
+	.name = "ifxmips_wdt",
+};
+
+static struct platform_device ifxmips_ebu = {
+	.id = 0,
+	.name = "ifxmips_ebu",
+};
+
+static struct resource ifxmips_mtd_resource = {
+	.start  = IFXMIPS_FLASH_START,
+	.end    = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1,
+	.flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device ifxmips_mtd = {
+	.id = 0,
+	.name = "ifxmips_mtd",
+	.num_resources  = 1,
+	.resource   = &ifxmips_mtd_resource,
+};
+
+static struct platform_device ifxmips_gpio_dev = {
+	.name     = "GPIODEV",
+	.id     = -1,
+	.num_resources    =	1,
+};
+
+#ifdef CONFIG_LEDS_GPIO
+static struct gpio_led arv4519_gpio_leds[] = {
+	{ .name = "ifx:green:power", .gpio = 3, .active_low = 1, },
+	{ .name = "ifx:red:power", .gpio = 7, .active_low = 1, },
+	{ .name = "ifx:green:adsl", .gpio = 4, .active_low = 1, },
+	{ .name = "ifx:green:internet", .gpio = 5, .active_low = 1, },
+	{ .name = "ifx:red:internet", .gpio = 8, .active_low = 1, },
+	{ .name = "ifx:green:wlan", .gpio = 6, .active_low = 1, },
+	{ .name = "ifx:green:usbpwr", .gpio = 14, .active_low = 1, },
+	{ .name = "ifx:green:usb", .gpio = 19, .active_low = 1, },
+};
+
+static struct gpio_led arv452_gpio_leds[] = {
+	{ .name = "ifx:blue:power", .gpio = 3, .active_low = 1, },
+	{ .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, },
+	{ .name = "ifx:blue:internet", .gpio = 5, .active_low = 1, },
+	{ .name = "ifx:red:power", .gpio = 6, .active_low = 1, },
+	{ .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, },
+	{ .name = "ifx:red:wps", .gpio = 9, .active_low = 1, },
+	{ .name = "ifx:blue:voip", .gpio = 32, .active_low = 1, },
+	{ .name = "ifx:blue:fxs1", .gpio = 33, .active_low = 1, },
+	{ .name = "ifx:blue:fxs2", .gpio = 34, .active_low = 1, },
+	{ .name = "ifx:blue:fxo", .gpio = 35, .active_low = 1, },
+	{ .name = "ifx:blue:voice", .gpio = 36, .active_low = 1, },
+	{ .name = "ifx:blue:usb", .gpio = 37, .active_low = 1, },
+	{ .name = "ifx:blue:wlan", .gpio = 38, .active_low = 1, },
+	{ .name = "ifx:red:internet", .gpio = 41, .active_low = 1, },
+};
+
+static struct gpio_led_platform_data ifxmips_gpio_led_data;
+
+static struct platform_device ifxmips_gpio_leds = {
+	.name = "leds-gpio",
+	.id = -1,
+	.dev = {
+		.platform_data = (void *) &ifxmips_gpio_led_data,
+	}
+};
+#endif
+
+static struct resource dwc_usb_res[] = {
+	{
+		.name = "dwc3884_membase",
+		.flags = IORESOURCE_MEM,
+		.start = 0x1E101000,
+		.end = 0x1E101FFF
+	},
+	{
+		.name = "dwc3884_irq",
+		.flags = IORESOURCE_IRQ,
+		.start = IFXMIPS_USB_INT,
+	}
+};
+
+static struct platform_device dwc_usb =
+{
+	.id = 0,
+	.name = "dwc3884-hcd",
+	.resource = dwc_usb_res,
+	.num_resources = ARRAY_SIZE(dwc_usb_res),
+};
+
+struct platform_device *easy50712_devs[] = {
+	&ifxmips_led, &ifxmips_gpio, &ifxmips_mii,
+	&ifxmips_mtd, &ifxmips_wdt, &ifxmips_gpio_dev, &dwc_usb
+};
+
+struct platform_device *easy4010_devs[] = {
+	&ifxmips_led, &ifxmips_gpio, &ifxmips_mii,
+	&ifxmips_mtd, &ifxmips_wdt, &ifxmips_gpio_dev, &dwc_usb
+};
+
+struct platform_device *arv5419_devs[] = {
+	&ifxmips_gpio, &ifxmips_mii, &ifxmips_mtd,
+	&ifxmips_gpio_dev, &ifxmips_wdt, &dwc_usb,
+#ifdef CONFIG_LEDS_GPIO
+	&ifxmips_gpio_leds,
+#endif
+};
+
+struct platform_device *arv452_devs[] = {
+	&ifxmips_gpio, &ifxmips_mii, &ifxmips_mtd,
+	&ifxmips_gpio_dev, &ifxmips_wdt, &dwc_usb,
+	&ifxmips_ebu,
+#ifdef CONFIG_LEDS_GPIO
+	&ifxmips_gpio_leds,
+#endif
+};
+
+static struct gpio_led easy50712_leds[] = {
+	{ .name = "ifx:green:test0", .gpio = 0,},
+	{ .name = "ifx:green:test1", .gpio = 1,},
+	{ .name = "ifx:green:test2", .gpio = 2,},
+	{ .name = "ifx:green:test3", .gpio = 3,},
+};
+
+static struct gpio_led easy4010_leds[] = {
+	{ .name = "ifx:green:test0", .gpio = 0,},
+	{ .name = "ifx:green:test1", .gpio = 1,},
+	{ .name = "ifx:green:test2", .gpio = 2,},
+	{ .name = "ifx:green:test3", .gpio = 3,},
+};
+
+static struct ifxmips_board boards[] = {
+	{
+		/* infineon eval kit */
+		.type = EASY50712,
+		.name = "EASY50712",
+		.system_type = SYSTEM_DANUBE_CHIPID1,
+		.devs = easy50712_devs,
+		.reset_resource = {.name = "reset", .start = 1, .end = 15,},
+		.gpiodev_resource = { .name = "gpio",
+			.start = (1 << 0) | (1 << 1),
+			.end = (1 << 0) | (1 << 1)},
+		.ifxmips_leds = easy50712_leds,
+	}, {
+		/* infineon eval kit */
+		.type = EASY4010,
+		.name = "EASY4010",
+		.system_type = SYSTEM_TWINPASS_CHIPID,
+		.devs = easy4010_devs,
+		.reset_resource = {.name = "reset", .start = 1, .end = 15},
+		.gpiodev_resource = { .name = "gpio",
+			.start = (1 << 0) | (1 << 1),
+			.end = (1 << 0) | (1 << 1)},
+		.ifxmips_leds = easy4010_leds,
+	}, {
+		/* arcaydian annex-a board used by thompson, airties, ... */
+		.type = ARV4519,
+		.name = "ARV4519",
+		.system_type = SYSTEM_DANUBE_CHIPID2,
+		.devs = arv5419_devs,
+		.reset_resource = {.name = "reset", .start = 1, .end = 14},
+		.pci_external_clock = 1,
+#ifdef CONFIG_LEDS_GPIO
+		.gpio_leds = arv4519_gpio_leds,
+#endif
+	}, {
+		/* arcaydian annex-b board used by airties, arcor */
+		.type = ARV452,
+		.name = "ARV452",
+		.system_type = SYSTEM_DANUBE_CHIPID2,
+		.devs = arv452_devs,
+		.reset_resource = {.name = "reset", .start = 1, .end = 14},
+		.pci_external_clock = 1,
+#ifdef CONFIG_LEDS_GPIO
+		.gpio_leds = arv452_gpio_leds,
+#endif
+	},
+};
+
+const char *get_system_type(void)
+{
+	chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF);
+
+	switch (chiprev) {
+	case SYSTEM_DANUBE_CHIPID1:
+	case SYSTEM_DANUBE_CHIPID2:
+		return SYSTEM_DANUBE;
+
+	case SYSTEM_TWINPASS_CHIPID:
+		return SYSTEM_TWINPASS;
+	}
+
+	return BOARD_SYSTEM_TYPE;
+}
+
+static int __init ifxmips_set_board_type(char *str)
+{
+	str = strchr(str, '=');
+	if (!str)
+		goto out;
+	str++;
+	if (strlen(str) > MAX_BOARD_NAME_LEN)
+		goto out;
+	strncpy(board_name, str, MAX_BOARD_NAME_LEN);
+	printk(KERN_INFO "bootloader told us, that this is a %s board\n",
+		board_name);
+out:
+	return 1;
+}
+__setup("ifxmips_board", ifxmips_set_board_type);
+
+static int __init ifxmips_set_ethaddr(char *str)
+{
+#define IS_HEX(x) \
+	(((x >= '0' && x <= '9') || (x >= 'a' && x <= 'f') \
+		|| (x >= 'A' && x <= 'F')) ? (1) : (0))
+	int i;
+	str = strchr(str, '=');
+	if (!str)
+		goto out;
+	str++;
+	if (strlen(str) != 17)
+		goto out;
+	for (i = 0; i < 6; i++) {
+		if (!IS_HEX(str[3 * i]) || !IS_HEX(str[(3 * i) + 1]))
+			goto out;
+		if ((i != 5) && (str[(3 * i) + 2] != ':'))
+			goto out;
+		ifxmips_ethaddr[i] = simple_strtoul(&str[3 * i], NULL, 16);
+	}
+	if (is_valid_ether_addr(ifxmips_ethaddr))
+		cmdline_mac = 1;
+out:
+	return 1;
+}
+__setup("ethaddr", ifxmips_set_ethaddr);
+
+int ifxmips_find_brn_block(void)
+{
+	unsigned char temp[8];
+	memcpy_fromio(temp,
+		(void *)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000), 8);
+	if (memcmp(temp, "BRN-BOOT", 8) == 0) {
+		if (!cmdline_mac)
+			memcpy_fromio(ifxmips_ethaddr,
+				(void *)KSEG1ADDR(IFXMIPS_FLASH_START +
+					0x800000 - 0x10000 + 0x16), 6);
+		if (is_valid_ether_addr(ifxmips_ethaddr))
+			cmdline_mac = 1;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int ifxmips_has_brn_block(void)
+{
+	return ifxmips_brn;
+}
+EXPORT_SYMBOL(ifxmips_has_brn_block);
+
+struct ifxmips_board *ifxmips_find_board(void)
+{
+	int i;
+	if (!*board_name)
+		return 0;
+	for (i = 0; i < ARRAY_SIZE(boards); i++)
+		if ((boards[i].system_type == chiprev) &&
+		    (!strcmp(boards[i].name, board_name)))
+			return &boards[i];
+	return 0;
+}
+
+int __init ifxmips_init_devices(void)
+{
+	struct ifxmips_board *board;
+
+	chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF);
+	board = ifxmips_find_board();
+	ifxmips_brn = ifxmips_find_brn_block();
+
+	if (!cmdline_mac)
+		random_ether_addr(ifxmips_ethaddr);
+
+	if (!board) {
+		switch (chiprev) {
+		case SYSTEM_DANUBE_CHIPID1:
+		case SYSTEM_DANUBE_CHIPID2:
+		default:
+			board = &boards[0];
+			break;
+		case SYSTEM_TWINPASS_CHIPID:
+			board = &boards[1];
+			break;
+		}
+	}
+
+	switch (board->type) {
+	case EASY50712:
+		board->num_devs = ARRAY_SIZE(easy50712_devs);
+		ifxmips_led_data.num_leds = ARRAY_SIZE(easy50712_leds);
+		break;
+	case EASY4010:
+		board->num_devs = ARRAY_SIZE(easy4010_devs);
+		ifxmips_led_data.num_leds = ARRAY_SIZE(easy4010_leds);
+		break;
+	case ARV4519:
+		/* set some sane defaults for the gpios */
+		gpio_set_value(3, 0);
+		gpio_set_value(4, 0);
+		gpio_set_value(5, 0);
+		gpio_set_value(6, 0);
+		gpio_set_value(7, 1);
+		gpio_set_value(8, 1);
+		gpio_set_value(19, 0);
+		board->num_devs = ARRAY_SIZE(arv5419_devs);
+#ifdef CONFIG_LEDS_GPIO
+		ifxmips_gpio_led_data.num_leds = ARRAY_SIZE(arv4519_gpio_leds);
+#endif
+		break;
+	case ARV452:
+		/* set some sane defaults for the gpios */
+		board->num_devs = ARRAY_SIZE(arv452_devs);
+		ifxmips_w32(0x8001e7ff, IFXMIPS_EBU_BUSCON1);
+#ifdef CONFIG_LEDS_GPIO
+		ifxmips_gpio_led_data.num_leds = ARRAY_SIZE(arv452_gpio_leds);
+#endif
+		break;
+	}
+#ifdef CONFIG_LEDS_GPIO
+	ifxmips_gpio_led_data.leds = board->gpio_leds;
+#endif
+	ifxmips_led_data.leds = board->ifxmips_leds;
+
+	printk(KERN_INFO "%s: adding %d devs\n",
+		__func__, board->num_devs);
+
+	ifxmips_gpio.resource = &board->reset_resource;
+	ifxmips_gpio_dev.resource = &board->gpiodev_resource;
+	if (board->pci_external_clock)
+		ifxmips_pci_external_clock = 1;
+	if (board->pci_req_mask)
+		ifxmips_pci_req_mask = board->pci_req_mask;
+	printk(KERN_INFO "using board definition %s\n", board->name);
+	return platform_add_devices(board->devs, board->num_devs);
+}
+
+arch_initcall(ifxmips_init_devices);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/cgu.c

@@ -0,0 +1,38 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+#include <linux/errno.h>
+
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <ifxmips.h>
+#include <ifxmips_cgu.h>
+
+void
+cgu_setup_pci_clk(int external_clock)
+{
+	/* set clock to 33Mhz */
+	ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
+		IFXMIPS_CGU_IFCCR);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
+		IFXMIPS_CGU_IFCCR);
+	if (external_clock)
+	{
+		ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
+			IFXMIPS_CGU_IFCCR);
+		ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
+	} else {
+		ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
+			IFXMIPS_CGU_IFCCR);
+		ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
+	}
+}
+
+

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/devices.c

@@ -0,0 +1,33 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mtd/physmap.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/reboot.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+
+/* pci */
+extern int ifxmips_pci_external_clock;
+extern int ifxmips_pci_req_mask;
+
+void __init
+ar9_register_pci(int clock, int irq_mask)
+{
+	ifxmips_pci_external_clock = clock;
+	if(irq_mask)
+		ifxmips_pci_req_mask = irq_mask;
+}

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/devices.h

@@ -0,0 +1,16 @@
+#ifndef _DANUBE_DEVICES_H__
+#define _DANUBE_DEVICES_H__
+
+#include "../common/devices.h"
+
+enum {
+	PCI_CLOCK_INT = 0,
+	PCI_CLOCK_EXT
+};
+
+void __init danube_register_usb(void);
+void __init danube_register_ebu_gpio(struct resource *resource, u32 value);
+void __init danube_register_ethernet(unsigned char *mac);
+void __init danube_register_pci(int clock, int irq_mask);
+
+#endif

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/dma-core.c

@@ -0,0 +1,690 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/stat.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/selection.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/uaccess.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_dma.h>
+#include <ifxmips_pmu.h>
+
+/*25 descriptors for each dma channel,4096/8/20=25.xx*/
+#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
+
+#define MAX_DMA_DEVICE_NUM  6	/*max ports connecting to dma */
+#define MAX_DMA_CHANNEL_NUM 20	/*max dma channels */
+#define DMA_INT_BUDGET      100	/*budget for interrupt handling */
+#define DMA_POLL_COUNTER    4	/*fix me, set the correct counter value here! */
+
+extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
+extern void ifxmips_enable_irq(unsigned int irq_nr);
+extern void ifxmips_disable_irq(unsigned int irq_nr);
+
+u64 *g_desc_list;
+struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
+struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
+
+static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
+	{ "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
+
+struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
+	{"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
+	{"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
+	{"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
+	{"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1},
+	{"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2},
+	{"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2},
+	{"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3},
+	{"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3},
+	{"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0},
+	{"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0},
+	{"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1},
+	{"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1},
+	{"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0},
+	{"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0},
+	{"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0},
+	{"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0},
+	{"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0},
+	{"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0},
+	{"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1},
+	{"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
+};
+
+struct dma_chan_map *chan_map = default_dma_map;
+volatile u32 g_ifxmips_dma_int_status;
+volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */
+
+void do_dma_tasklet(unsigned long);
+DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
+
+u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
+{
+	u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
+
+	*byte_offset = 0;
+
+	return buffer;
+}
+
+void common_buffer_free(u8 *dataptr, void *opt)
+{
+	kfree(dataptr);
+}
+
+void enable_ch_irq(struct dma_channel_info *pCh)
+{
+	int chan_no = (int)(pCh - dma_chan);
+	unsigned long flag;
+
+	local_irq_save(flag);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(0x4a, IFXMIPS_DMA_CIE);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+	local_irq_restore(flag);
+	ifxmips_enable_irq(pCh->irq);
+}
+
+void disable_ch_irq(struct dma_channel_info *pCh)
+{
+	unsigned long flag;
+	int chan_no = (int) (pCh - dma_chan);
+
+	local_irq_save(flag);
+	g_ifxmips_dma_int_status &= ~(1 << chan_no);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(0, IFXMIPS_DMA_CIE);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
+	local_irq_restore(flag);
+	ifxmips_mask_and_ack_irq(pCh->irq);
+}
+
+void open_chan(struct dma_channel_info *pCh)
+{
+	unsigned long flag;
+	int chan_no = (int)(pCh - dma_chan);
+
+	local_irq_save(flag);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
+	if (pCh->dir == IFXMIPS_DMA_RX)
+		enable_ch_irq(pCh);
+	local_irq_restore(flag);
+}
+
+void close_chan(struct dma_channel_info *pCh)
+{
+	unsigned long flag;
+	int chan_no = (int) (pCh - dma_chan);
+
+	local_irq_save(flag);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+	disable_ch_irq(pCh);
+	local_irq_restore(flag);
+}
+
+void reset_chan(struct dma_channel_info *pCh)
+{
+	int chan_no = (int) (pCh - dma_chan);
+
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+}
+
+void rx_chan_intr_handler(int chan_no)
+{
+	struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
+	struct dma_channel_info *pCh = &dma_chan[chan_no];
+	struct rx_desc *rx_desc_p;
+	int tmp;
+	unsigned long flag;
+
+	/*handle command complete interrupt */
+	rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
+	if (rx_desc_p->status.field.OWN == CPU_OWN
+	    && rx_desc_p->status.field.C
+	    && rx_desc_p->status.field.data_length < 1536){
+		/* Every thing is correct, then we inform the upper layer */
+		pDev->current_rx_chan = pCh->rel_chan_no;
+		if (pDev->intr_handler)
+			pDev->intr_handler(pDev, RCV_INT);
+		pCh->weight--;
+	} else {
+		local_irq_save(flag);
+		tmp = ifxmips_r32(IFXMIPS_DMA_CS);
+		ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+		ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+		ifxmips_w32(tmp, IFXMIPS_DMA_CS);
+		g_ifxmips_dma_int_status &= ~(1 << chan_no);
+		local_irq_restore(flag);
+		ifxmips_enable_irq(dma_chan[chan_no].irq);
+	}
+}
+
+inline void tx_chan_intr_handler(int chan_no)
+{
+	struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
+	struct dma_channel_info *pCh = &dma_chan[chan_no];
+	int tmp;
+	unsigned long flag;
+
+	local_irq_save(flag);
+	tmp = ifxmips_r32(IFXMIPS_DMA_CS);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+	ifxmips_w32(tmp, IFXMIPS_DMA_CS);
+	g_ifxmips_dma_int_status &= ~(1 << chan_no);
+	local_irq_restore(flag);
+	pDev->current_tx_chan = pCh->rel_chan_no;
+	if (pDev->intr_handler)
+		pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
+}
+
+void do_dma_tasklet(unsigned long unused)
+{
+	int i;
+	int chan_no = 0;
+	int budget = DMA_INT_BUDGET;
+	int weight = 0;
+	unsigned long flag;
+
+	while (g_ifxmips_dma_int_status) {
+		if (budget-- < 0) {
+			tasklet_schedule(&dma_tasklet);
+			return;
+		}
+		chan_no = -1;
+		weight = 0;
+		for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
+			if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
+				if (dma_chan[i].weight > weight) {
+					chan_no = i;
+					weight = dma_chan[chan_no].weight;
+				}
+			}
+		}
+
+		if (chan_no >= 0) {
+			if (chan_map[chan_no].dir == IFXMIPS_DMA_RX)
+				rx_chan_intr_handler(chan_no);
+			else
+				tx_chan_intr_handler(chan_no);
+		} else {
+			for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+				dma_chan[i].weight = dma_chan[i].default_weight;
+		}
+	}
+
+	local_irq_save(flag);
+	g_ifxmips_dma_in_process = 0;
+	if (g_ifxmips_dma_int_status) {
+		g_ifxmips_dma_in_process = 1;
+		tasklet_schedule(&dma_tasklet);
+	}
+	local_irq_restore(flag);
+}
+
+irqreturn_t dma_interrupt(int irq, void *dev_id)
+{
+	struct dma_channel_info *pCh;
+	int chan_no = 0;
+	int tmp;
+
+	pCh = (struct dma_channel_info *)dev_id;
+	chan_no = (int)(pCh - dma_chan);
+	if (chan_no < 0 || chan_no > 19)
+		BUG();
+
+	tmp = ifxmips_r32(IFXMIPS_DMA_IRNEN);
+	ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
+	g_ifxmips_dma_int_status |= 1 << chan_no;
+	ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN);
+	ifxmips_mask_and_ack_irq(irq);
+
+	if (!g_ifxmips_dma_in_process) {
+		g_ifxmips_dma_in_process = 1;
+		tasklet_schedule(&dma_tasklet);
+	}
+
+	return IRQ_HANDLED;
+}
+
+struct dma_device_info *dma_device_reserve(char *dev_name)
+{
+	int i;
+
+	for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
+		if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
+			if (dma_devs[i].reserved)
+				return NULL;
+			dma_devs[i].reserved = 1;
+			break;
+		}
+	}
+
+	return &dma_devs[i];
+}
+EXPORT_SYMBOL(dma_device_reserve);
+
+void dma_device_release(struct dma_device_info *dev)
+{
+	dev->reserved = 0;
+}
+EXPORT_SYMBOL(dma_device_release);
+
+void dma_device_register(struct dma_device_info *dev)
+{
+	int i, j;
+	int chan_no = 0;
+	u8 *buffer;
+	int byte_offset;
+	unsigned long flag;
+	struct dma_device_info *pDev;
+	struct dma_channel_info *pCh;
+	struct rx_desc *rx_desc_p;
+	struct tx_desc *tx_desc_p;
+
+	for (i = 0; i < dev->max_tx_chan_num; i++) {
+		pCh = dev->tx_chan[i];
+		if (pCh->control == IFXMIPS_DMA_CH_ON) {
+			chan_no = (int)(pCh - dma_chan);
+			for (j = 0; j < pCh->desc_len; j++) {
+				tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
+				memset(tx_desc_p, 0, sizeof(struct tx_desc));
+			}
+			local_irq_save(flag);
+			ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+			/* check if the descriptor length is changed */
+			if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+				ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+			while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2)
+				;
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+			ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /* reset and enable channel,enable channel later */
+			local_irq_restore(flag);
+		}
+	}
+
+	for (i = 0; i < dev->max_rx_chan_num; i++) {
+		pCh = dev->rx_chan[i];
+		if (pCh->control == IFXMIPS_DMA_CH_ON) {
+			chan_no = (int)(pCh - dma_chan);
+
+			for (j = 0; j < pCh->desc_len; j++) {
+				rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
+				pDev = (struct dma_device_info *)(pCh->dma_dev);
+				buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
+				if (!buffer)
+					break;
+
+				dma_cache_inv((unsigned long) buffer, pCh->packet_size);
+
+				rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
+				rx_desc_p->status.word = 0;
+				rx_desc_p->status.field.byte_offset = byte_offset;
+				rx_desc_p->status.field.OWN = DMA_OWN;
+				rx_desc_p->status.field.data_length = pCh->packet_size;
+			}
+
+			local_irq_save(flag);
+			ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+			/* check if the descriptor length is changed */
+			if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+				ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+			while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2)
+				;
+			ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /* fix me, should enable all the interrupts here? */
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+			ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL);
+			local_irq_restore(flag);
+			ifxmips_enable_irq(dma_chan[chan_no].irq);
+		}
+	}
+}
+EXPORT_SYMBOL(dma_device_register);
+
+void dma_device_unregister(struct dma_device_info *dev)
+{
+	int i, j;
+	int chan_no;
+	struct dma_channel_info *pCh;
+	struct rx_desc *rx_desc_p;
+	struct tx_desc *tx_desc_p;
+	unsigned long flag;
+
+	for (i = 0; i < dev->max_tx_chan_num; i++) {
+		pCh = dev->tx_chan[i];
+		if (pCh->control == IFXMIPS_DMA_CH_ON) {
+			chan_no = (int)(dev->tx_chan[i] - dma_chan);
+			local_irq_save(flag);
+			ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+			pCh->curr_desc = 0;
+			pCh->prev_desc = 0;
+			pCh->control = IFXMIPS_DMA_CH_OFF;
+			ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1)
+				;
+			local_irq_restore(flag);
+
+			for (j = 0; j < pCh->desc_len; j++) {
+				tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
+				if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
+						|| (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
+					dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
+				}
+				tx_desc_p->status.field.OWN = CPU_OWN;
+				memset(tx_desc_p, 0, sizeof(struct tx_desc));
+			}
+			/* TODO should free buffer that is not transferred by dma */
+		}
+	}
+
+	for (i = 0; i < dev->max_rx_chan_num; i++) {
+		pCh = dev->rx_chan[i];
+		chan_no = (int)(dev->rx_chan[i] - dma_chan);
+		ifxmips_disable_irq(pCh->irq);
+
+		local_irq_save(flag);
+		g_ifxmips_dma_int_status &= ~(1 << chan_no);
+		pCh->curr_desc = 0;
+		pCh->prev_desc = 0;
+		pCh->control = IFXMIPS_DMA_CH_OFF;
+
+		ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+		ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */
+		ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */
+		ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+		while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1)
+			;
+
+		local_irq_restore(flag);
+		for (j = 0; j < pCh->desc_len; j++) {
+			rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
+			if ((rx_desc_p->status.field.OWN == CPU_OWN
+			     && rx_desc_p->status.field.C)
+			    || (rx_desc_p->status.field.OWN == DMA_OWN
+				&& rx_desc_p->status.field.data_length > 0)) {
+				dev->buffer_free((u8 *)
+						 __va(rx_desc_p->Data_Pointer),
+						 (void *) pCh->opt[j]);
+			}
+		}
+	}
+}
+EXPORT_SYMBOL(dma_device_unregister);
+
+int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
+{
+	u8 *buf;
+	int len;
+	int byte_offset = 0;
+	void *p = NULL;
+	struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
+	struct rx_desc *rx_desc_p;
+
+	/* get the rx data first */
+	rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
+	if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
+		return 0;
+
+	buf = (u8 *) __va(rx_desc_p->Data_Pointer);
+	*(u32 *)dataptr = (u32)buf;
+	len = rx_desc_p->status.field.data_length;
+
+	if (opt)
+		*(int *)opt = (int)pCh->opt[pCh->curr_desc];
+
+	/* replace with a new allocated buffer */
+	buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
+
+	if (buf) {
+		dma_cache_inv((unsigned long) buf, pCh->packet_size);
+		pCh->opt[pCh->curr_desc] = p;
+		wmb();
+
+		rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
+		rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
+		wmb();
+	} else {
+		*(u32 *) dataptr = 0;
+		if (opt)
+			*(int *) opt = 0;
+		len = 0;
+	}
+
+	/* increase the curr_desc pointer */
+	pCh->curr_desc++;
+	if (pCh->curr_desc == pCh->desc_len)
+		pCh->curr_desc = 0;
+
+	return len;
+}
+EXPORT_SYMBOL(dma_device_read);
+
+int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
+{
+	unsigned long flag;
+	u32 tmp, byte_offset;
+	struct dma_channel_info *pCh;
+	int chan_no;
+	struct tx_desc *tx_desc_p;
+	local_irq_save(flag);
+
+	pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
+	chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
+
+	tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
+	while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
+		dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
+		memset(tx_desc_p, 0, sizeof(struct tx_desc));
+		pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
+		tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
+	}
+	tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
+	/* Check whether this descriptor is available */
+	if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
+		/* if not, the tell the upper layer device */
+		dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
+		local_irq_restore(flag);
+		printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
+
+		return 0;
+	}
+	pCh->opt[pCh->curr_desc] = opt;
+	/* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
+	byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
+	dma_cache_wback((unsigned long) dataptr, len);
+	wmb();
+	tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
+	wmb();
+	tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
+	wmb();
+
+	pCh->curr_desc++;
+	if (pCh->curr_desc == pCh->desc_len)
+		pCh->curr_desc = 0;
+
+	/*Check whether this descriptor is available */
+	tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
+	if (tx_desc_p->status.field.OWN == DMA_OWN) {
+		/*if not , the tell the upper layer device */
+		dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
+	}
+
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL);
+
+	if (!(tmp & 1))
+		pCh->open(pCh);
+
+	local_irq_restore(flag);
+
+	return len;
+}
+EXPORT_SYMBOL(dma_device_write);
+
+int map_dma_chan(struct dma_chan_map *map)
+{
+	int i, j;
+	int result;
+
+	for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
+		strcpy(dma_devs[i].device_name, global_device_name[i]);
+
+	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
+		dma_chan[i].irq = map[i].irq;
+		result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
+		if (result) {
+			printk(KERN_WARNING "error, cannot get dma_irq!\n");
+			free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
+
+			return -EFAULT;
+		}
+	}
+
+	for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
+		dma_devs[i].num_tx_chan = 0;	/*set default tx channel number to be one */
+		dma_devs[i].num_rx_chan = 0;	/*set default rx channel number to be one */
+		dma_devs[i].max_rx_chan_num = 0;
+		dma_devs[i].max_tx_chan_num = 0;
+		dma_devs[i].buffer_alloc = &common_buffer_alloc;
+		dma_devs[i].buffer_free = &common_buffer_free;
+		dma_devs[i].intr_handler = NULL;
+		dma_devs[i].tx_burst_len = 4;
+		dma_devs[i].rx_burst_len = 4;
+		if (i == 0) {
+			ifxmips_w32(0, IFXMIPS_DMA_PS);
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL);	/*enable dma drop */
+		}
+
+		if (i == 1) {
+			ifxmips_w32(1, IFXMIPS_DMA_PS);
+			ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL);	/*deu port setting */
+		}
+
+		for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
+			dma_chan[j].byte_offset = 0;
+			dma_chan[j].open = &open_chan;
+			dma_chan[j].close = &close_chan;
+			dma_chan[j].reset = &reset_chan;
+			dma_chan[j].enable_irq = &enable_ch_irq;
+			dma_chan[j].disable_irq = &disable_ch_irq;
+			dma_chan[j].rel_chan_no = map[j].rel_chan_no;
+			dma_chan[j].control = IFXMIPS_DMA_CH_OFF;
+			dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT;
+			dma_chan[j].weight = dma_chan[j].default_weight;
+			dma_chan[j].curr_desc = 0;
+			dma_chan[j].prev_desc = 0;
+		}
+
+		for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
+			if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
+				if (map[j].dir == IFXMIPS_DMA_RX) {
+					dma_chan[j].dir = IFXMIPS_DMA_RX;
+					dma_devs[i].max_rx_chan_num++;
+					dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
+					dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
+					dma_chan[j].dma_dev = (void *)&dma_devs[i];
+				} else if (map[j].dir == IFXMIPS_DMA_TX) {
+					/*TX direction */
+					dma_chan[j].dir = IFXMIPS_DMA_TX;
+					dma_devs[i].max_tx_chan_num++;
+					dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
+					dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
+					dma_chan[j].dma_dev = (void *)&dma_devs[i];
+				} else {
+					printk(KERN_WARNING "WRONG DMA MAP!\n");
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+void dma_chip_init(void)
+{
+	int i;
+
+	/* enable DMA from PMU */
+	ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
+
+	/* reset DMA */
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
+
+	/* disable all interrupts */
+	ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
+
+	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
+		ifxmips_w32(i, IFXMIPS_DMA_CS);
+		ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL);
+		ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL);
+		ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
+	}
+}
+
+int ifxmips_dma_init(void)
+{
+	int i;
+
+	dma_chip_init();
+	if (map_dma_chan(default_dma_map))
+		BUG();
+
+	g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
+
+	if (g_desc_list == NULL) {
+		printk(KERN_WARNING "no memory for desriptor\n");
+		return -ENOMEM;
+	}
+
+	memset(g_desc_list, 0, PAGE_SIZE);
+
+	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
+		dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8;
+		dma_chan[i].curr_desc = 0;
+		dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
+
+		ifxmips_w32(i, IFXMIPS_DMA_CS);
+		ifxmips_w32((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
+		ifxmips_w32(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
+	}
+
+	return 0;
+}
+
+arch_initcall(ifxmips_dma_init);
+
+void dma_cleanup(void)
+{
+	int i;
+
+	free_page(KSEG0ADDR((unsigned long) g_desc_list));
+	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+		free_irq(dma_chan[i].irq, (void  *)&dma_interrupt);
+}
+
+MODULE_LICENSE("GPL");

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/irq.c

@@ -0,0 +1,233 @@
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+
+void
+ifxmips_disable_irq(unsigned int irq_nr)
+{
+	int i;
+	u32 *ier = IFXMIPS_ICU_IM0_IER;
+
+	irq_nr -= INT_NUM_IRQ0;
+	for (i = 0; i <= 4; i++)
+	{
+		if (irq_nr < INT_NUM_IM_OFFSET)
+		{
+			ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
+			return;
+		}
+		ier += IFXMIPS_ICU_OFFSET;
+		irq_nr -= INT_NUM_IM_OFFSET;
+	}
+}
+EXPORT_SYMBOL(ifxmips_disable_irq);
+
+void
+ifxmips_mask_and_ack_irq(unsigned int irq_nr)
+{
+	int i;
+	u32 *ier = IFXMIPS_ICU_IM0_IER;
+	u32 *isr = IFXMIPS_ICU_IM0_ISR;
+
+	irq_nr -= INT_NUM_IRQ0;
+	for (i = 0; i <= 4; i++)
+	{
+		if (irq_nr < INT_NUM_IM_OFFSET)
+		{
+			ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
+			ifxmips_w32((1 << irq_nr), isr);
+			return;
+		}
+		ier += IFXMIPS_ICU_OFFSET;
+		isr += IFXMIPS_ICU_OFFSET;
+		irq_nr -= INT_NUM_IM_OFFSET;
+	}
+}
+EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
+
+void
+ifxmips_enable_irq(unsigned int irq_nr)
+{
+	int i;
+	u32 *ier = IFXMIPS_ICU_IM0_IER;
+
+	irq_nr -= INT_NUM_IRQ0;
+	for (i = 0; i <= 4; i++)
+	{
+		if (irq_nr < INT_NUM_IM_OFFSET)
+		{
+			ifxmips_w32(ifxmips_r32(ier) | (1 << irq_nr), ier);
+			return;
+		}
+		ier += IFXMIPS_ICU_OFFSET;
+		irq_nr -= INT_NUM_IM_OFFSET;
+	}
+}
+EXPORT_SYMBOL(ifxmips_enable_irq);
+
+static unsigned int
+ifxmips_startup_irq(unsigned int irq)
+{
+	ifxmips_enable_irq(irq);
+	return 0;
+}
+
+static void
+ifxmips_end_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+		ifxmips_enable_irq(irq);
+}
+
+static struct irq_chip
+ifxmips_irq_type = {
+	"ifxmips",
+	.startup = ifxmips_startup_irq,
+	.enable = ifxmips_enable_irq,
+	.disable = ifxmips_disable_irq,
+	.unmask = ifxmips_enable_irq,
+	.ack = ifxmips_end_irq,
+	.mask = ifxmips_disable_irq,
+	.mask_ack = ifxmips_mask_and_ack_irq,
+	.end = ifxmips_end_irq,
+};
+
+/* silicon bug causes only the msb set to 1 to be valid. all
+   other bits might be bogus */
+static inline int
+ls1bit32(unsigned long x)
+{
+	__asm__ (
+		".set push \n"
+		".set mips32 \n"
+		"clz %0, %1 \n"
+		".set pop \n"
+		: "=r" (x)
+		: "r" (x));
+	return 31 - x;
+}
+
+static void
+ifxmips_hw_irqdispatch(int module)
+{
+	u32 irq;
+
+	irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
+	if (irq == 0)
+		return;
+
+	/* we need to do this due to a silicon bug */
+	irq = ls1bit32(irq);
+	do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
+
+	if ((irq == 22) && (module == 0))
+		ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
+			IFXMIPS_EBU_PCC_ISTAT);
+}
+
+#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
+#define DEFINE_HWx_IRQDISPATCH(x) \
+static void ifxmips_hw ## x ## _irqdispatch(void)\
+{\
+	ifxmips_hw_irqdispatch(x); \
+}
+static void ifxmips_hw5_irqdispatch(void)
+{
+	do_IRQ(MIPS_CPU_TIMER_IRQ);
+}
+DEFINE_HWx_IRQDISPATCH(0)
+DEFINE_HWx_IRQDISPATCH(1)
+DEFINE_HWx_IRQDISPATCH(2)
+DEFINE_HWx_IRQDISPATCH(3)
+DEFINE_HWx_IRQDISPATCH(4)
+/*DEFINE_HWx_IRQDISPATCH(5)*/
+#endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
+
+asmlinkage void
+plat_irq_dispatch(void)
+{
+	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+	unsigned int i;
+
+	if (pending & CAUSEF_IP7)
+	{
+		do_IRQ(MIPS_CPU_TIMER_IRQ);
+		goto out;
+	} else {
+		for (i = 0; i < 5; i++)
+		{
+			if (pending & (CAUSEF_IP2 << i))
+			{
+				ifxmips_hw_irqdispatch(i);
+				goto out;
+			}
+		}
+	}
+	printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
+
+out:
+	return;
+}
+
+static struct irqaction
+cascade = {
+	.handler = no_action,
+	.flags = IRQF_DISABLED,
+	.name = "cascade",
+};
+
+void __init
+arch_init_irq(void)
+{
+	int i;
+
+	for (i = 0; i < 5; i++)
+		ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
+
+	mips_cpu_irq_init();
+
+	for (i = 2; i <= 6; i++)
+		setup_irq(i, &cascade);
+
+#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
+	if (cpu_has_vint) {
+		printk(KERN_INFO "Setting up vectored interrupts\n");
+		set_vi_handler(2, ifxmips_hw0_irqdispatch);
+		set_vi_handler(3, ifxmips_hw1_irqdispatch);
+		set_vi_handler(4, ifxmips_hw2_irqdispatch);
+		set_vi_handler(5, ifxmips_hw3_irqdispatch);
+		set_vi_handler(6, ifxmips_hw4_irqdispatch);
+		set_vi_handler(7, ifxmips_hw5_irqdispatch);
+	}
+#endif
+
+	for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
+		set_irq_chip_and_handler(i, &ifxmips_irq_type,
+			handle_level_irq);
+
+	#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
+	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
+		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+	#else
+	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
+		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+	#endif
+}
+
+void __cpuinit
+arch_fixup_c0_irqs(void)
+{
+	/* FIXME: check for CPUID and only do fix for specific chips/versions */
+	cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+	cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
+}

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/mach-arv452.c

@@ -0,0 +1,170 @@
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+
+#include <machine.h>
+#include <ifxmips_prom.h>
+
+#include "arcaydian.h"
+#include "devices.h"
+
+#define ARV452_EBU_GPIO_START	0x14000000
+#define ARV452_EBU_GPIO_SIZE	0x00001000
+
+#define ARV452_GPIO_BUTTON_RESET		14
+#define ARV452_BUTTONS_POLL_INTERVAL	20
+
+#define ARV452_LATCH_SWITCH				(1 << 10)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition arv452_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x20000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x20000,
+		.size	= 0x0,
+	},
+	{
+		.name	= "kernel",
+		.offset	= 0x0,
+		.size	= 0x0,
+	},
+	{
+		.name	= "rootfs",
+		.offset	= 0x0,
+		.size	= 0x0,
+	},
+	{
+		.name	= "board_config",
+		.offset	= 0x3f0000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "openwrt",
+		.offset	= 0x0,
+		.size	= 0x0,
+	},
+};
+#endif
+
+static struct physmap_flash_data arv452_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+	.nr_parts	= ARRAY_SIZE(arv452_partitions),
+	.parts		= arv452_partitions,
+#endif
+};
+
+static struct gpio_led
+arv452_leds_gpio[] __initdata = {
+/*
+	{ .name = "ifx0", .gpio = 0, .active_low = 1, },
+	{ .name = "ifx1", .gpio = 1, .active_low = 1, },
+	{ .name = "ifx2", .gpio = 2, .active_low = 1, },
+*/
+	{ .name = "ifx:blue:power", .gpio = 3, .active_low = 1, },
+	{ .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, },
+	{ .name = "ifx:blue:internet", .gpio = 5, .active_low = 1, },
+	{ .name = "ifx:red:power", .gpio = 6, .active_low = 1, },
+	{ .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, },
+	{ .name = "ifx:red:wps", .gpio = 9, .active_low = 1, },
+/*
+	{ .name = "ifx10", .gpio = 10, .active_low = 1, },
+	{ .name = "ifx11", .gpio = 11, .active_low = 1, },
+	{ .name = "ifx12", .gpio = 12, .active_low = 1, },
+	{ .name = "ifx13", .gpio = 13, .active_low = 1, },
+	{ .name = "ifx14", .gpio = 14, .active_low = 1, },
+	{ .name = "ifx15", .gpio = 15, .active_low = 1, },
+	{ .name = "ifx16", .gpio = 16, .active_low = 1, },
+	{ .name = "ifx17", .gpio = 17, .active_low = 1, },
+	{ .name = "ifx18", .gpio = 18, .active_low = 1, },
+	{ .name = "ifx19", .gpio = 19, .active_low = 1, },
+	{ .name = "ifx20", .gpio = 20, .active_low = 1, },
+	{ .name = "ifx21", .gpio = 21, .active_low = 1, },
+	{ .name = "ifx22", .gpio = 22, .active_low = 1, },
+	{ .name = "ifx23", .gpio = 23, .active_low = 1, },
+	{ .name = "ifx24", .gpio = 24, .active_low = 1, },
+	{ .name = "ifx25", .gpio = 25, .active_low = 1, },
+	{ .name = "ifx26", .gpio = 26, .active_low = 1, },
+	{ .name = "ifx27", .gpio = 27, .active_low = 1, },
+	{ .name = "ifx28", .gpio = 28, .active_low = 1, },
+	{ .name = "ifx29", .gpio = 29, .active_low = 1, },
+	{ .name = "ifx30", .gpio = 30, .active_low = 1, },
+	{ .name = "ifx31", .gpio = 31, .active_low = 1, },
+*/
+	{ .name = "ifx:blue:voip", .gpio = 32, .active_low = 1, },
+	{ .name = "ifx:blue:fxs1", .gpio = 33, .active_low = 1, },
+	{ .name = "ifx:blue:fxs2", .gpio = 34, .active_low = 1, },
+	{ .name = "ifx:blue:fxo", .gpio = 35, .active_low = 1, },
+	{ .name = "ifx:blue:voice", .gpio = 36, .active_low = 1, },
+	{ .name = "ifx:blue:usb", .gpio = 37, .active_low = 1, },
+	{ .name = "ifx:blue:wlan", .gpio = 38, .active_low = 1, },
+/*	{ .name = "ifx39", .gpio = 39, .active_low = 1, },
+	{ .name = "ifx40", .gpio = 40, .active_low = 1, },
+	{ .name = "ifx41", .gpio = 41, .active_low = 1, },
+	{ .name = "ifx42", .gpio = 42, .active_low = 1, },
+	{ .name = "ifx43", .gpio = 43, .active_low = 1, },
+	{ .name = "ifx44", .gpio = 44, .active_low = 1, },
+	{ .name = "ifx45", .gpio = 45, .active_low = 1, },
+	{ .name = "ifx46", .gpio = 46, .active_low = 1, },
+	{ .name = "ifx47", .gpio = 47, .active_low = 1, },
+*/
+};
+
+static struct gpio_button
+arv452_gpio_buttons[] __initdata = {
+	{
+		.desc		= "reset",
+		.type		= EV_KEY,
+		.code		= BTN_0,
+		.threshold	= 3,
+		.gpio		= ARV452_GPIO_BUTTON_RESET,
+		.active_low	= 1,
+	}
+};
+
+static struct resource arv452_ebu_resource =
+{
+	.name	= "ebu-gpio",
+	.start	= ARV452_EBU_GPIO_START,
+	.end	= ARV452_EBU_GPIO_START + ARV452_EBU_GPIO_SIZE - 1,
+	.flags	= IORESOURCE_MEM,
+};
+
+static void __init
+arv452_init(void)
+{
+	unsigned char mac[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	ifxmips_find_brn_mac(mac);
+
+	ifxmips_register_gpio();
+
+	danube_register_ebu_gpio(&arv452_ebu_resource, ARV452_LATCH_SWITCH);
+
+	ifxmips_register_mtd(&arv452_flash_data);
+
+	danube_register_pci(PCI_CLOCK_EXT, 0);
+
+	ifxmips_register_wdt();
+
+	ifxmips_register_gpio_leds(arv452_leds_gpio, ARRAY_SIZE(arv452_leds_gpio));
+
+	danube_register_ethernet(mac);
+
+	danube_register_usb();
+}
+
+MIPS_MACHINE(IFXMIPS_MACH_ARV452,
+			"ARV452",
+			"Airties WAV-281, Arcor A800",
+		     arv452_init);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/ar9/setup.c

@@ -0,0 +1,96 @@
+#include <linux/cpu.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pm.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <ifxmips.h>
+#include <ifxmips_cgu.h>
+
+#define SYSTEM_DANUBE			"Danube"
+#define SYSTEM_DANUBE_CHIPID1	0x00129083
+#define SYSTEM_DANUBE_CHIPID2	0x0012B083
+
+#define SYSTEM_TWINPASS			"Twinpass"
+#define SYSTEM_TWINPASS_CHIPID	0x0012D083
+
+static unsigned int chiprev = 0;
+unsigned char ifxmips_sys_type[IFXMIPS_SYS_TYPE_LEN];
+
+unsigned int
+ifxmips_get_cpu_ver(void)
+{
+	return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0xF0000000) >> 28;
+}
+EXPORT_SYMBOL(ifxmips_get_cpu_ver);
+
+const char*
+get_system_type(void)
+{
+	return ifxmips_sys_type;
+}
+
+static void
+ifxmips_machine_restart(char *command)
+{
+	printk(KERN_NOTICE "System restart\n");
+	local_irq_disable();
+	ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL,
+		IFXMIPS_RCU_RST);
+	for(;;);
+}
+
+static void
+ifxmips_machine_halt(void)
+{
+	printk(KERN_NOTICE "System halted.\n");
+	local_irq_disable();
+	for(;;);
+}
+
+static void
+ifxmips_machine_power_off(void)
+{
+	printk(KERN_NOTICE "Please turn off the power now.\n");
+	local_irq_disable();
+	for(;;);
+}
+
+void __init
+ifxmips_soc_setup(void)
+{
+	char *name = SYSTEM_DANUBE;
+	ioport_resource.start = IOPORT_RESOURCE_START;
+	ioport_resource.end = IOPORT_RESOURCE_END;
+	iomem_resource.start = IOMEM_RESOURCE_START;
+	iomem_resource.end = IOMEM_RESOURCE_END;
+
+	_machine_restart = ifxmips_machine_restart;
+	_machine_halt = ifxmips_machine_halt;
+	pm_power_off = ifxmips_machine_power_off;
+
+	chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF);
+
+	switch (chiprev)
+	{
+	case SYSTEM_DANUBE_CHIPID1:
+	case SYSTEM_DANUBE_CHIPID2:
+		name = SYSTEM_DANUBE;
+		break;
+
+	case SYSTEM_TWINPASS_CHIPID:
+		name = SYSTEM_TWINPASS;
+		break;
+
+	default:
+		printk(KERN_ERR "This is not a danube chiprev : 0x%08X\n", chiprev);
+		BUG();
+		break;
+	}
+	snprintf(ifxmips_sys_type, IFXMIPS_SYS_TYPE_LEN - 1, "%s rev1.%d %dMhz",
+		name, ifxmips_get_cpu_ver(),
+		ifxmips_get_cpu_hz() / 1000000);
+	ifxmips_sys_type[IFXMIPS_SYS_TYPE_LEN - 1] = '\0';
+}

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/common/Makefile

@@ -0,0 +1,2 @@
+obj-y := gpio.o pmu.o prom.o setup.o devices.o
+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/common/devices.c

@@ -0,0 +1,135 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mtd/physmap.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/reboot.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+
+/* gpiodev */
+static struct platform_device ifxmips_gpio_dev =
+{
+	.name			= "GPIODEV",
+	.num_resources	= 1,
+};
+
+void __init
+ifxmips_register_gpio_dev(void)
+{
+	platform_device_register(&ifxmips_gpio_dev);
+}
+
+/* gpio leds */
+#ifdef CONFIG_LEDS_GPIO
+static struct gpio_led_platform_data ifxmips_gpio_led_data;
+
+static struct platform_device ifxmips_gpio_leds =
+{
+	.name = "leds-gpio",
+	.dev = {
+		.platform_data = (void *) &ifxmips_gpio_led_data,
+	}
+};
+
+void __init
+ifxmips_register_gpio_leds(struct gpio_led *leds, int cnt)
+{
+	ifxmips_gpio_led_data.leds = leds;
+	ifxmips_gpio_led_data.num_leds = cnt;
+	platform_device_register(&ifxmips_gpio_leds);
+}
+#endif
+
+/* leds */
+static struct gpio_led_platform_data ifxmips_led_data;
+
+static struct platform_device ifxmips_led =
+{
+	.name = "ifxmips_led",
+	.dev = {
+		.platform_data = (void *) &ifxmips_led_data,
+	}
+};
+
+void __init
+ifxmips_register_leds(struct gpio_led *leds, int cnt)
+{
+	ifxmips_led_data.leds = leds;
+	ifxmips_led_data.num_leds = cnt;
+	platform_device_register(&ifxmips_led);
+}
+
+/* mtd flash */
+static struct resource ifxmips_mtd_resource =
+{
+	.start  = IFXMIPS_FLASH_START,
+	.end    = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1,
+	.flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device ifxmips_mtd =
+{
+	.name			= "ifxmips_mtd",
+	.resource		= &ifxmips_mtd_resource,
+	.num_resources	= 1,
+};
+
+void __init
+ifxmips_register_mtd(struct physmap_flash_data *pdata)
+{
+	ifxmips_mtd.dev.platform_data = pdata;
+	platform_device_register(&ifxmips_mtd);
+}
+
+/* watchdog */
+static struct resource ifxmips_wdt_resource =
+{
+	.start  = IFXMIPS_WDT_BASE_ADDR,
+	.end    = IFXMIPS_WDT_BASE_ADDR + IFXMIPS_WDT_SIZE - 1,
+	.flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device ifxmips_wdt =
+{
+	.name			= "ifxmips_wdt",
+	.resource		= &ifxmips_wdt_resource,
+	.num_resources = 1,
+};
+
+void __init
+ifxmips_register_wdt(void)
+{
+	platform_device_register(&ifxmips_wdt);
+}
+
+/* gpio */
+static struct platform_device ifxmips_gpio0 =
+{
+	.name = "ifxmips_gpio",
+};
+
+static struct platform_device ifxmips_gpio1 =
+{
+	.name = "ifxmips_gpio1",
+};
+
+void __init
+ifxmips_register_gpio(void)
+{
+	platform_device_register(&ifxmips_gpio0);
+	platform_device_register(&ifxmips_gpio1);
+}

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/common/devices.h

@@ -0,0 +1,11 @@
+#ifndef _IFXMIPS_DEVICES_H__
+#define _IFXMIPS_DEVICES_H__
+
+void __init ifxmips_register_gpio_dev(void);
+void __init ifxmips_register_gpio_leds(struct gpio_led *leds, int cnt);
+void __init ifxmips_register_leds(struct gpio_led *leds, int cnt);
+void __init ifxmips_register_mtd(struct physmap_flash_data *pdata);
+void __init ifxmips_register_wdt(void);
+void __init ifxmips_register_gpio(void);
+
+#endif

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/common/early_printk.c

@@ -0,0 +1,56 @@
+#include <linux/init.h>
+#include <linux/cpu.h>
+
+#include <ifxmips.h>
+
+#ifdef CONFIG_IFXMIPS_PROM_ASC0
+#define IFXMIPS_ASC_DIFF	0
+#else
+#define IFXMIPS_ASC_DIFF	IFXMIPS_ASC_BASE_DIFF
+#endif
+
+static char buf[1024];
+
+static inline u32
+asc_r32(unsigned long r)
+{
+	return ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r));
+}
+
+static inline void
+asc_w32(u32 v, unsigned long r)
+{
+	ifxmips_w32(v, (u32 *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r));
+}
+
+void
+prom_putchar(char c)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	while ((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
+
+	if (c == '\n')
+		asc_w32('\r', IFXMIPS_ASC_TBUF);
+	asc_w32(c, IFXMIPS_ASC_TBUF);
+	local_irq_restore(flags);
+}
+
+void
+early_printf(const char *fmt, ...)
+{
+	va_list args;
+	int l;
+	char *p, *buf_end;
+
+	va_start(args, fmt);
+	l = vsprintf(buf, fmt, args);
+	va_end(args);
+	buf_end = buf + l;
+
+	for (p = buf; p < buf_end; p++)
+		prom_putchar(*p);
+}
+
+

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/common/gpio.c

@@ -0,0 +1,345 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2004 btxu Generate from INCA-IP project
+ *   Copyright (C) 2005 Jin-Sze.Sow Comments edited
+ *   Copyright (C) 2006 Huang Xiaogang Modification & verification on Danube chip
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/ioctl.h>
+#include <linux/timer.h>
+#include <linux/module.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/kobject.h>
+#include <linux/workqueue.h>
+#include <linux/skbuff.h>
+#include <linux/netlink.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/semaphore.h>
+#include <linux/gpio.h>
+
+#include <net/sock.h>
+
+#include <ifxmips.h>
+
+#define MAX_PORTS			2
+#define PINS_PER_PORT		16
+
+#define IFXMIPS_GPIO_SANITY		{if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
+
+#define GPIO_TO_PORT(x) ((x > 15) ? (1) : (0))
+#define GPIO_TO_GPIO(x) ((x > 15) ? (x - 16) : (x))
+
+int
+ifxmips_port_reserve_pin(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	printk(KERN_INFO "%s : call to obseleted function\n", __func__);
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_reserve_pin);
+
+int
+ifxmips_port_free_pin(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	printk(KERN_INFO "%s : call to obseleted function\n", __func__);
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_free_pin);
+
+int
+ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin),
+		IFXMIPS_GPIO_P0_OD + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_open_drain);
+
+int
+ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin),
+		IFXMIPS_GPIO_P0_OD + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_clear_open_drain);
+
+int
+ifxmips_port_set_pudsel(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin),
+		IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_pudsel);
+
+int
+ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin),
+		IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_clear_pudsel);
+
+int
+ifxmips_port_set_puden(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin),
+		IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_puden);
+
+int
+ifxmips_port_clear_puden(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin),
+		IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_clear_puden);
+
+int
+ifxmips_port_set_stoff(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin),
+		IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_stoff);
+
+int
+ifxmips_port_clear_stoff(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin),
+		IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_clear_stoff);
+
+int
+ifxmips_port_set_dir_out(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin),
+		IFXMIPS_GPIO_P0_DIR + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_dir_out);
+
+int
+ifxmips_port_set_dir_in(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin),
+		IFXMIPS_GPIO_P0_DIR + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_dir_in);
+
+int
+ifxmips_port_set_output(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin),
+		IFXMIPS_GPIO_P0_OUT + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_output);
+
+int
+ifxmips_port_clear_output(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin),
+		IFXMIPS_GPIO_P0_OUT + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_clear_output);
+
+int
+ifxmips_port_get_input(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
+		return 0;
+	else
+		return 1;
+}
+EXPORT_SYMBOL(ifxmips_port_get_input);
+
+int
+ifxmips_port_set_altsel0(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin),
+		IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_altsel0);
+
+int
+ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin),
+		IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_clear_altsel0);
+
+int
+ifxmips_port_set_altsel1(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin),
+		IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_set_altsel1);
+
+int
+ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
+{
+	IFXMIPS_GPIO_SANITY;
+	ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin),
+		IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_port_clear_altsel1);
+
+static void
+ifxmips_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
+{
+	int port = GPIO_TO_PORT(offset);
+	int gpio = GPIO_TO_GPIO(offset);
+	if(value)
+		ifxmips_port_set_output(port, gpio);
+	else
+		ifxmips_port_clear_output(port, gpio);
+}
+
+static int
+ifxmips_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+	int port = GPIO_TO_PORT(offset);
+	int gpio = GPIO_TO_GPIO(offset);
+	return ifxmips_port_get_input(port, gpio);
+}
+
+static int
+ifxmips_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
+{
+	int port = GPIO_TO_PORT(offset);
+	int gpio = GPIO_TO_GPIO(offset);
+	ifxmips_port_set_open_drain(port, gpio);
+	ifxmips_port_clear_altsel0(port, gpio);
+	ifxmips_port_clear_altsel1(port, gpio);
+	ifxmips_port_set_dir_in(port, gpio);
+	return 0;
+}
+
+static int
+ifxmips_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
+{
+	int port = GPIO_TO_PORT(offset);
+	int gpio = GPIO_TO_GPIO(offset);
+	ifxmips_port_clear_open_drain(port, gpio);
+	ifxmips_port_clear_altsel0(port, gpio);
+	ifxmips_port_clear_altsel1(port, gpio);
+	ifxmips_port_set_dir_out(port, gpio);
+	ifxmips_gpio_set(chip, offset, value);
+	return 0;
+}
+
+int
+gpio_to_irq(unsigned int gpio)
+{
+	return -EINVAL;
+}
+EXPORT_SYMBOL(gpio_to_irq);
+
+struct gpio_chip
+ifxmips_gpio_chip =
+{
+	.label = "ifxmips-gpio",
+	.direction_input = ifxmips_gpio_direction_input,
+	.direction_output = ifxmips_gpio_direction_output,
+	.get = ifxmips_gpio_get,
+	.set = ifxmips_gpio_set,
+	.base = 0,
+	.ngpio = 32,
+};
+
+static int
+ifxmips_gpio_probe(struct platform_device *dev)
+{
+	gpiochip_add(&ifxmips_gpio_chip);
+	return 0;
+}
+
+static int
+ifxmips_gpio_remove(struct platform_device *pdev)
+{
+	gpiochip_remove(&ifxmips_gpio_chip);
+	return 0;
+}
+
+static struct platform_driver
+ifxmips_gpio_driver = {
+	.probe = ifxmips_gpio_probe,
+	.remove = ifxmips_gpio_remove,
+	.driver = {
+		.name = "ifxmips_gpio",
+		.owner = THIS_MODULE,
+	},
+};
+
+int __init
+ifxmips_gpio_init(void)
+{
+	int ret = platform_driver_register(&ifxmips_gpio_driver);
+	if (ret)
+		printk(KERN_INFO "ifxmips_gpio : Error registering platfom driver!");
+	return ret;
+}
+
+void __exit
+ifxmips_gpio_exit(void)
+{
+	platform_driver_unregister(&ifxmips_gpio_driver);
+}
+
+module_init(ifxmips_gpio_init);
+module_exit(ifxmips_gpio_exit);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/common/pmu.c

@@ -0,0 +1,25 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+
+#include <ifxmips.h>
+
+void
+ifxmips_pmu_enable(unsigned int module)
+{
+	int err = 1000000;
+
+	ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
+	while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module));
+
+	if (!err)
+		panic("activating PMU module failed!");
+}
+EXPORT_SYMBOL(ifxmips_pmu_enable);
+
+void
+ifxmips_pmu_disable(unsigned int module)
+{
+	ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
+}
+EXPORT_SYMBOL(ifxmips_pmu_disable);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/common/prom.c

@@ -0,0 +1,143 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/bootmem.h>
+#include <linux/etherdevice.h>
+
+#include <asm/bootinfo.h>
+#include <machine.h>
+
+#include <ifxmips.h>
+#include <ifxmips_prom.h>
+
+/* for voice cpu (MIPS24K) */
+unsigned int *prom_cp1_base;
+unsigned int prom_cp1_size;
+
+/* for Multithreading (APRP) on MIPS34K */
+unsigned long physical_memsize;
+
+void
+prom_free_prom_memory(void)
+{
+}
+
+unsigned int*
+prom_get_cp1_base(void)
+{
+	return prom_cp1_base;
+}
+EXPORT_SYMBOL(prom_get_cp1_base);
+
+unsigned int
+prom_get_cp1_size(void)
+{
+	/* return size im MB */
+	return prom_cp1_size>>20;
+}
+EXPORT_SYMBOL(prom_get_cp1_size);
+
+extern unsigned char ifxmips_ethaddr[6];
+int cmdline_mac = 0;
+
+static int __init
+ifxmips_set_ethaddr(char *str)
+{
+#define IS_HEX(x) \
+	(((x >= '0' && x <= '9') || (x >= 'a' && x <= 'f') \
+		|| (x >= 'A' && x <= 'F')) ? (1) : (0))
+	int i;
+	str = strchr(str, '=');
+	if (!str)
+		goto out;
+	str++;
+	if (strlen(str) != 17)
+		goto out;
+	for (i = 0; i < 6; i++) {
+		if (!IS_HEX(str[3 * i]) || !IS_HEX(str[(3 * i) + 1]))
+			goto out;
+		if ((i != 5) && (str[(3 * i) + 2] != ':'))
+			goto out;
+		ifxmips_ethaddr[i] = simple_strtoul(&str[3 * i], NULL, 16);
+	}
+	if (is_valid_ether_addr(ifxmips_ethaddr))
+		cmdline_mac = 1;
+out:
+	return 1;
+}
+__setup("ethaddr", ifxmips_set_ethaddr);
+
+static void __init prom_detect_machtype(void)
+{
+	mips_machtype = IFXMIPS_MACH_EASY50712;
+}
+
+static void __init prom_init_cmdline(void)
+{
+	int argc = fw_arg0;
+	char **argv = (char **) fw_arg1;
+	char **envp = (char **) fw_arg2;
+
+	int memsize = 16; /* assume 16M as default */
+	int i;
+
+	if (argc)
+	{
+		argv = (char **)KSEG1ADDR((unsigned long)argv);
+		arcs_cmdline[0] = '\0';
+		for (i = 1; i < argc; i++)
+		{
+			char *a = (char *)KSEG1ADDR(argv[i]);
+			if (!argv[i])
+				continue;
+			/* for voice cpu on Twinpass/Danube */
+			if (cpu_data[0].cputype == CPU_24K)
+				if (!strncmp(a, "cp1_size=", 9))
+				{
+					prom_cp1_size = memparse(a + 9, &a);
+					continue;
+				}
+			if (strlen(arcs_cmdline) + strlen(a + 1) >= sizeof(arcs_cmdline))
+			{
+				early_printf("cmdline overflow, skipping: %s\n", a);
+				break;
+			}
+			strcat(arcs_cmdline, a);
+			strcat(arcs_cmdline, " ");
+		}
+		if (!*arcs_cmdline)
+			strcpy(&(arcs_cmdline[0]),
+				"console=ttyS0,115200 rootfstype=squashfs,jffs2");
+	}
+	envp = (char **)KSEG1ADDR((unsigned long)envp);
+	while (*envp)
+	{
+		char *e = (char *)KSEG1ADDR(*envp);
+
+		if (!strncmp(e, "memsize=", 8))
+		{
+			e += 8;
+			memsize = simple_strtoul(e, NULL, 10);
+		}
+		envp++;
+	}
+	memsize *= 1024 * 1024;
+
+	/* only on Twinpass/Danube a second CPU is used for Voice */
+	if ((cpu_data[0].cputype == CPU_24K) && (prom_cp1_size))
+	{
+		memsize -= prom_cp1_size;
+		prom_cp1_base = (unsigned int *)KSEG1ADDR(memsize);
+
+		early_printf("Using %dMB Ram and reserving %dMB for cp1\n",
+			memsize>>20, prom_cp1_size>>20);
+	}
+
+	add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
+}
+
+void __init
+prom_init(void)
+{
+	prom_detect_machtype();
+	prom_init_cmdline();
+}

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/common/setup.c

@@ -0,0 +1,104 @@
+#include <linux/init.h>
+#include <linux/cpu.h>
+
+#include <asm/time.h>
+#include <asm/traps.h>
+#include <asm/irq.h>
+#include <asm/bootinfo.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_pmu.h>
+#include <ifxmips_cgu.h>
+#include <ifxmips_prom.h>
+
+#include <machine.h>
+
+DEFINE_SPINLOCK(ebu_lock);
+EXPORT_SYMBOL_GPL(ebu_lock);
+
+static unsigned int r4k_offset;
+static unsigned int r4k_cur;
+
+static unsigned int ifxmips_ram_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
+#define DDR_HZ ifxmips_ram_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
+
+extern void __init ifxmips_soc_setup(void);
+
+static inline u32
+ifxmips_get_counter_resolution(void)
+{
+	u32 res;
+	__asm__ __volatile__(
+		".set   push\n"
+		".set   mips32r2\n"
+		".set   noreorder\n"
+		"rdhwr  %0, $3\n"
+		"ehb\n"
+		".set pop\n"
+		: "=&r" (res)
+		: /* no input */
+		: "memory");
+	instruction_hazard();
+	return res;
+}
+
+void __init
+plat_time_init(void)
+{
+	mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution();
+	r4k_cur = (read_c0_count() + r4k_offset);
+	write_c0_compare(r4k_cur);
+
+	ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
+	ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC); /* set clock divider to 1 */
+}
+
+void __init
+plat_mem_setup(void)
+{
+	u32 status;
+
+	/* make sure to have no "reverse endian" for user mode! */
+	status = read_c0_status();
+	status &= (~(1<<25));
+	write_c0_status(status);
+
+	/* call the chip specific init code */
+	ifxmips_soc_setup();
+}
+
+
+unsigned int
+ifxmips_get_cpu_hz(void)
+{
+	switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
+	{
+	case 0:
+		return CLOCK_333M;
+	case 4:
+		return DDR_HZ;
+	}
+	return DDR_HZ >> 1;
+}
+EXPORT_SYMBOL(ifxmips_get_cpu_hz);
+
+static int __init
+ifxmips_machine_setup(void)
+{
+	mips_machine_setup();
+	return 0;
+}
+
+arch_initcall(ifxmips_machine_setup);
+
+static void __init
+ifxmips_generic_init(void)
+{
+}
+
+MIPS_MACHINE(IFXMIPS_MACH_GENERIC, "Generic", "Generic Infineon board",
+	ifxmips_generic_init);
+
+__setup("board=", mips_machtype_setup);
+

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/compat/Makefile

@@ -0,0 +1 @@
+obj-y := timer.o cgu.o

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/compat/cgu.c

@@ -0,0 +1,173 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 Xu Liang, infineon
+ *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+#include <linux/errno.h>
+
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <ifxmips.h>
+#include <ifxmips_cgu.h>
+
+static unsigned int cgu_get_pll0_fdiv(void);
+unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
+
+#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
+
+static inline unsigned int get_input_clock(int pll)
+{
+	switch (pll) {
+	case 0:
+		if (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
+			return BASIS_INPUT_CRYSTAL_USB;
+		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			return BASIC_INPUT_CLOCK_FREQUENCY_1;
+		else
+			return BASIC_INPUT_CLOCK_FREQUENCY_2;
+	case 1:
+		if (CGU_PLL1_SRC)
+			return BASIS_INPUT_CRYSTAL_USB;
+		else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			return BASIC_INPUT_CLOCK_FREQUENCY_1;
+		else
+			return BASIC_INPUT_CLOCK_FREQUENCY_2;
+	case 2:
+		switch (CGU_PLL2_SRC) {
+		case 0:
+			return cgu_get_pll0_fdiv();
+		case 1:
+			return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
+				BASIC_INPUT_CLOCK_FREQUENCY_1 :
+				BASIC_INPUT_CLOCK_FREQUENCY_2;
+		case 2:
+			return BASIS_INPUT_CRYSTAL_USB;
+		}
+	default:
+		return 0;
+	}
+}
+
+static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
+{
+	u64 res, clock = get_input_clock(pll);
+
+	res = num * clock;
+	do_div(res, den);
+	return res;
+}
+
+static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = ((N + 1) << 10) + K;
+	unsigned int den = (M + 1) << 10;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = ((N + 1) << 11) + K + 512;
+	unsigned int den = (M + 1) << 11;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
+	unsigned int K)
+{
+	unsigned int num = K >= 512 ?
+		((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
+	unsigned int den = (M + 1) << 12;
+
+	return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
+	unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
+{
+	if (!dsmsel)
+		return mash_dsm(pll, M, N, K);
+	else if (!phase_div_en)
+		return mash_dsm(pll, M, N, K);
+	else
+		return ssff_dsm_2(pll, M, N, K);
+}
+
+static inline unsigned int cgu_get_pll0_fosc(void)
+{
+	if (CGU_PLL0_BYPASS)
+		return get_input_clock(0);
+	else
+		return !CGU_PLL0_CFG_FRAC_EN
+			? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
+				CGU_PLL0_PHASE_DIVIDER_ENABLE)
+			: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
+				CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
+}
+
+static unsigned int cgu_get_pll0_fdiv(void)
+{
+	unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
+	return (cgu_get_pll0_fosc() + (div >> 1)) / div;
+}
+
+unsigned int cgu_get_io_region_clock(void)
+{
+	unsigned int ret = cgu_get_pll0_fosc();
+	switch (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
+	default:
+	case 0:
+		return (ret + 1) / 2;
+	case 1:
+		return (ret * 2 + 2) / 5;
+	case 2:
+		return (ret + 1) / 3;
+	case 3:
+		return (ret + 2) / 4;
+	}
+}
+
+unsigned int cgu_get_fpi_bus_clock(int fpi)
+{
+	unsigned int ret = cgu_get_io_region_clock();
+	if ((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
+		ret >>= 1;
+	return ret;
+}
+EXPORT_SYMBOL(cgu_get_fpi_bus_clock);
+
+unsigned int ifxmips_get_fpi_hz(void)
+{
+	unsigned int ddr_clock = DDR_HZ;
+	if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
+		return ddr_clock >> 1;
+	return ddr_clock;
+}
+EXPORT_SYMBOL(ifxmips_get_fpi_hz);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/compat/timer.c

@@ -0,0 +1,830 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_cgu.h>
+#include <ifxmips_gptu.h>
+#include <ifxmips_pmu.h>
+
+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS	6
+
+#ifdef TIMER1A
+#define FIRST_TIMER			TIMER1A
+#else
+#define FIRST_TIMER			2
+#endif
+
+/*
+ *  GPTC divider is set or not.
+ */
+#define GPTU_CLC_RMC_IS_SET		0
+
+/*
+ *  Timer Interrupt (IRQ)
+ */
+/*  Must be adjusted when ICU driver is available */
+#define TIMER_INTERRUPT			(INT_NUM_IM3_IRL0 + 22)
+
+/*
+ *  Bits Operation
+ */
+#define GET_BITS(x, msb, lsb)		\
+	(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
+#define SET_BITS(x, msb, lsb, value)	\
+	(((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
+	(((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
+
+/*
+ *  GPTU Register Mapping
+ */
+#define IFXMIPS_GPTU			(KSEG1 + 0x1E100A00)
+#define IFXMIPS_GPTU_CLC		((volatile u32 *)(IFXMIPS_GPTU + 0x0000))
+#define IFXMIPS_GPTU_ID			((volatile u32 *)(IFXMIPS_GPTU + 0x0008))
+#define IFXMIPS_GPTU_CON(n, X)		((volatile u32 *)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
+#define IFXMIPS_GPTU_RUN(n, X)		((volatile u32 *)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
+#define IFXMIPS_GPTU_RELOAD(n, X)	((volatile u32 *)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
+#define IFXMIPS_GPTU_COUNT(n, X)	((volatile u32 *)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
+#define IFXMIPS_GPTU_IRNEN		((volatile u32 *)(IFXMIPS_GPTU + 0x00F4))
+#define IFXMIPS_GPTU_IRNICR		((volatile u32 *)(IFXMIPS_GPTU + 0x00F8))
+#define IFXMIPS_GPTU_IRNCR		((volatile u32 *)(IFXMIPS_GPTU + 0x00FC))
+
+/*
+ *  Clock Control Register
+ */
+#define GPTU_CLC_SMC			GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
+#define GPTU_CLC_RMC			GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
+#define GPTU_CLC_FSOE			(*IFXMIPS_GPTU_CLC & (1 << 5))
+#define GPTU_CLC_EDIS			(*IFXMIPS_GPTU_CLC & (1 << 3))
+#define GPTU_CLC_SPEN			(*IFXMIPS_GPTU_CLC & (1 << 2))
+#define GPTU_CLC_DISS			(*IFXMIPS_GPTU_CLC & (1 << 1))
+#define GPTU_CLC_DISR			(*IFXMIPS_GPTU_CLC & (1 << 0))
+
+#define GPTU_CLC_SMC_SET(value)		SET_BITS(0, 23, 16, (value))
+#define GPTU_CLC_RMC_SET(value)		SET_BITS(0, 15, 8, (value))
+#define GPTU_CLC_FSOE_SET(value)	((value) ? (1 << 5) : 0)
+#define GPTU_CLC_SBWE_SET(value)	((value) ? (1 << 4) : 0)
+#define GPTU_CLC_EDIS_SET(value)	((value) ? (1 << 3) : 0)
+#define GPTU_CLC_SPEN_SET(value)	((value) ? (1 << 2) : 0)
+#define GPTU_CLC_DISR_SET(value)	((value) ? (1 << 0) : 0)
+
+/*
+ *  ID Register
+ */
+#define GPTU_ID_ID			GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
+#define GPTU_ID_CFG			GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
+#define GPTU_ID_REV			GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
+
+/*
+ *  Control Register of Timer/Counter nX
+ *    n is the index of block (1 based index)
+ *    X is either A or B
+ */
+#define GPTU_CON_SRC_EG(n, X)		(*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
+#define GPTU_CON_SRC_EXT(n, X)		(*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
+#define GPTU_CON_SYNC(n, X)		(*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
+#define GPTU_CON_EDGE(n, X)		GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
+#define GPTU_CON_INV(n, X)		(*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
+#define GPTU_CON_EXT(n, X)		(*IFXMIPS_GPTU_CON(n, A) & (1 << 4))	/* Timer/Counter B does not have this bit */
+#define GPTU_CON_STP(n, X)		(*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
+#define GPTU_CON_CNT(n, X)		(*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
+#define GPTU_CON_DIR(n, X)		(*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
+#define GPTU_CON_EN(n, X)		(*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
+
+#define GPTU_CON_SRC_EG_SET(value)	((value) ? 0 : (1 << 10))
+#define GPTU_CON_SRC_EXT_SET(value)	((value) ? (1 << 9) : 0)
+#define GPTU_CON_SYNC_SET(value)	((value) ? (1 << 8) : 0)
+#define GPTU_CON_EDGE_SET(value)	SET_BITS(0, 7, 6, (value))
+#define GPTU_CON_INV_SET(value)		((value) ? (1 << 5) : 0)
+#define GPTU_CON_EXT_SET(value)		((value) ? (1 << 4) : 0)
+#define GPTU_CON_STP_SET(value)		((value) ? (1 << 3) : 0)
+#define GPTU_CON_CNT_SET(value)		((value) ? (1 << 2) : 0)
+#define GPTU_CON_DIR_SET(value)		((value) ? (1 << 1) : 0)
+
+#define GPTU_RUN_RL_SET(value)		((value) ? (1 << 2) : 0)
+#define GPTU_RUN_CEN_SET(value)		((value) ? (1 << 1) : 0)
+#define GPTU_RUN_SEN_SET(value)		((value) ? (1 << 0) : 0)
+
+#define GPTU_IRNEN_TC_SET(n, X, value)	((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
+#define GPTU_IRNCR_TC_SET(n, X, value)	((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
+
+#define TIMER_FLAG_MASK_SIZE(x)		(x & 0x0001)
+#define TIMER_FLAG_MASK_TYPE(x)		(x & 0x0002)
+#define TIMER_FLAG_MASK_STOP(x)		(x & 0x0004)
+#define TIMER_FLAG_MASK_DIR(x)		(x & 0x0008)
+#define TIMER_FLAG_NONE_EDGE		0x0000
+#define TIMER_FLAG_MASK_EDGE(x)		(x & 0x0030)
+#define TIMER_FLAG_REAL			0x0000
+#define TIMER_FLAG_INVERT		0x0040
+#define TIMER_FLAG_MASK_INVERT(x)	(x & 0x0040)
+#define TIMER_FLAG_MASK_TRIGGER(x)	(x & 0x0070)
+#define TIMER_FLAG_MASK_SYNC(x)		(x & 0x0080)
+#define TIMER_FLAG_CALLBACK_IN_HB	0x0200
+#define TIMER_FLAG_MASK_HANDLE(x)	(x & 0x0300)
+#define TIMER_FLAG_MASK_SRC(x)		(x & 0x1000)
+
+struct timer_dev_timer {
+	unsigned int f_irq_on;
+	unsigned int irq;
+	unsigned int flag;
+	unsigned long arg1;
+	unsigned long arg2;
+};
+
+struct timer_dev {
+	struct mutex gptu_mutex;
+	unsigned int number_of_timers;
+	unsigned int occupation;
+	unsigned int f_gptu_on;
+	struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
+};
+
+static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+static int gptu_open(struct inode *, struct file *);
+static int gptu_release(struct inode *, struct file *);
+
+static struct file_operations gptu_fops = {
+	.owner = THIS_MODULE,
+	.ioctl = gptu_ioctl,
+	.open = gptu_open,
+	.release = gptu_release
+};
+
+static struct miscdevice gptu_miscdev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "gptu",
+	.fops = &gptu_fops,
+};
+
+static struct timer_dev timer_dev;
+
+static irqreturn_t timer_irq_handler(int irq, void *p)
+{
+	unsigned int timer;
+	unsigned int flag;
+	struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
+
+	timer = irq - TIMER_INTERRUPT;
+	if (timer < timer_dev.number_of_timers
+		&& dev_timer == &timer_dev.timer[timer]) {
+		/*  Clear interrupt.    */
+		ifxmips_w32(1 << timer, IFXMIPS_GPTU_IRNCR);
+
+		/*  Call user hanler or signal. */
+		flag = dev_timer->flag;
+		if (!(timer & 0x01)
+			|| TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
+			/* 16-bit timer or timer A of 32-bit timer  */
+			switch (TIMER_FLAG_MASK_HANDLE(flag)) {
+			case TIMER_FLAG_CALLBACK_IN_IRQ:
+			case TIMER_FLAG_CALLBACK_IN_HB:
+				if (dev_timer->arg1)
+					(*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
+				break;
+			case TIMER_FLAG_SIGNAL:
+				send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
+				break;
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static inline void ifxmips_enable_gptu(void)
+{
+	ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT);
+
+	/*  Set divider as 1, disable write protection for SPEN, enable module. */
+	*IFXMIPS_GPTU_CLC =
+		GPTU_CLC_SMC_SET(0x00) |
+		GPTU_CLC_RMC_SET(0x01) |
+		GPTU_CLC_FSOE_SET(0) |
+		GPTU_CLC_SBWE_SET(1) |
+		GPTU_CLC_EDIS_SET(0) |
+		GPTU_CLC_SPEN_SET(0) |
+		GPTU_CLC_DISR_SET(0);
+}
+
+static inline void ifxmips_disable_gptu(void)
+{
+	ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN);
+	ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
+
+	/*  Set divider as 0, enable write protection for SPEN, disable module. */
+	*IFXMIPS_GPTU_CLC =
+		GPTU_CLC_SMC_SET(0x00) |
+		GPTU_CLC_RMC_SET(0x00) |
+		GPTU_CLC_FSOE_SET(0) |
+		GPTU_CLC_SBWE_SET(0) |
+		GPTU_CLC_EDIS_SET(0) |
+		GPTU_CLC_SPEN_SET(0) |
+		GPTU_CLC_DISR_SET(1);
+
+	ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT);
+}
+
+int ifxmips_request_timer(unsigned int timer, unsigned int flag,
+	unsigned long value, unsigned long arg1, unsigned long arg2)
+{
+	int ret = 0;
+	unsigned int con_reg, irnen_reg;
+	int n, X;
+
+	if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
+		return -EINVAL;
+
+	printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
+		timer, flag, value);
+
+	if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
+		value &= 0xFFFF;
+	else
+		timer &= ~0x01;
+
+	mutex_lock(&timer_dev.gptu_mutex);
+
+	/*
+	 *  Allocate timer.
+	 */
+	if (timer < FIRST_TIMER) {
+		unsigned int mask;
+		unsigned int shift;
+		/* This takes care of TIMER1B which is the only choice for Voice TAPI system */
+		unsigned int offset = TIMER2A;
+
+		/*
+		 *  Pick up a free timer.
+		 */
+		if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
+			mask = 1 << offset;
+			shift = 1;
+		} else {
+			mask = 3 << offset;
+			shift = 2;
+		}
+		for (timer = offset;
+		     timer < offset + timer_dev.number_of_timers;
+		     timer += shift, mask <<= shift)
+			if (!(timer_dev.occupation & mask)) {
+				timer_dev.occupation |= mask;
+				break;
+			}
+		if (timer >= offset + timer_dev.number_of_timers) {
+			printk("failed![%d]\n", __LINE__);
+			mutex_unlock(&timer_dev.gptu_mutex);
+			return -EINVAL;
+		} else
+			ret = timer;
+	} else {
+		register unsigned int mask;
+
+		/*
+		 *  Check if the requested timer is free.
+		 */
+		mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+		if ((timer_dev.occupation & mask)) {
+			printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
+				__LINE__, mask, timer_dev.occupation);
+			mutex_unlock(&timer_dev.gptu_mutex);
+			return -EBUSY;
+		} else {
+			timer_dev.occupation |= mask;
+			ret = 0;
+		}
+	}
+
+	/*
+	 *  Prepare control register value.
+	 */
+	switch (TIMER_FLAG_MASK_EDGE(flag)) {
+	default:
+	case TIMER_FLAG_NONE_EDGE:
+		con_reg = GPTU_CON_EDGE_SET(0x00);
+		break;
+	case TIMER_FLAG_RISE_EDGE:
+		con_reg = GPTU_CON_EDGE_SET(0x01);
+		break;
+	case TIMER_FLAG_FALL_EDGE:
+		con_reg = GPTU_CON_EDGE_SET(0x02);
+		break;
+	case TIMER_FLAG_ANY_EDGE:
+		con_reg = GPTU_CON_EDGE_SET(0x03);
+		break;
+	}
+	if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
+		con_reg |=
+			TIMER_FLAG_MASK_SRC(flag) ==
+			TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
+			GPTU_CON_SRC_EXT_SET(0);
+	else
+		con_reg |=
+			TIMER_FLAG_MASK_SRC(flag) ==
+			TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
+			GPTU_CON_SRC_EG_SET(0);
+	con_reg |=
+		TIMER_FLAG_MASK_SYNC(flag) ==
+		TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
+		GPTU_CON_SYNC_SET(1);
+	con_reg |=
+		TIMER_FLAG_MASK_INVERT(flag) ==
+		TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
+	con_reg |=
+		TIMER_FLAG_MASK_SIZE(flag) ==
+		TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
+		GPTU_CON_EXT_SET(1);
+	con_reg |=
+		TIMER_FLAG_MASK_STOP(flag) ==
+		TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
+	con_reg |=
+		TIMER_FLAG_MASK_TYPE(flag) ==
+		TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
+		GPTU_CON_CNT_SET(1);
+	con_reg |=
+		TIMER_FLAG_MASK_DIR(flag) ==
+		TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
+
+	/*
+	 *  Fill up running data.
+	 */
+	timer_dev.timer[timer - FIRST_TIMER].flag = flag;
+	timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
+	timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
+	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
+		timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
+
+	/*
+	 *  Enable GPTU module.
+	 */
+	if (!timer_dev.f_gptu_on) {
+		ifxmips_enable_gptu();
+		timer_dev.f_gptu_on = 1;
+	}
+
+	/*
+	 *  Enable IRQ.
+	 */
+	if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
+		if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
+			timer_dev.timer[timer - FIRST_TIMER].arg1 =
+				(unsigned long) find_task_by_vpid((int) arg1);
+
+		irnen_reg = 1 << (timer - FIRST_TIMER);
+
+		if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
+		    || (TIMER_FLAG_MASK_HANDLE(flag) ==
+			TIMER_FLAG_CALLBACK_IN_IRQ
+			&& timer_dev.timer[timer - FIRST_TIMER].arg1)) {
+			enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
+			timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
+		}
+	} else
+		irnen_reg = 0;
+
+	/*
+	 *  Write config register, reload value and enable interrupt.
+	 */
+	n = timer >> 1;
+	X = timer & 0x01;
+	*IFXMIPS_GPTU_CON(n, X) = con_reg;
+	*IFXMIPS_GPTU_RELOAD(n, X) = value;
+	/* printk("reload value = %d\n", (u32)value); */
+	*IFXMIPS_GPTU_IRNEN |= irnen_reg;
+
+	mutex_unlock(&timer_dev.gptu_mutex);
+	printk("successful!\n");
+	return ret;
+}
+EXPORT_SYMBOL(ifxmips_request_timer);
+
+int ifxmips_free_timer(unsigned int timer)
+{
+	unsigned int flag;
+	unsigned int mask;
+	int n, X;
+
+	if (!timer_dev.f_gptu_on)
+		return -EINVAL;
+
+	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
+		return -EINVAL;
+
+	mutex_lock(&timer_dev.gptu_mutex);
+
+	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
+	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
+		timer &= ~0x01;
+
+	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+	if (((timer_dev.occupation & mask) ^ mask)) {
+		mutex_unlock(&timer_dev.gptu_mutex);
+		return -EINVAL;
+	}
+
+	n = timer >> 1;
+	X = timer & 0x01;
+
+	if (GPTU_CON_EN(n, X))
+		*IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
+
+	*IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
+	*IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
+
+	if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
+		disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
+		timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
+	}
+
+	timer_dev.occupation &= ~mask;
+	if (!timer_dev.occupation && timer_dev.f_gptu_on) {
+		ifxmips_disable_gptu();
+		timer_dev.f_gptu_on = 0;
+	}
+
+	mutex_unlock(&timer_dev.gptu_mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_free_timer);
+
+int ifxmips_start_timer(unsigned int timer, int is_resume)
+{
+	unsigned int flag;
+	unsigned int mask;
+	int n, X;
+
+	if (!timer_dev.f_gptu_on)
+		return -EINVAL;
+
+	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
+		return -EINVAL;
+
+	mutex_lock(&timer_dev.gptu_mutex);
+
+	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
+	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
+		timer &= ~0x01;
+
+	mask = (TIMER_FLAG_MASK_SIZE(flag) ==
+	TIMER_FLAG_16BIT ? 1 : 3) << timer;
+	if (((timer_dev.occupation & mask) ^ mask)) {
+		mutex_unlock(&timer_dev.gptu_mutex);
+		return -EINVAL;
+	}
+
+	n = timer >> 1;
+	X = timer & 0x01;
+
+	*IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
+
+	mutex_unlock(&timer_dev.gptu_mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_start_timer);
+
+int ifxmips_stop_timer(unsigned int timer)
+{
+	unsigned int flag;
+	unsigned int mask;
+	int n, X;
+
+	if (!timer_dev.f_gptu_on)
+		return -EINVAL;
+
+	if (timer < FIRST_TIMER
+	    || timer >= FIRST_TIMER + timer_dev.number_of_timers)
+		return -EINVAL;
+
+	mutex_lock(&timer_dev.gptu_mutex);
+
+	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
+	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
+		timer &= ~0x01;
+
+	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+	if (((timer_dev.occupation & mask) ^ mask)) {
+		mutex_unlock(&timer_dev.gptu_mutex);
+		return -EINVAL;
+	}
+
+	n = timer >> 1;
+	X = timer & 0x01;
+
+	*IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
+
+	mutex_unlock(&timer_dev.gptu_mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_stop_timer);
+
+int ifxmips_reset_counter_flags(u32 timer, u32 flags)
+{
+	unsigned int oflag;
+	unsigned int mask, con_reg;
+	int n, X;
+
+	if (!timer_dev.f_gptu_on)
+		return -EINVAL;
+
+	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
+		return -EINVAL;
+
+	mutex_lock(&timer_dev.gptu_mutex);
+
+	oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
+	if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
+		timer &= ~0x01;
+
+	mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+	if (((timer_dev.occupation & mask) ^ mask)) {
+		mutex_unlock(&timer_dev.gptu_mutex);
+		return -EINVAL;
+	}
+
+	switch (TIMER_FLAG_MASK_EDGE(flags)) {
+	default:
+	case TIMER_FLAG_NONE_EDGE:
+		con_reg = GPTU_CON_EDGE_SET(0x00);
+		break;
+	case TIMER_FLAG_RISE_EDGE:
+		con_reg = GPTU_CON_EDGE_SET(0x01);
+		break;
+	case TIMER_FLAG_FALL_EDGE:
+		con_reg = GPTU_CON_EDGE_SET(0x02);
+		break;
+	case TIMER_FLAG_ANY_EDGE:
+		con_reg = GPTU_CON_EDGE_SET(0x03);
+		break;
+	}
+	if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
+		con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
+	else
+		con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
+	con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
+	con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
+	con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
+	con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
+	con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
+	con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
+
+	timer_dev.timer[timer - FIRST_TIMER].flag = flags;
+	if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
+		timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
+
+	n = timer >> 1;
+	X = timer & 0x01;
+
+	*IFXMIPS_GPTU_CON(n, X) = con_reg;
+	smp_wmb();
+	printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON(n, X));
+	mutex_unlock(&timer_dev.gptu_mutex);
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_reset_counter_flags);
+
+int ifxmips_get_count_value(unsigned int timer, unsigned long *value)
+{
+	unsigned int flag;
+	unsigned int mask;
+	int n, X;
+
+	if (!timer_dev.f_gptu_on)
+		return -EINVAL;
+
+	if (timer < FIRST_TIMER
+	    || timer >= FIRST_TIMER + timer_dev.number_of_timers)
+		return -EINVAL;
+
+	mutex_lock(&timer_dev.gptu_mutex);
+
+	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
+	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
+		timer &= ~0x01;
+
+	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
+	if (((timer_dev.occupation & mask) ^ mask)) {
+		mutex_unlock(&timer_dev.gptu_mutex);
+		return -EINVAL;
+	}
+
+	n = timer >> 1;
+	X = timer & 0x01;
+
+	*value = *IFXMIPS_GPTU_COUNT(n, X);
+
+	mutex_unlock(&timer_dev.gptu_mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(ifxmips_get_count_value);
+
+u32 ifxmips_cal_divider(unsigned long freq)
+{
+	u64 module_freq, fpi = cgu_get_fpi_bus_clock(2);
+	u32 clock_divider = 1;
+	module_freq = fpi * 1000;
+	do_div(module_freq, clock_divider * freq);
+	return module_freq;
+}
+EXPORT_SYMBOL(ifxmips_cal_divider);
+
+int ifxmips_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
+	int is_ext_src, unsigned int handle_flag, unsigned long arg1,
+	unsigned long arg2)
+{
+	unsigned long divider;
+	unsigned int flag;
+
+	divider = ifxmips_cal_divider(freq);
+	if (divider == 0)
+		return -EINVAL;
+	flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
+		| (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
+		| (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
+		| TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
+		| TIMER_FLAG_MASK_HANDLE(handle_flag);
+
+	printk(KERN_INFO "ifxmips_set_timer(%d, %d), divider = %lu\n",
+		timer, freq, divider);
+	return ifxmips_request_timer(timer, flag, divider, arg1, arg2);
+}
+EXPORT_SYMBOL(ifxmips_set_timer);
+
+int ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload,
+	unsigned long arg1, unsigned long arg2)
+{
+	printk(KERN_INFO "ifxmips_set_counter(%d, %#x, %d)\n", timer, flag, reload);
+	return ifxmips_request_timer(timer, flag, reload, arg1, arg2);
+}
+EXPORT_SYMBOL(ifxmips_set_counter);
+
+static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
+	unsigned long arg)
+{
+	int ret;
+	struct gptu_ioctl_param param;
+
+	if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
+		return -EFAULT;
+	copy_from_user(&param, (void *) arg, sizeof(param));
+
+	if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
+	       || GPTU_SET_COUNTER) && param.timer < 2)
+	     || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
+	    && !access_ok(VERIFY_WRITE, arg,
+			   sizeof(struct gptu_ioctl_param)))
+		return -EFAULT;
+
+	switch (cmd) {
+	case GPTU_REQUEST_TIMER:
+		ret = ifxmips_request_timer(param.timer, param.flag, param.value,
+				     (unsigned long) param.pid,
+				     (unsigned long) param.sig);
+		if (ret > 0) {
+			copy_to_user(&((struct gptu_ioctl_param *) arg)->
+				      timer, &ret, sizeof(&ret));
+			ret = 0;
+		}
+		break;
+	case GPTU_FREE_TIMER:
+		ret = ifxmips_free_timer(param.timer);
+		break;
+	case GPTU_START_TIMER:
+		ret = ifxmips_start_timer(param.timer, param.flag);
+		break;
+	case GPTU_STOP_TIMER:
+		ret = ifxmips_stop_timer(param.timer);
+		break;
+	case GPTU_GET_COUNT_VALUE:
+		ret = ifxmips_get_count_value(param.timer, &param.value);
+		if (!ret)
+			copy_to_user(&((struct gptu_ioctl_param *) arg)->
+				      value, &param.value,
+				      sizeof(param.value));
+		break;
+	case GPTU_CALCULATE_DIVIDER:
+		param.value = ifxmips_cal_divider(param.value);
+		if (param.value == 0)
+			ret = -EINVAL;
+		else {
+			copy_to_user(&((struct gptu_ioctl_param *) arg)->
+				      value, &param.value,
+				      sizeof(param.value));
+			ret = 0;
+		}
+		break;
+	case GPTU_SET_TIMER:
+		ret = ifxmips_set_timer(param.timer, param.value,
+				 TIMER_FLAG_MASK_STOP(param.flag) !=
+				 TIMER_FLAG_ONCE ? 1 : 0,
+				 TIMER_FLAG_MASK_SRC(param.flag) ==
+				 TIMER_FLAG_EXT_SRC ? 1 : 0,
+				 TIMER_FLAG_MASK_HANDLE(param.flag) ==
+				 TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
+				 TIMER_FLAG_NO_HANDLE,
+				 (unsigned long) param.pid,
+				 (unsigned long) param.sig);
+		if (ret > 0) {
+			copy_to_user(&((struct gptu_ioctl_param *) arg)->
+				      timer, &ret, sizeof(&ret));
+			ret = 0;
+		}
+		break;
+	case GPTU_SET_COUNTER:
+		ifxmips_set_counter(param.timer, param.flag, param.value, 0, 0);
+		if (ret > 0) {
+			copy_to_user(&((struct gptu_ioctl_param *) arg)->
+				      timer, &ret, sizeof(&ret));
+			ret = 0;
+		}
+		break;
+	default:
+		ret = -ENOTTY;
+	}
+
+	return ret;
+}
+
+static int gptu_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int gptu_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+int __init ifxmips_gptu_init(void)
+{
+	int ret;
+	unsigned int i;
+
+	ifxmips_w32(0, IFXMIPS_GPTU_IRNEN);
+	ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
+
+	memset(&timer_dev, 0, sizeof(timer_dev));
+	mutex_init(&timer_dev.gptu_mutex);
+
+	ifxmips_enable_gptu();
+	timer_dev.number_of_timers = GPTU_ID_CFG * 2;
+	ifxmips_disable_gptu();
+	if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
+		timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
+	printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
+
+	ret = misc_register(&gptu_miscdev);
+	if (ret) {
+		printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
+		return ret;
+	} else {
+		printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
+	}
+
+	for (i = 0; i < timer_dev.number_of_timers; i++) {
+		ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
+		if (ret) {
+			for (; i >= 0; i--)
+				free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
+			misc_deregister(&gptu_miscdev);
+			printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
+			return ret;
+		} else {
+			timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
+			disable_irq(timer_dev.timer[i].irq);
+			printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
+		}
+	}
+
+	return 0;
+}
+
+void __exit ifxmips_gptu_exit(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < timer_dev.number_of_timers; i++) {
+		if (timer_dev.timer[i].f_irq_on)
+			disable_irq(timer_dev.timer[i].irq);
+		free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
+	}
+	ifxmips_disable_gptu();
+	misc_deregister(&gptu_miscdev);
+}
+
+module_init(ifxmips_gptu_init);
+module_exit(ifxmips_gptu_exit);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/Kconfig

@@ -0,0 +1,29 @@
+if IFXMIPS_DANUBE
+
+config IFXMIPS_ARCAYDIAN_BRNBOOT
+	bool
+	default n
+
+menu "infineon SoC machine selection"
+
+config DANUBE_MACH_EASY50712
+	bool "Easy50712"
+	default y
+
+config DANUBE_MACH_EASY4010
+	bool "Easy4010"
+	default y
+
+config DANUBE_MACH_ARV4519
+	bool "ARV4519"
+	default y
+	select DANUBE_ARCAYDIAN_BRNBOOT
+
+config DANUBE_MACH_ARV452
+	bool "ARV452"
+	default y
+	select IFXMIPS_ARCAYDIAN_BRNBOOT
+
+endmenu
+
+endif

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/Makefile

@@ -0,0 +1,5 @@
+obj-y := dma-core.o irq.o ebu.o setup.o devices.o cgu.o
+obj-$(CONFIG_IFXMIPS_ARCAYDIAN_BRNBOOT) += arcaydian.o
+obj-$(CONFIG_DANUBE_MACH_ARV452) += mach-arv452.o
+obj-$(CONFIG_DANUBE_MACH_EASY50712) += mach-easy50712.o
+obj-$(CONFIG_DANUBE_MACH_EASY4010) += mach-easy4010.o

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/arcaydian.c

@@ -0,0 +1,47 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mtd/physmap.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/reboot.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <ifxmips.h>
+#include <ifxmips_prom.h>
+
+#include "arcaydian.h"
+
+static int ifxmips_brn = 1;
+
+int __init
+ifxmips_find_brn_mac(unsigned char *ifxmips_ethaddr)
+{
+	unsigned char temp[8];
+	memcpy_fromio(temp,
+		(void *)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000), 8);
+	if (!memcmp(temp, "BRN-BOOT", 8))
+	{
+		memcpy_fromio(ifxmips_ethaddr,
+			(void *)KSEG1ADDR(IFXMIPS_FLASH_START +
+			0x800000 - 0x10000 + 0x16), 6);
+		if (is_valid_ether_addr(ifxmips_ethaddr))
+			return 1;
+	} else {
+		ifxmips_brn = 0;
+	}
+	return 0;
+}
+
+int
+ifxmips_has_brn_block(void)
+{
+	return ifxmips_brn;
+}
+EXPORT_SYMBOL(ifxmips_has_brn_block);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/arcaydian.h

@@ -0,0 +1,6 @@
+#ifndef _ARCAYDIAN_H__
+#define _ARCAYDIAN_H__
+
+int __init ifxmips_find_brn_mac(unsigned char *ifxmips_ethaddr);
+
+#endif

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/board.c

@@ -0,0 +1,457 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mtd/physmap.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/reboot.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+
+#define MAX_BOARD_NAME_LEN		32
+#define MAX_IFXMIPS_DEVS		9
+
+#define SYSTEM_DANUBE			"Danube"
+#define SYSTEM_DANUBE_CHIPID1	0x00129083
+#define SYSTEM_DANUBE_CHIPID2	0x0012B083
+
+#define SYSTEM_TWINPASS			"Twinpass"
+#define SYSTEM_TWINPASS_CHIPID	0x0012D083
+
+enum {
+	EASY50712,
+	EASY4010,
+	ARV4519,
+	ARV452,
+};
+
+extern int ifxmips_pci_external_clock;
+extern int ifxmips_pci_req_mask;
+
+static unsigned int chiprev;
+static int cmdline_mac;
+char board_name[MAX_BOARD_NAME_LEN + 1] = { 0 };
+
+struct ifxmips_board {
+	int type;
+	char name[32];
+	unsigned int system_type;
+	struct platform_device **devs;
+	struct resource reset_resource;
+	struct resource gpiodev_resource;
+	struct gpio_led *ifxmips_leds;
+	struct gpio_led *gpio_leds;
+	int pci_external_clock;
+	int pci_req_mask;
+	int num_devs;
+};
+
+DEFINE_SPINLOCK(ebu_lock);
+EXPORT_SYMBOL_GPL(ebu_lock);
+
+extern unsigned char ifxmips_ethaddr[6];
+static int ifxmips_brn;
+
+static struct gpio_led_platform_data ifxmips_led_data;
+
+static struct platform_device ifxmips_led = {
+	.id = 0,
+	.name = "ifxmips_led",
+	.dev = {
+		.platform_data = (void *) &ifxmips_led_data,
+	}
+};
+
+static struct platform_device ifxmips_gpio = {
+	.id = 0,
+	.name = "ifxmips_gpio",
+	.num_resources = 1,
+};
+
+static struct platform_device ifxmips_mii = {
+	.id = 0,
+	.name = "ifxmips_mii0",
+	.dev = {
+		.platform_data = ifxmips_ethaddr,
+	}
+};
+
+static struct platform_device ifxmips_wdt = {
+	.id = 0,
+	.name = "ifxmips_wdt",
+};
+
+static struct platform_device ifxmips_ebu = {
+	.id = 0,
+	.name = "ifxmips_ebu",
+};
+
+static struct resource ifxmips_mtd_resource = {
+	.start  = IFXMIPS_FLASH_START,
+	.end    = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1,
+	.flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device ifxmips_mtd = {
+	.id = 0,
+	.name = "ifxmips_mtd",
+	.num_resources  = 1,
+	.resource   = &ifxmips_mtd_resource,
+};
+
+static struct platform_device ifxmips_gpio_dev = {
+	.name     = "GPIODEV",
+	.id     = -1,
+	.num_resources    =	1,
+};
+
+#ifdef CONFIG_LEDS_GPIO
+static struct gpio_led arv4519_gpio_leds[] = {
+	{ .name = "ifx:green:power", .gpio = 3, .active_low = 1, },
+	{ .name = "ifx:red:power", .gpio = 7, .active_low = 1, },
+	{ .name = "ifx:green:adsl", .gpio = 4, .active_low = 1, },
+	{ .name = "ifx:green:internet", .gpio = 5, .active_low = 1, },
+	{ .name = "ifx:red:internet", .gpio = 8, .active_low = 1, },
+	{ .name = "ifx:green:wlan", .gpio = 6, .active_low = 1, },
+	{ .name = "ifx:green:usbpwr", .gpio = 14, .active_low = 1, },
+	{ .name = "ifx:green:usb", .gpio = 19, .active_low = 1, },
+};
+
+static struct gpio_led arv452_gpio_leds[] = {
+	{ .name = "ifx:blue:power", .gpio = 3, .active_low = 1, },
+	{ .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, },
+	{ .name = "ifx:blue:internet", .gpio = 5, .active_low = 1, },
+	{ .name = "ifx:red:power", .gpio = 6, .active_low = 1, },
+	{ .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, },
+	{ .name = "ifx:red:wps", .gpio = 9, .active_low = 1, },
+	{ .name = "ifx:blue:voip", .gpio = 32, .active_low = 1, },
+	{ .name = "ifx:blue:fxs1", .gpio = 33, .active_low = 1, },
+	{ .name = "ifx:blue:fxs2", .gpio = 34, .active_low = 1, },
+	{ .name = "ifx:blue:fxo", .gpio = 35, .active_low = 1, },
+	{ .name = "ifx:blue:voice", .gpio = 36, .active_low = 1, },
+	{ .name = "ifx:blue:usb", .gpio = 37, .active_low = 1, },
+	{ .name = "ifx:blue:wlan", .gpio = 38, .active_low = 1, },
+	{ .name = "ifx:red:internet", .gpio = 41, .active_low = 1, },
+};
+
+static struct gpio_led_platform_data ifxmips_gpio_led_data;
+
+static struct platform_device ifxmips_gpio_leds = {
+	.name = "leds-gpio",
+	.id = -1,
+	.dev = {
+		.platform_data = (void *) &ifxmips_gpio_led_data,
+	}
+};
+#endif
+
+static struct resource dwc_usb_res[] = {
+	{
+		.name = "dwc3884_membase",
+		.flags = IORESOURCE_MEM,
+		.start = 0x1E101000,
+		.end = 0x1E101FFF
+	},
+	{
+		.name = "dwc3884_irq",
+		.flags = IORESOURCE_IRQ,
+		.start = IFXMIPS_USB_INT,
+	}
+};
+
+static struct platform_device dwc_usb =
+{
+	.id = 0,
+	.name = "dwc3884-hcd",
+	.resource = dwc_usb_res,
+	.num_resources = ARRAY_SIZE(dwc_usb_res),
+};
+
+struct platform_device *easy50712_devs[] = {
+	&ifxmips_led, &ifxmips_gpio, &ifxmips_mii,
+	&ifxmips_mtd, &ifxmips_wdt, &ifxmips_gpio_dev, &dwc_usb
+};
+
+struct platform_device *easy4010_devs[] = {
+	&ifxmips_led, &ifxmips_gpio, &ifxmips_mii,
+	&ifxmips_mtd, &ifxmips_wdt, &ifxmips_gpio_dev, &dwc_usb
+};
+
+struct platform_device *arv5419_devs[] = {
+	&ifxmips_gpio, &ifxmips_mii, &ifxmips_mtd,
+	&ifxmips_gpio_dev, &ifxmips_wdt, &dwc_usb,
+#ifdef CONFIG_LEDS_GPIO
+	&ifxmips_gpio_leds,
+#endif
+};
+
+struct platform_device *arv452_devs[] = {
+	&ifxmips_gpio, &ifxmips_mii, &ifxmips_mtd,
+	&ifxmips_gpio_dev, &ifxmips_wdt, &dwc_usb,
+	&ifxmips_ebu,
+#ifdef CONFIG_LEDS_GPIO
+	&ifxmips_gpio_leds,
+#endif
+};
+
+static struct gpio_led easy50712_leds[] = {
+	{ .name = "ifx:green:test0", .gpio = 0,},
+	{ .name = "ifx:green:test1", .gpio = 1,},
+	{ .name = "ifx:green:test2", .gpio = 2,},
+	{ .name = "ifx:green:test3", .gpio = 3,},
+};
+
+static struct gpio_led easy4010_leds[] = {
+	{ .name = "ifx:green:test0", .gpio = 0,},
+	{ .name = "ifx:green:test1", .gpio = 1,},
+	{ .name = "ifx:green:test2", .gpio = 2,},
+	{ .name = "ifx:green:test3", .gpio = 3,},
+};
+
+static struct ifxmips_board boards[] = {
+	{
+		/* infineon eval kit */
+		.type = EASY50712,
+		.name = "EASY50712",
+		.system_type = SYSTEM_DANUBE_CHIPID1,
+		.devs = easy50712_devs,
+		.reset_resource = {.name = "reset", .start = 1, .end = 15,},
+		.gpiodev_resource = { .name = "gpio",
+			.start = (1 << 0) | (1 << 1),
+			.end = (1 << 0) | (1 << 1)},
+		.ifxmips_leds = easy50712_leds,
+	}, {
+		/* infineon eval kit */
+		.type = EASY4010,
+		.name = "EASY4010",
+		.system_type = SYSTEM_TWINPASS_CHIPID,
+		.devs = easy4010_devs,
+		.reset_resource = {.name = "reset", .start = 1, .end = 15},
+		.gpiodev_resource = { .name = "gpio",
+			.start = (1 << 0) | (1 << 1),
+			.end = (1 << 0) | (1 << 1)},
+		.ifxmips_leds = easy4010_leds,
+	}, {
+		/* arcaydian annex-a board used by thompson, airties, ... */
+		.type = ARV4519,
+		.name = "ARV4519",
+		.system_type = SYSTEM_DANUBE_CHIPID2,
+		.devs = arv5419_devs,
+		.reset_resource = {.name = "reset", .start = 1, .end = 14},
+		.pci_external_clock = 1,
+#ifdef CONFIG_LEDS_GPIO
+		.gpio_leds = arv4519_gpio_leds,
+#endif
+	}, {
+		/* arcaydian annex-b board used by airties, arcor */
+		.type = ARV452,
+		.name = "ARV452",
+		.system_type = SYSTEM_DANUBE_CHIPID2,
+		.devs = arv452_devs,
+		.reset_resource = {.name = "reset", .start = 1, .end = 14},
+		.pci_external_clock = 1,
+#ifdef CONFIG_LEDS_GPIO
+		.gpio_leds = arv452_gpio_leds,
+#endif
+	},
+};
+
+const char *get_system_type(void)
+{
+	chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF);
+
+	switch (chiprev) {
+	case SYSTEM_DANUBE_CHIPID1:
+	case SYSTEM_DANUBE_CHIPID2:
+		return SYSTEM_DANUBE;
+
+	case SYSTEM_TWINPASS_CHIPID:
+		return SYSTEM_TWINPASS;
+	}
+
+	return BOARD_SYSTEM_TYPE;
+}
+
+static int __init ifxmips_set_board_type(char *str)
+{
+	str = strchr(str, '=');
+	if (!str)
+		goto out;
+	str++;
+	if (strlen(str) > MAX_BOARD_NAME_LEN)
+		goto out;
+	strncpy(board_name, str, MAX_BOARD_NAME_LEN);
+	printk(KERN_INFO "bootloader told us, that this is a %s board\n",
+		board_name);
+out:
+	return 1;
+}
+__setup("ifxmips_board", ifxmips_set_board_type);
+
+static int __init ifxmips_set_ethaddr(char *str)
+{
+#define IS_HEX(x) \
+	(((x >= '0' && x <= '9') || (x >= 'a' && x <= 'f') \
+		|| (x >= 'A' && x <= 'F')) ? (1) : (0))
+	int i;
+	str = strchr(str, '=');
+	if (!str)
+		goto out;
+	str++;
+	if (strlen(str) != 17)
+		goto out;
+	for (i = 0; i < 6; i++) {
+		if (!IS_HEX(str[3 * i]) || !IS_HEX(str[(3 * i) + 1]))
+			goto out;
+		if ((i != 5) && (str[(3 * i) + 2] != ':'))
+			goto out;
+		ifxmips_ethaddr[i] = simple_strtoul(&str[3 * i], NULL, 16);
+	}
+	if (is_valid_ether_addr(ifxmips_ethaddr))
+		cmdline_mac = 1;
+out:
+	return 1;
+}
+__setup("ethaddr", ifxmips_set_ethaddr);
+
+int ifxmips_find_brn_block(void)
+{
+	unsigned char temp[8];
+	memcpy_fromio(temp,
+		(void *)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000), 8);
+	if (memcmp(temp, "BRN-BOOT", 8) == 0) {
+		if (!cmdline_mac)
+			memcpy_fromio(ifxmips_ethaddr,
+				(void *)KSEG1ADDR(IFXMIPS_FLASH_START +
+					0x800000 - 0x10000 + 0x16), 6);
+		if (is_valid_ether_addr(ifxmips_ethaddr))
+			cmdline_mac = 1;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int ifxmips_has_brn_block(void)
+{
+	return ifxmips_brn;
+}
+EXPORT_SYMBOL(ifxmips_has_brn_block);
+
+struct ifxmips_board *ifxmips_find_board(void)
+{
+	int i;
+	if (!*board_name)
+		return 0;
+	for (i = 0; i < ARRAY_SIZE(boards); i++)
+		if ((boards[i].system_type == chiprev) &&
+		    (!strcmp(boards[i].name, board_name)))
+			return &boards[i];
+	return 0;
+}
+
+int __init ifxmips_init_devices(void)
+{
+	struct ifxmips_board *board;
+
+	chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF);
+	board = ifxmips_find_board();
+	ifxmips_brn = ifxmips_find_brn_block();
+
+	if (!cmdline_mac)
+		random_ether_addr(ifxmips_ethaddr);
+
+	if (!board) {
+		switch (chiprev) {
+		case SYSTEM_DANUBE_CHIPID1:
+		case SYSTEM_DANUBE_CHIPID2:
+		default:
+			board = &boards[0];
+			break;
+		case SYSTEM_TWINPASS_CHIPID:
+			board = &boards[1];
+			break;
+		}
+	}
+
+	switch (board->type) {
+	case EASY50712:
+		board->num_devs = ARRAY_SIZE(easy50712_devs);
+		ifxmips_led_data.num_leds = ARRAY_SIZE(easy50712_leds);
+		break;
+	case EASY4010:
+		board->num_devs = ARRAY_SIZE(easy4010_devs);
+		ifxmips_led_data.num_leds = ARRAY_SIZE(easy4010_leds);
+		break;
+	case ARV4519:
+		/* set some sane defaults for the gpios */
+		gpio_set_value(3, 0);
+		gpio_set_value(4, 0);
+		gpio_set_value(5, 0);
+		gpio_set_value(6, 0);
+		gpio_set_value(7, 1);
+		gpio_set_value(8, 1);
+		gpio_set_value(19, 0);
+		board->num_devs = ARRAY_SIZE(arv5419_devs);
+#ifdef CONFIG_LEDS_GPIO
+		ifxmips_gpio_led_data.num_leds = ARRAY_SIZE(arv4519_gpio_leds);
+#endif
+		break;
+	case ARV452:
+		/* set some sane defaults for the gpios */
+		board->num_devs = ARRAY_SIZE(arv452_devs);
+		ifxmips_w32(0x8001e7ff, IFXMIPS_EBU_BUSCON1);
+#ifdef CONFIG_LEDS_GPIO
+		ifxmips_gpio_led_data.num_leds = ARRAY_SIZE(arv452_gpio_leds);
+#endif
+		break;
+	}
+#ifdef CONFIG_LEDS_GPIO
+	ifxmips_gpio_led_data.leds = board->gpio_leds;
+#endif
+	ifxmips_led_data.leds = board->ifxmips_leds;
+
+	printk(KERN_INFO "%s: adding %d devs\n",
+		__func__, board->num_devs);
+
+	ifxmips_gpio.resource = &board->reset_resource;
+	ifxmips_gpio_dev.resource = &board->gpiodev_resource;
+	if (board->pci_external_clock)
+		ifxmips_pci_external_clock = 1;
+	if (board->pci_req_mask)
+		ifxmips_pci_req_mask = board->pci_req_mask;
+	printk(KERN_INFO "using board definition %s\n", board->name);
+	return platform_add_devices(board->devs, board->num_devs);
+}
+
+arch_initcall(ifxmips_init_devices);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/cgu.c

@@ -0,0 +1,38 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+#include <linux/errno.h>
+
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <ifxmips.h>
+#include <ifxmips_cgu.h>
+
+void
+cgu_setup_pci_clk(int external_clock)
+{
+	/* set clock to 33Mhz */
+	ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
+		IFXMIPS_CGU_IFCCR);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
+		IFXMIPS_CGU_IFCCR);
+	if (external_clock)
+	{
+		ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
+			IFXMIPS_CGU_IFCCR);
+		ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
+	} else {
+		ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
+			IFXMIPS_CGU_IFCCR);
+		ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
+	}
+}
+
+

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/devices.c

@@ -0,0 +1,104 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mtd/physmap.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/reboot.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+
+/* usb */
+static struct resource dwc_usb_res[] =
+{
+	{
+		.name = "dwc3884_membase",
+		.flags = IORESOURCE_MEM,
+		.start = 0x1E101000,
+		.end = 0x1E101FFF
+	},
+	{
+		.name = "dwc3884_irq",
+		.flags = IORESOURCE_IRQ,
+		.start = IFXMIPS_USB_INT,
+	}
+};
+
+static struct platform_device dwc_usb =
+{
+	.name = "dwc3884-hcd",
+	.resource = dwc_usb_res,
+	.num_resources = ARRAY_SIZE(dwc_usb_res),
+};
+
+void __init
+danube_register_usb(void)
+{
+	platform_device_register(&dwc_usb);
+}
+
+/* ebu gpio */
+static struct platform_device ifxmips_ebu_gpio =
+{
+	.name = "ifxmips_ebu",
+	.num_resources = 1,
+};
+
+void __init
+danube_register_ebu_gpio(struct resource *resource, u32 value)
+{
+	ifxmips_ebu_gpio.resource = resource;
+	ifxmips_ebu_gpio.dev.platform_data = (void*)value;
+	platform_device_register(&ifxmips_ebu_gpio);
+}
+
+/* ethernet */
+unsigned char ifxmips_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+static struct resource danube_ethernet_resources =
+{
+	.start  = IFXMIPS_PPE32_BASE_ADDR,
+	.end    = IFXMIPS_PPE32_BASE_ADDR + IFXMIPS_PPE32_SIZE - 1,
+	.flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device danube_ethernet =
+{
+	.name			= "ifxmips_mii0",
+	.resource		= &danube_ethernet_resources,
+	.num_resources	= 1,
+	.dev = {
+		.platform_data = ifxmips_ethaddr,
+	}
+};
+
+void __init
+danube_register_ethernet(unsigned char *mac)
+{
+	if(mac)
+		danube_ethernet.dev.platform_data = mac;
+	platform_device_register(&danube_ethernet);
+}
+
+/* pci */
+extern int ifxmips_pci_external_clock;
+extern int ifxmips_pci_req_mask;
+
+void __init
+danube_register_pci(int clock, int irq_mask)
+{
+	ifxmips_pci_external_clock = clock;
+	if(irq_mask)
+		ifxmips_pci_req_mask = irq_mask;
+}

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/devices.h

@@ -0,0 +1,16 @@
+#ifndef _DANUBE_DEVICES_H__
+#define _DANUBE_DEVICES_H__
+
+#include "../common/devices.h"
+
+enum {
+	PCI_CLOCK_INT = 0,
+	PCI_CLOCK_EXT
+};
+
+void __init danube_register_usb(void);
+void __init danube_register_ebu_gpio(struct resource *resource, u32 value);
+void __init danube_register_ethernet(unsigned char *mac);
+void __init danube_register_pci(int clock, int irq_mask);
+
+#endif

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/dma-core.c

@@ -0,0 +1,690 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/stat.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/selection.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/uaccess.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_dma.h>
+#include <ifxmips_pmu.h>
+
+/*25 descriptors for each dma channel,4096/8/20=25.xx*/
+#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
+
+#define MAX_DMA_DEVICE_NUM  6	/*max ports connecting to dma */
+#define MAX_DMA_CHANNEL_NUM 20	/*max dma channels */
+#define DMA_INT_BUDGET      100	/*budget for interrupt handling */
+#define DMA_POLL_COUNTER    4	/*fix me, set the correct counter value here! */
+
+extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
+extern void ifxmips_enable_irq(unsigned int irq_nr);
+extern void ifxmips_disable_irq(unsigned int irq_nr);
+
+u64 *g_desc_list;
+struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
+struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
+
+static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
+	{ "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
+
+struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
+	{"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
+	{"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
+	{"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
+	{"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1},
+	{"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2},
+	{"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2},
+	{"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3},
+	{"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3},
+	{"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0},
+	{"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0},
+	{"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1},
+	{"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1},
+	{"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0},
+	{"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0},
+	{"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0},
+	{"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0},
+	{"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0},
+	{"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0},
+	{"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1},
+	{"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
+};
+
+struct dma_chan_map *chan_map = default_dma_map;
+volatile u32 g_ifxmips_dma_int_status;
+volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */
+
+void do_dma_tasklet(unsigned long);
+DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
+
+u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
+{
+	u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
+
+	*byte_offset = 0;
+
+	return buffer;
+}
+
+void common_buffer_free(u8 *dataptr, void *opt)
+{
+	kfree(dataptr);
+}
+
+void enable_ch_irq(struct dma_channel_info *pCh)
+{
+	int chan_no = (int)(pCh - dma_chan);
+	unsigned long flag;
+
+	local_irq_save(flag);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(0x4a, IFXMIPS_DMA_CIE);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+	local_irq_restore(flag);
+	ifxmips_enable_irq(pCh->irq);
+}
+
+void disable_ch_irq(struct dma_channel_info *pCh)
+{
+	unsigned long flag;
+	int chan_no = (int) (pCh - dma_chan);
+
+	local_irq_save(flag);
+	g_ifxmips_dma_int_status &= ~(1 << chan_no);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(0, IFXMIPS_DMA_CIE);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
+	local_irq_restore(flag);
+	ifxmips_mask_and_ack_irq(pCh->irq);
+}
+
+void open_chan(struct dma_channel_info *pCh)
+{
+	unsigned long flag;
+	int chan_no = (int)(pCh - dma_chan);
+
+	local_irq_save(flag);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
+	if (pCh->dir == IFXMIPS_DMA_RX)
+		enable_ch_irq(pCh);
+	local_irq_restore(flag);
+}
+
+void close_chan(struct dma_channel_info *pCh)
+{
+	unsigned long flag;
+	int chan_no = (int) (pCh - dma_chan);
+
+	local_irq_save(flag);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+	disable_ch_irq(pCh);
+	local_irq_restore(flag);
+}
+
+void reset_chan(struct dma_channel_info *pCh)
+{
+	int chan_no = (int) (pCh - dma_chan);
+
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+}
+
+void rx_chan_intr_handler(int chan_no)
+{
+	struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
+	struct dma_channel_info *pCh = &dma_chan[chan_no];
+	struct rx_desc *rx_desc_p;
+	int tmp;
+	unsigned long flag;
+
+	/*handle command complete interrupt */
+	rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
+	if (rx_desc_p->status.field.OWN == CPU_OWN
+	    && rx_desc_p->status.field.C
+	    && rx_desc_p->status.field.data_length < 1536){
+		/* Every thing is correct, then we inform the upper layer */
+		pDev->current_rx_chan = pCh->rel_chan_no;
+		if (pDev->intr_handler)
+			pDev->intr_handler(pDev, RCV_INT);
+		pCh->weight--;
+	} else {
+		local_irq_save(flag);
+		tmp = ifxmips_r32(IFXMIPS_DMA_CS);
+		ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+		ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+		ifxmips_w32(tmp, IFXMIPS_DMA_CS);
+		g_ifxmips_dma_int_status &= ~(1 << chan_no);
+		local_irq_restore(flag);
+		ifxmips_enable_irq(dma_chan[chan_no].irq);
+	}
+}
+
+inline void tx_chan_intr_handler(int chan_no)
+{
+	struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
+	struct dma_channel_info *pCh = &dma_chan[chan_no];
+	int tmp;
+	unsigned long flag;
+
+	local_irq_save(flag);
+	tmp = ifxmips_r32(IFXMIPS_DMA_CS);
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+	ifxmips_w32(tmp, IFXMIPS_DMA_CS);
+	g_ifxmips_dma_int_status &= ~(1 << chan_no);
+	local_irq_restore(flag);
+	pDev->current_tx_chan = pCh->rel_chan_no;
+	if (pDev->intr_handler)
+		pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
+}
+
+void do_dma_tasklet(unsigned long unused)
+{
+	int i;
+	int chan_no = 0;
+	int budget = DMA_INT_BUDGET;
+	int weight = 0;
+	unsigned long flag;
+
+	while (g_ifxmips_dma_int_status) {
+		if (budget-- < 0) {
+			tasklet_schedule(&dma_tasklet);
+			return;
+		}
+		chan_no = -1;
+		weight = 0;
+		for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
+			if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
+				if (dma_chan[i].weight > weight) {
+					chan_no = i;
+					weight = dma_chan[chan_no].weight;
+				}
+			}
+		}
+
+		if (chan_no >= 0) {
+			if (chan_map[chan_no].dir == IFXMIPS_DMA_RX)
+				rx_chan_intr_handler(chan_no);
+			else
+				tx_chan_intr_handler(chan_no);
+		} else {
+			for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+				dma_chan[i].weight = dma_chan[i].default_weight;
+		}
+	}
+
+	local_irq_save(flag);
+	g_ifxmips_dma_in_process = 0;
+	if (g_ifxmips_dma_int_status) {
+		g_ifxmips_dma_in_process = 1;
+		tasklet_schedule(&dma_tasklet);
+	}
+	local_irq_restore(flag);
+}
+
+irqreturn_t dma_interrupt(int irq, void *dev_id)
+{
+	struct dma_channel_info *pCh;
+	int chan_no = 0;
+	int tmp;
+
+	pCh = (struct dma_channel_info *)dev_id;
+	chan_no = (int)(pCh - dma_chan);
+	if (chan_no < 0 || chan_no > 19)
+		BUG();
+
+	tmp = ifxmips_r32(IFXMIPS_DMA_IRNEN);
+	ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
+	g_ifxmips_dma_int_status |= 1 << chan_no;
+	ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN);
+	ifxmips_mask_and_ack_irq(irq);
+
+	if (!g_ifxmips_dma_in_process) {
+		g_ifxmips_dma_in_process = 1;
+		tasklet_schedule(&dma_tasklet);
+	}
+
+	return IRQ_HANDLED;
+}
+
+struct dma_device_info *dma_device_reserve(char *dev_name)
+{
+	int i;
+
+	for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
+		if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
+			if (dma_devs[i].reserved)
+				return NULL;
+			dma_devs[i].reserved = 1;
+			break;
+		}
+	}
+
+	return &dma_devs[i];
+}
+EXPORT_SYMBOL(dma_device_reserve);
+
+void dma_device_release(struct dma_device_info *dev)
+{
+	dev->reserved = 0;
+}
+EXPORT_SYMBOL(dma_device_release);
+
+void dma_device_register(struct dma_device_info *dev)
+{
+	int i, j;
+	int chan_no = 0;
+	u8 *buffer;
+	int byte_offset;
+	unsigned long flag;
+	struct dma_device_info *pDev;
+	struct dma_channel_info *pCh;
+	struct rx_desc *rx_desc_p;
+	struct tx_desc *tx_desc_p;
+
+	for (i = 0; i < dev->max_tx_chan_num; i++) {
+		pCh = dev->tx_chan[i];
+		if (pCh->control == IFXMIPS_DMA_CH_ON) {
+			chan_no = (int)(pCh - dma_chan);
+			for (j = 0; j < pCh->desc_len; j++) {
+				tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
+				memset(tx_desc_p, 0, sizeof(struct tx_desc));
+			}
+			local_irq_save(flag);
+			ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+			/* check if the descriptor length is changed */
+			if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+				ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+			while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2)
+				;
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+			ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /* reset and enable channel,enable channel later */
+			local_irq_restore(flag);
+		}
+	}
+
+	for (i = 0; i < dev->max_rx_chan_num; i++) {
+		pCh = dev->rx_chan[i];
+		if (pCh->control == IFXMIPS_DMA_CH_ON) {
+			chan_no = (int)(pCh - dma_chan);
+
+			for (j = 0; j < pCh->desc_len; j++) {
+				rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
+				pDev = (struct dma_device_info *)(pCh->dma_dev);
+				buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
+				if (!buffer)
+					break;
+
+				dma_cache_inv((unsigned long) buffer, pCh->packet_size);
+
+				rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
+				rx_desc_p->status.word = 0;
+				rx_desc_p->status.field.byte_offset = byte_offset;
+				rx_desc_p->status.field.OWN = DMA_OWN;
+				rx_desc_p->status.field.data_length = pCh->packet_size;
+			}
+
+			local_irq_save(flag);
+			ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+			/* check if the descriptor length is changed */
+			if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+				ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+			while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2)
+				;
+			ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /* fix me, should enable all the interrupts here? */
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+			ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL);
+			local_irq_restore(flag);
+			ifxmips_enable_irq(dma_chan[chan_no].irq);
+		}
+	}
+}
+EXPORT_SYMBOL(dma_device_register);
+
+void dma_device_unregister(struct dma_device_info *dev)
+{
+	int i, j;
+	int chan_no;
+	struct dma_channel_info *pCh;
+	struct rx_desc *rx_desc_p;
+	struct tx_desc *tx_desc_p;
+	unsigned long flag;
+
+	for (i = 0; i < dev->max_tx_chan_num; i++) {
+		pCh = dev->tx_chan[i];
+		if (pCh->control == IFXMIPS_DMA_CH_ON) {
+			chan_no = (int)(dev->tx_chan[i] - dma_chan);
+			local_irq_save(flag);
+			ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+			pCh->curr_desc = 0;
+			pCh->prev_desc = 0;
+			pCh->control = IFXMIPS_DMA_CH_OFF;
+			ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1)
+				;
+			local_irq_restore(flag);
+
+			for (j = 0; j < pCh->desc_len; j++) {
+				tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
+				if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
+						|| (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
+					dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
+				}
+				tx_desc_p->status.field.OWN = CPU_OWN;
+				memset(tx_desc_p, 0, sizeof(struct tx_desc));
+			}
+			/* TODO should free buffer that is not transferred by dma */
+		}
+	}
+
+	for (i = 0; i < dev->max_rx_chan_num; i++) {
+		pCh = dev->rx_chan[i];
+		chan_no = (int)(dev->rx_chan[i] - dma_chan);
+		ifxmips_disable_irq(pCh->irq);
+
+		local_irq_save(flag);
+		g_ifxmips_dma_int_status &= ~(1 << chan_no);
+		pCh->curr_desc = 0;
+		pCh->prev_desc = 0;
+		pCh->control = IFXMIPS_DMA_CH_OFF;
+
+		ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+		ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */
+		ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */
+		ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+		while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1)
+			;
+
+		local_irq_restore(flag);
+		for (j = 0; j < pCh->desc_len; j++) {
+			rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
+			if ((rx_desc_p->status.field.OWN == CPU_OWN
+			     && rx_desc_p->status.field.C)
+			    || (rx_desc_p->status.field.OWN == DMA_OWN
+				&& rx_desc_p->status.field.data_length > 0)) {
+				dev->buffer_free((u8 *)
+						 __va(rx_desc_p->Data_Pointer),
+						 (void *) pCh->opt[j]);
+			}
+		}
+	}
+}
+EXPORT_SYMBOL(dma_device_unregister);
+
+int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
+{
+	u8 *buf;
+	int len;
+	int byte_offset = 0;
+	void *p = NULL;
+	struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
+	struct rx_desc *rx_desc_p;
+
+	/* get the rx data first */
+	rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
+	if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
+		return 0;
+
+	buf = (u8 *) __va(rx_desc_p->Data_Pointer);
+	*(u32 *)dataptr = (u32)buf;
+	len = rx_desc_p->status.field.data_length;
+
+	if (opt)
+		*(int *)opt = (int)pCh->opt[pCh->curr_desc];
+
+	/* replace with a new allocated buffer */
+	buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
+
+	if (buf) {
+		dma_cache_inv((unsigned long) buf, pCh->packet_size);
+		pCh->opt[pCh->curr_desc] = p;
+		wmb();
+
+		rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
+		rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
+		wmb();
+	} else {
+		*(u32 *) dataptr = 0;
+		if (opt)
+			*(int *) opt = 0;
+		len = 0;
+	}
+
+	/* increase the curr_desc pointer */
+	pCh->curr_desc++;
+	if (pCh->curr_desc == pCh->desc_len)
+		pCh->curr_desc = 0;
+
+	return len;
+}
+EXPORT_SYMBOL(dma_device_read);
+
+int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
+{
+	unsigned long flag;
+	u32 tmp, byte_offset;
+	struct dma_channel_info *pCh;
+	int chan_no;
+	struct tx_desc *tx_desc_p;
+	local_irq_save(flag);
+
+	pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
+	chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
+
+	tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
+	while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
+		dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
+		memset(tx_desc_p, 0, sizeof(struct tx_desc));
+		pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
+		tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
+	}
+	tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
+	/* Check whether this descriptor is available */
+	if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
+		/* if not, the tell the upper layer device */
+		dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
+		local_irq_restore(flag);
+		printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
+
+		return 0;
+	}
+	pCh->opt[pCh->curr_desc] = opt;
+	/* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
+	byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
+	dma_cache_wback((unsigned long) dataptr, len);
+	wmb();
+	tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
+	wmb();
+	tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
+	wmb();
+
+	pCh->curr_desc++;
+	if (pCh->curr_desc == pCh->desc_len)
+		pCh->curr_desc = 0;
+
+	/*Check whether this descriptor is available */
+	tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
+	if (tx_desc_p->status.field.OWN == DMA_OWN) {
+		/*if not , the tell the upper layer device */
+		dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
+	}
+
+	ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+	tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL);
+
+	if (!(tmp & 1))
+		pCh->open(pCh);
+
+	local_irq_restore(flag);
+
+	return len;
+}
+EXPORT_SYMBOL(dma_device_write);
+
+int map_dma_chan(struct dma_chan_map *map)
+{
+	int i, j;
+	int result;
+
+	for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
+		strcpy(dma_devs[i].device_name, global_device_name[i]);
+
+	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
+		dma_chan[i].irq = map[i].irq;
+		result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
+		if (result) {
+			printk(KERN_WARNING "error, cannot get dma_irq!\n");
+			free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
+
+			return -EFAULT;
+		}
+	}
+
+	for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
+		dma_devs[i].num_tx_chan = 0;	/*set default tx channel number to be one */
+		dma_devs[i].num_rx_chan = 0;	/*set default rx channel number to be one */
+		dma_devs[i].max_rx_chan_num = 0;
+		dma_devs[i].max_tx_chan_num = 0;
+		dma_devs[i].buffer_alloc = &common_buffer_alloc;
+		dma_devs[i].buffer_free = &common_buffer_free;
+		dma_devs[i].intr_handler = NULL;
+		dma_devs[i].tx_burst_len = 4;
+		dma_devs[i].rx_burst_len = 4;
+		if (i == 0) {
+			ifxmips_w32(0, IFXMIPS_DMA_PS);
+			ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL);	/*enable dma drop */
+		}
+
+		if (i == 1) {
+			ifxmips_w32(1, IFXMIPS_DMA_PS);
+			ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL);	/*deu port setting */
+		}
+
+		for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
+			dma_chan[j].byte_offset = 0;
+			dma_chan[j].open = &open_chan;
+			dma_chan[j].close = &close_chan;
+			dma_chan[j].reset = &reset_chan;
+			dma_chan[j].enable_irq = &enable_ch_irq;
+			dma_chan[j].disable_irq = &disable_ch_irq;
+			dma_chan[j].rel_chan_no = map[j].rel_chan_no;
+			dma_chan[j].control = IFXMIPS_DMA_CH_OFF;
+			dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT;
+			dma_chan[j].weight = dma_chan[j].default_weight;
+			dma_chan[j].curr_desc = 0;
+			dma_chan[j].prev_desc = 0;
+		}
+
+		for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
+			if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
+				if (map[j].dir == IFXMIPS_DMA_RX) {
+					dma_chan[j].dir = IFXMIPS_DMA_RX;
+					dma_devs[i].max_rx_chan_num++;
+					dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
+					dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
+					dma_chan[j].dma_dev = (void *)&dma_devs[i];
+				} else if (map[j].dir == IFXMIPS_DMA_TX) {
+					/*TX direction */
+					dma_chan[j].dir = IFXMIPS_DMA_TX;
+					dma_devs[i].max_tx_chan_num++;
+					dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
+					dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
+					dma_chan[j].dma_dev = (void *)&dma_devs[i];
+				} else {
+					printk(KERN_WARNING "WRONG DMA MAP!\n");
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+void dma_chip_init(void)
+{
+	int i;
+
+	/* enable DMA from PMU */
+	ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
+
+	/* reset DMA */
+	ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
+
+	/* disable all interrupts */
+	ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
+
+	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
+		ifxmips_w32(i, IFXMIPS_DMA_CS);
+		ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL);
+		ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL);
+		ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
+	}
+}
+
+int ifxmips_dma_init(void)
+{
+	int i;
+
+	dma_chip_init();
+	if (map_dma_chan(default_dma_map))
+		BUG();
+
+	g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
+
+	if (g_desc_list == NULL) {
+		printk(KERN_WARNING "no memory for desriptor\n");
+		return -ENOMEM;
+	}
+
+	memset(g_desc_list, 0, PAGE_SIZE);
+
+	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
+		dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8;
+		dma_chan[i].curr_desc = 0;
+		dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
+
+		ifxmips_w32(i, IFXMIPS_DMA_CS);
+		ifxmips_w32((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
+		ifxmips_w32(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
+	}
+
+	return 0;
+}
+
+arch_initcall(ifxmips_dma_init);
+
+void dma_cleanup(void)
+{
+	int i;
+
+	free_page(KSEG0ADDR((unsigned long) g_desc_list));
+	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
+		free_irq(dma_chan[i].irq, (void  *)&dma_interrupt);
+}
+
+MODULE_LICENSE("GPL");

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/ebu.c

@@ -0,0 +1,96 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/gpio.h>
+
+#include <ifxmips.h>
+#include <ifxmips_ebu.h>
+
+#define IFXMIPS_EBU_BUSCON	0x1e7ff
+#define IFXMIPS_EBU_WP		0x80000000
+
+static int shadow = 0;
+static void __iomem *virt;
+
+static int
+ifxmips_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+	return 0;
+}
+
+static void
+ifxmips_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+	unsigned long flags;
+	if(value)
+		shadow |= (1 << offset);
+	else
+		shadow &= ~(1 << offset);
+	spin_lock_irqsave(&ebu_lock, flags);
+	ifxmips_w32(IFXMIPS_EBU_BUSCON, IFXMIPS_EBU_BUSCON1);
+	*((__u16*)virt) = shadow;
+	ifxmips_w32(IFXMIPS_EBU_BUSCON | IFXMIPS_EBU_WP, IFXMIPS_EBU_BUSCON1);
+	spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+static struct gpio_chip
+ifxmips_ebu_chip =
+{
+	.label = "ifxmips_ebu",
+	.direction_output = ifxmips_ebu_direction_output,
+	.set = ifxmips_ebu_set,
+	.base = 32,
+	.ngpio = 16,
+	.can_sleep = 1,
+	.owner = THIS_MODULE,
+};
+
+static int __devinit
+ifxmips_ebu_probe(struct platform_device *pdev)
+{
+	ifxmips_w32(pdev->resource->start | 0x1, IFXMIPS_EBU_ADDRSEL1);
+	ifxmips_w32(IFXMIPS_EBU_BUSCON | IFXMIPS_EBU_WP, IFXMIPS_EBU_BUSCON1);
+	virt = ioremap_nocache(pdev->resource->start, pdev->resource->end);
+	if(gpiochip_add(&ifxmips_ebu_chip))
+		return -EINVAL;
+	shadow = (int) pdev->dev.platform_data;
+	printk("IFXMIPS: ebu-gpio loaded\n");
+	return 0;
+}
+
+static int
+ifxmips_ebu_remove(struct platform_device *dev)
+{
+	return gpiochip_remove(&ifxmips_ebu_chip);
+}
+
+static struct platform_driver
+ifxmips_ebu_driver = {
+	.probe = ifxmips_ebu_probe,
+	.remove = ifxmips_ebu_remove,
+	.driver = {
+		.name = "ifxmips_ebu",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init
+ifxmips_ebu_init(void)
+{
+	return platform_driver_register(&ifxmips_ebu_driver);
+}
+
+static void __exit
+ifxmips_ebu_exit(void)
+{
+	platform_driver_unregister(&ifxmips_ebu_driver);
+}
+
+module_init(ifxmips_ebu_init);
+module_exit(ifxmips_ebu_exit);
+
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("ifxmips - EBU Latch GPIO-Expander");

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/irq.c

@@ -0,0 +1,233 @@
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+
+void
+ifxmips_disable_irq(unsigned int irq_nr)
+{
+	int i;
+	u32 *ier = IFXMIPS_ICU_IM0_IER;
+
+	irq_nr -= INT_NUM_IRQ0;
+	for (i = 0; i <= 4; i++)
+	{
+		if (irq_nr < INT_NUM_IM_OFFSET)
+		{
+			ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
+			return;
+		}
+		ier += IFXMIPS_ICU_OFFSET;
+		irq_nr -= INT_NUM_IM_OFFSET;
+	}
+}
+EXPORT_SYMBOL(ifxmips_disable_irq);
+
+void
+ifxmips_mask_and_ack_irq(unsigned int irq_nr)
+{
+	int i;
+	u32 *ier = IFXMIPS_ICU_IM0_IER;
+	u32 *isr = IFXMIPS_ICU_IM0_ISR;
+
+	irq_nr -= INT_NUM_IRQ0;
+	for (i = 0; i <= 4; i++)
+	{
+		if (irq_nr < INT_NUM_IM_OFFSET)
+		{
+			ifxmips_w32(ifxmips_r32(ier) & ~(1 << irq_nr), ier);
+			ifxmips_w32((1 << irq_nr), isr);
+			return;
+		}
+		ier += IFXMIPS_ICU_OFFSET;
+		isr += IFXMIPS_ICU_OFFSET;
+		irq_nr -= INT_NUM_IM_OFFSET;
+	}
+}
+EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
+
+void
+ifxmips_enable_irq(unsigned int irq_nr)
+{
+	int i;
+	u32 *ier = IFXMIPS_ICU_IM0_IER;
+
+	irq_nr -= INT_NUM_IRQ0;
+	for (i = 0; i <= 4; i++)
+	{
+		if (irq_nr < INT_NUM_IM_OFFSET)
+		{
+			ifxmips_w32(ifxmips_r32(ier) | (1 << irq_nr), ier);
+			return;
+		}
+		ier += IFXMIPS_ICU_OFFSET;
+		irq_nr -= INT_NUM_IM_OFFSET;
+	}
+}
+EXPORT_SYMBOL(ifxmips_enable_irq);
+
+static unsigned int
+ifxmips_startup_irq(unsigned int irq)
+{
+	ifxmips_enable_irq(irq);
+	return 0;
+}
+
+static void
+ifxmips_end_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+		ifxmips_enable_irq(irq);
+}
+
+static struct irq_chip
+ifxmips_irq_type = {
+	"ifxmips",
+	.startup = ifxmips_startup_irq,
+	.enable = ifxmips_enable_irq,
+	.disable = ifxmips_disable_irq,
+	.unmask = ifxmips_enable_irq,
+	.ack = ifxmips_end_irq,
+	.mask = ifxmips_disable_irq,
+	.mask_ack = ifxmips_mask_and_ack_irq,
+	.end = ifxmips_end_irq,
+};
+
+/* silicon bug causes only the msb set to 1 to be valid. all
+   other bits might be bogus */
+static inline int
+ls1bit32(unsigned long x)
+{
+	__asm__ (
+		".set push \n"
+		".set mips32 \n"
+		"clz %0, %1 \n"
+		".set pop \n"
+		: "=r" (x)
+		: "r" (x));
+	return 31 - x;
+}
+
+static void
+ifxmips_hw_irqdispatch(int module)
+{
+	u32 irq;
+
+	irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
+	if (irq == 0)
+		return;
+
+	/* we need to do this due to a silicon bug */
+	irq = ls1bit32(irq);
+	do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
+
+	if ((irq == 22) && (module == 0))
+		ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
+			IFXMIPS_EBU_PCC_ISTAT);
+}
+
+#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
+#define DEFINE_HWx_IRQDISPATCH(x) \
+static void ifxmips_hw ## x ## _irqdispatch(void)\
+{\
+	ifxmips_hw_irqdispatch(x); \
+}
+static void ifxmips_hw5_irqdispatch(void)
+{
+	do_IRQ(MIPS_CPU_TIMER_IRQ);
+}
+DEFINE_HWx_IRQDISPATCH(0)
+DEFINE_HWx_IRQDISPATCH(1)
+DEFINE_HWx_IRQDISPATCH(2)
+DEFINE_HWx_IRQDISPATCH(3)
+DEFINE_HWx_IRQDISPATCH(4)
+/*DEFINE_HWx_IRQDISPATCH(5)*/
+#endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
+
+asmlinkage void
+plat_irq_dispatch(void)
+{
+	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+	unsigned int i;
+
+	if (pending & CAUSEF_IP7)
+	{
+		do_IRQ(MIPS_CPU_TIMER_IRQ);
+		goto out;
+	} else {
+		for (i = 0; i < 5; i++)
+		{
+			if (pending & (CAUSEF_IP2 << i))
+			{
+				ifxmips_hw_irqdispatch(i);
+				goto out;
+			}
+		}
+	}
+	printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
+
+out:
+	return;
+}
+
+static struct irqaction
+cascade = {
+	.handler = no_action,
+	.flags = IRQF_DISABLED,
+	.name = "cascade",
+};
+
+void __init
+arch_init_irq(void)
+{
+	int i;
+
+	for (i = 0; i < 5; i++)
+		ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
+
+	mips_cpu_irq_init();
+
+	for (i = 2; i <= 6; i++)
+		setup_irq(i, &cascade);
+
+#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
+	if (cpu_has_vint) {
+		printk(KERN_INFO "Setting up vectored interrupts\n");
+		set_vi_handler(2, ifxmips_hw0_irqdispatch);
+		set_vi_handler(3, ifxmips_hw1_irqdispatch);
+		set_vi_handler(4, ifxmips_hw2_irqdispatch);
+		set_vi_handler(5, ifxmips_hw3_irqdispatch);
+		set_vi_handler(6, ifxmips_hw4_irqdispatch);
+		set_vi_handler(7, ifxmips_hw5_irqdispatch);
+	}
+#endif
+
+	for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
+		set_irq_chip_and_handler(i, &ifxmips_irq_type,
+			handle_level_irq);
+
+	#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
+	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
+		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+	#else
+	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
+		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+	#endif
+}
+
+void __cpuinit
+arch_fixup_c0_irqs(void)
+{
+	/* FIXME: check for CPUID and only do fix for specific chips/versions */
+	cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+	cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
+}

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/mach-arv452.c

@@ -0,0 +1,170 @@
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+
+#include <machine.h>
+#include <ifxmips_prom.h>
+
+#include "arcaydian.h"
+#include "devices.h"
+
+#define ARV452_EBU_GPIO_START	0x14000000
+#define ARV452_EBU_GPIO_SIZE	0x00001000
+
+#define ARV452_GPIO_BUTTON_RESET		14
+#define ARV452_BUTTONS_POLL_INTERVAL	20
+
+#define ARV452_LATCH_SWITCH				(1 << 10)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition arv452_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x20000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x20000,
+		.size	= 0x0,
+	},
+	{
+		.name	= "kernel",
+		.offset	= 0x0,
+		.size	= 0x0,
+	},
+	{
+		.name	= "rootfs",
+		.offset	= 0x0,
+		.size	= 0x0,
+	},
+	{
+		.name	= "board_config",
+		.offset	= 0x3f0000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "openwrt",
+		.offset	= 0x0,
+		.size	= 0x0,
+	},
+};
+#endif
+
+static struct physmap_flash_data arv452_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+	.nr_parts	= ARRAY_SIZE(arv452_partitions),
+	.parts		= arv452_partitions,
+#endif
+};
+
+static struct gpio_led
+arv452_leds_gpio[] __initdata = {
+/*
+	{ .name = "ifx0", .gpio = 0, .active_low = 1, },
+	{ .name = "ifx1", .gpio = 1, .active_low = 1, },
+	{ .name = "ifx2", .gpio = 2, .active_low = 1, },
+*/
+	{ .name = "ifx:blue:power", .gpio = 3, .active_low = 1, },
+	{ .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, },
+	{ .name = "ifx:blue:internet", .gpio = 5, .active_low = 1, },
+	{ .name = "ifx:red:power", .gpio = 6, .active_low = 1, },
+	{ .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, },
+	{ .name = "ifx:red:wps", .gpio = 9, .active_low = 1, },
+/*
+	{ .name = "ifx10", .gpio = 10, .active_low = 1, },
+	{ .name = "ifx11", .gpio = 11, .active_low = 1, },
+	{ .name = "ifx12", .gpio = 12, .active_low = 1, },
+	{ .name = "ifx13", .gpio = 13, .active_low = 1, },
+	{ .name = "ifx14", .gpio = 14, .active_low = 1, },
+	{ .name = "ifx15", .gpio = 15, .active_low = 1, },
+	{ .name = "ifx16", .gpio = 16, .active_low = 1, },
+	{ .name = "ifx17", .gpio = 17, .active_low = 1, },
+	{ .name = "ifx18", .gpio = 18, .active_low = 1, },
+	{ .name = "ifx19", .gpio = 19, .active_low = 1, },
+	{ .name = "ifx20", .gpio = 20, .active_low = 1, },
+	{ .name = "ifx21", .gpio = 21, .active_low = 1, },
+	{ .name = "ifx22", .gpio = 22, .active_low = 1, },
+	{ .name = "ifx23", .gpio = 23, .active_low = 1, },
+	{ .name = "ifx24", .gpio = 24, .active_low = 1, },
+	{ .name = "ifx25", .gpio = 25, .active_low = 1, },
+	{ .name = "ifx26", .gpio = 26, .active_low = 1, },
+	{ .name = "ifx27", .gpio = 27, .active_low = 1, },
+	{ .name = "ifx28", .gpio = 28, .active_low = 1, },
+	{ .name = "ifx29", .gpio = 29, .active_low = 1, },
+	{ .name = "ifx30", .gpio = 30, .active_low = 1, },
+	{ .name = "ifx31", .gpio = 31, .active_low = 1, },
+*/
+	{ .name = "ifx:blue:voip", .gpio = 32, .active_low = 1, },
+	{ .name = "ifx:blue:fxs1", .gpio = 33, .active_low = 1, },
+	{ .name = "ifx:blue:fxs2", .gpio = 34, .active_low = 1, },
+	{ .name = "ifx:blue:fxo", .gpio = 35, .active_low = 1, },
+	{ .name = "ifx:blue:voice", .gpio = 36, .active_low = 1, },
+	{ .name = "ifx:blue:usb", .gpio = 37, .active_low = 1, },
+	{ .name = "ifx:blue:wlan", .gpio = 38, .active_low = 1, },
+/*	{ .name = "ifx39", .gpio = 39, .active_low = 1, },
+	{ .name = "ifx40", .gpio = 40, .active_low = 1, },
+	{ .name = "ifx41", .gpio = 41, .active_low = 1, },
+	{ .name = "ifx42", .gpio = 42, .active_low = 1, },
+	{ .name = "ifx43", .gpio = 43, .active_low = 1, },
+	{ .name = "ifx44", .gpio = 44, .active_low = 1, },
+	{ .name = "ifx45", .gpio = 45, .active_low = 1, },
+	{ .name = "ifx46", .gpio = 46, .active_low = 1, },
+	{ .name = "ifx47", .gpio = 47, .active_low = 1, },
+*/
+};
+
+static struct gpio_button
+arv452_gpio_buttons[] __initdata = {
+	{
+		.desc		= "reset",
+		.type		= EV_KEY,
+		.code		= BTN_0,
+		.threshold	= 3,
+		.gpio		= ARV452_GPIO_BUTTON_RESET,
+		.active_low	= 1,
+	}
+};
+
+static struct resource arv452_ebu_resource =
+{
+	.name	= "ebu-gpio",
+	.start	= ARV452_EBU_GPIO_START,
+	.end	= ARV452_EBU_GPIO_START + ARV452_EBU_GPIO_SIZE - 1,
+	.flags	= IORESOURCE_MEM,
+};
+
+static void __init
+arv452_init(void)
+{
+	unsigned char mac[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	ifxmips_find_brn_mac(mac);
+
+	ifxmips_register_gpio();
+
+	danube_register_ebu_gpio(&arv452_ebu_resource, ARV452_LATCH_SWITCH);
+
+	ifxmips_register_mtd(&arv452_flash_data);
+
+	danube_register_pci(PCI_CLOCK_EXT, 0);
+
+	ifxmips_register_wdt();
+
+	ifxmips_register_gpio_leds(arv452_leds_gpio, ARRAY_SIZE(arv452_leds_gpio));
+
+	danube_register_ethernet(mac);
+
+	danube_register_usb();
+}
+
+MIPS_MACHINE(IFXMIPS_MACH_ARV452,
+			"ARV452",
+			"Airties WAV-281, Arcor A800",
+			arv452_init);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/mach-easy4010.c

@@ -0,0 +1,79 @@
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+
+#include <machine.h>
+#include <ifxmips_prom.h>
+
+#include "devices.h"
+
+extern unsigned char ifxmips_ethaddr[6];
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition easy4010_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x40000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x40000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "kernel",
+		.offset	= 0x0,
+		.size	= 0x0,
+	},
+	{
+		.name	= "rootfs",
+		.offset	= 0x0,
+		.size	= 0x0,
+	}
+};
+#endif
+
+static struct physmap_flash_data easy4010_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+	.nr_parts	= ARRAY_SIZE(easy4010_partitions),
+	.parts		= easy4010_partitions,
+#endif
+};
+
+static struct gpio_led easy4010_leds[] = {
+	{ .name = "ifx:green:test0", .gpio = 0,},
+	{ .name = "ifx:green:test1", .gpio = 1,},
+	{ .name = "ifx:green:test2", .gpio = 2,},
+	{ .name = "ifx:green:test3", .gpio = 3,},
+};
+
+static void __init
+easy4010_init(void)
+{
+	ifxmips_register_gpio();
+
+	ifxmips_register_gpio_dev();
+
+	ifxmips_register_mtd(&easy4010_flash_data);
+
+	ifxmips_register_leds(easy4010_leds, ARRAY_SIZE(easy4010_leds));
+
+	ifxmips_register_wdt();
+
+	danube_register_ethernet(ifxmips_ethaddr);
+
+	danube_register_usb();
+}
+
+MIPS_MACHINE(IFXMIPS_MACH_EASY4010,
+			"EASY4010",
+			"Lantiq Twinpass Eval Board",
+			easy4010_init);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/mach-easy50712.c

@@ -0,0 +1,80 @@
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+
+#include <machine.h>
+#include <ifxmips_prom.h>
+
+#include "devices.h"
+
+extern unsigned char ifxmips_ethaddr[6];
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition easy50712_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x40000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x40000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "kernel",
+		.offset	= 0x0,
+		.size	= 0x0,
+	},
+	{
+		.name	= "rootfs",
+		.offset	= 0x0,
+		.size	= 0x0,
+	}
+};
+#endif
+
+static struct physmap_flash_data easy50712_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+	.nr_parts	= ARRAY_SIZE(easy50712_partitions),
+	.parts		= easy50712_partitions,
+#endif
+};
+
+static struct gpio_led easy50712_leds[] = {
+	{ .name = "ifx:green:test0", .gpio = 0,},
+	{ .name = "ifx:green:test1", .gpio = 1,},
+	{ .name = "ifx:green:test2", .gpio = 2,},
+	{ .name = "ifx:green:test3", .gpio = 3,},
+};
+
+static void __init
+easy50712_init(void)
+{
+	ifxmips_register_gpio();
+
+	//printk("ifxmips_register_gpio_dev\n");
+	//ifxmips_register_gpio_dev();
+
+	ifxmips_register_mtd(&easy50712_flash_data);
+
+	ifxmips_register_leds(easy50712_leds, ARRAY_SIZE(easy50712_leds));
+
+	ifxmips_register_wdt();
+
+	danube_register_ethernet(ifxmips_ethaddr);
+
+	danube_register_usb();
+}
+
+MIPS_MACHINE(IFXMIPS_MACH_EASY50712,
+			"EASY50712",
+			"Lantiq Eval Board",
+			easy50712_init);

target/linux/ifxmips/files-2.6.32/arch/mips/ifxmips/danube/setup.c

@@ -0,0 +1,96 @@
+#include <linux/cpu.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pm.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <ifxmips.h>
+#include <ifxmips_cgu.h>
+
+#define SYSTEM_DANUBE			"Danube"
+#define SYSTEM_DANUBE_CHIPID1	0x00129083
+#define SYSTEM_DANUBE_CHIPID2	0x0012B083
+
+#define SYSTEM_TWINPASS			"Twinpass"
+#define SYSTEM_TWINPASS_CHIPID	0x0012D083
+
+static unsigned int chiprev = 0;
+unsigned char ifxmips_sys_type[IFXMIPS_SYS_TYPE_LEN];
+
+unsigned int
+ifxmips_get_cpu_ver(void)
+{
+	return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0xF0000000) >> 28;
+}
+EXPORT_SYMBOL(ifxmips_get_cpu_ver);
+
+const char*
+get_system_type(void)
+{
+	return ifxmips_sys_type;
+}
+
+static void
+ifxmips_machine_restart(char *command)
+{
+	printk(KERN_NOTICE "System restart\n");
+	local_irq_disable();
+	ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL,
+		IFXMIPS_RCU_RST);
+	for(;;);
+}
+
+static void
+ifxmips_machine_halt(void)
+{
+	printk(KERN_NOTICE "System halted.\n");
+	local_irq_disable();
+	for(;;);
+}
+
+static void
+ifxmips_machine_power_off(void)
+{
+	printk(KERN_NOTICE "Please turn off the power now.\n");
+	local_irq_disable();
+	for(;;);
+}
+
+void __init
+ifxmips_soc_setup(void)
+{
+	char *name = SYSTEM_DANUBE;
+	ioport_resource.start = IOPORT_RESOURCE_START;
+	ioport_resource.end = IOPORT_RESOURCE_END;
+	iomem_resource.start = IOMEM_RESOURCE_START;
+	iomem_resource.end = IOMEM_RESOURCE_END;
+
+	_machine_restart = ifxmips_machine_restart;
+	_machine_halt = ifxmips_machine_halt;
+	pm_power_off = ifxmips_machine_power_off;
+
+	chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF);
+
+	switch (chiprev)
+	{
+	case SYSTEM_DANUBE_CHIPID1:
+	case SYSTEM_DANUBE_CHIPID2:
+		name = SYSTEM_DANUBE;
+		break;
+
+	case SYSTEM_TWINPASS_CHIPID:
+		name = SYSTEM_TWINPASS;
+		break;
+
+	default:
+		printk(KERN_ERR "This is not a danube chiprev : 0x%08X\n", chiprev);
+		BUG();
+		break;
+	}
+	snprintf(ifxmips_sys_type, IFXMIPS_SYS_TYPE_LEN - 1, "%s rev1.%d %dMhz",
+		name, ifxmips_get_cpu_ver(),
+		ifxmips_get_cpu_hz() / 1000000);
+	ifxmips_sys_type[IFXMIPS_SYS_TYPE_LEN - 1] = '\0';
+}