qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-11-28 14:22:48 +02:00
Code

Fix issues form previous commit...

Browse Source
This commit is contained in:
Lars-Peter Clausen 2009-11-21 03:14:20 +01:00
parent 0c0247d223
commit 145c533ec2
3 changed files with 3 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
target/linux/xburst/files-2.6.31/arch/mips/include/asm/jzsoc.h
View File

@ -1,26 +0,0 @@
/*
* linux/include/asm-mips/jzsoc.h
*
* Ingenic's JZXXXX SoC common include.
*
* Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
*
* Author: <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_JZSOC_H__
#define __ASM_JZSOC_H__
/*
* SoC include
*/
#ifdef CONFIG_SOC_JZ4740
#include <asm/mach-jz4740/jz4740.h>
#endif
#endif /* __ASM_JZSOC_H__ */

2
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h
View File

@ -59,7 +59,7 @@
*/
#define MSC_WP_PIN GPIO_SD_WP
#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N)
#define MSC_HOTPLUG_IRQ (JZ_IRQ_GPIO(GPIO_SD_CD_N))
#define __msc_init_io() \
do { \

13
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/irq.h
View File

@ -1,15 +1,7 @@
#ifndef __JZ4740_IRQ_H__
#define __JZ4740_IRQ_H__
/*
* JZ4740 irqs.
*
* Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define MIPS_CPU_IRQ_BASE 0
#define JZ_IRQ_BASE 8
// 1st-level interrupts
@ -39,10 +31,9 @@
/* 2nd-level interrupts */
#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
#define JZ_IRQ_GPIO_0 JZ_IRQ(48) /* 48 to 175 for GPIO pin 0 to 127 */
#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
#define JZ_IRQ_GPIO(x) ((x) + JZ_IRQ(48)
#define JZ_IRQ_GPIO(x) (JZ_IRQ(48) + (x))
#define NR_IRQS (JZ_IRQ_GPIO(127) + 1)