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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
[xburst] Cleanup clock module a bit and replace last users of __cpm_*
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19281 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
lars
@@ -17,282 +17,16 @@
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#include <asm/mach-jz4740/regs.h>
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/***************************************************************************
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* CPM
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***************************************************************************/
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#define __cpm_get_pllm() \
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((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
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#define __cpm_get_plln() \
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((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
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#define __cpm_get_pllod() \
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((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
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#define __cpm_get_cdiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
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#define __cpm_get_hdiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
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#define __cpm_get_pdiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
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#define __cpm_get_mdiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
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#define __cpm_get_ldiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
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#define __cpm_get_udiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
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#define __cpm_get_i2sdiv() \
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((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
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#define __cpm_get_pixdiv() \
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((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
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#define __cpm_get_mscdiv() \
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((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
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#define __cpm_get_uhcdiv() \
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((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT)
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#define __cpm_get_ssidiv() \
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((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
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#define __cpm_set_cdiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
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#define __cpm_set_hdiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
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#define __cpm_set_pdiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
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#define __cpm_set_mdiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
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#define __cpm_set_ldiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
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#define __cpm_set_udiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
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#define __cpm_set_i2sdiv(v) \
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(REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
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#define __cpm_set_pixdiv(v) \
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(REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
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#define __cpm_set_mscdiv(v) \
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(REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
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#define __cpm_set_uhcdiv(v) \
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(REG_CPM_UHCCDR = (REG_CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | ((v) << (CPM_UHCCDR_UHCDIV_BIT)))
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#define __cpm_ssiclk_select_exclk() \
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(REG_CPM_SSICDR &= ~CPM_SSICDR_SCS)
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#define __cpm_ssiclk_select_pllout() \
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(REG_CPM_SSICDR |= CPM_SSICDR_SCS)
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#define __cpm_set_ssidiv(v) \
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(REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
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#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
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#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
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#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
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#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
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#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
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#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
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#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
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#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
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#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
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#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
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#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
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#define __cpm_get_cclk_doze_duty() \
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((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
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#define __cpm_set_cclk_doze_duty(v) \
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(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
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#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
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#define __cpm_idle_mode() \
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(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
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#define __cpm_sleep_mode() \
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(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
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#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
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#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
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#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
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#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
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#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
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#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
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#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
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#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
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#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
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#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
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#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
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#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
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#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
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#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
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#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
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#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
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#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
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#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
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#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
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#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
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#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
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#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
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#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
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#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
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#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
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#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
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#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
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#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
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#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
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#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
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#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
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#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
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#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
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#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
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#define __cpm_get_o1st() \
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((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
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#define __cpm_set_o1st(v) \
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(REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
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#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
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#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
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/*
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* JZ4740 clocks structure
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*/
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typedef struct {
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unsigned int cclk; /* CPU clock */
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unsigned int hclk; /* System bus clock */
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unsigned int pclk; /* Peripheral bus clock */
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unsigned int mclk; /* Flash/SRAM/SDRAM clock */
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unsigned int lcdclk; /* LCDC module clock */
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unsigned int pixclk; /* LCD pixel clock */
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unsigned int i2sclk; /* AIC module clock */
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unsigned int usbclk; /* USB module clock */
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unsigned int mscclk; /* MSC module clock */
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unsigned int extalclk; /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
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unsigned int rtcclk; /* RTC clock for CPM,INTC,RTC,TCU,WDT */
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} jz_clocks_t;
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extern jz_clocks_t jz_clocks;
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/* PLL output frequency */
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static __inline__ unsigned int __cpm_get_pllout(void)
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enum jz4740_wait_mode
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{
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unsigned long m, n, no, pllout;
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unsigned long cppcr = REG_CPM_CPPCR;
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unsigned long od[4] = {1, 2, 2, 4};
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if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
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m = __cpm_get_pllm() + 2;
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n = __cpm_get_plln() + 2;
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no = od[__cpm_get_pllod()];
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pllout = ((JZ_EXTAL) / (n * no)) * m;
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} else
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pllout = JZ_EXTAL;
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return pllout;
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}
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/* PLL output frequency for MSC/I2S/LCD/USB */
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static __inline__ unsigned int __cpm_get_pllout2(void)
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{
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if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
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return __cpm_get_pllout();
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else
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return __cpm_get_pllout()/2;
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}
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/* CPU core clock */
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static __inline__ unsigned int __cpm_get_cclk(void)
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{
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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return __cpm_get_pllout() / div[__cpm_get_cdiv()];
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}
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/* AHB system bus clock */
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static __inline__ unsigned int __cpm_get_hclk(void)
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{
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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return __cpm_get_pllout() / div[__cpm_get_hdiv()];
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}
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/* Memory bus clock */
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static __inline__ unsigned int __cpm_get_mclk(void)
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{
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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return __cpm_get_pllout() / div[__cpm_get_mdiv()];
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}
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/* APB peripheral bus clock */
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static __inline__ unsigned int __cpm_get_pclk(void)
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{
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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return __cpm_get_pllout() / div[__cpm_get_pdiv()];
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}
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/* LCDC module clock */
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static __inline__ unsigned int __cpm_get_lcdclk(void)
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{
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return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
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}
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/* LCD pixel clock */
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static __inline__ unsigned int __cpm_get_pixclk(void)
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{
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return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
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}
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/* I2S clock */
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static __inline__ unsigned int __cpm_get_i2sclk(void)
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{
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if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
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return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
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}
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else {
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return JZ_EXTAL;
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}
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}
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/* USB clock */
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static __inline__ unsigned int __cpm_get_usbclk(void)
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{
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if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
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return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
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}
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else {
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return JZ_EXTAL;
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}
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}
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/* MSC clock */
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static __inline__ unsigned int __cpm_get_mscclk(void)
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{
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return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
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}
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/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
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static __inline__ unsigned int __cpm_get_extalclk(void)
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{
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return JZ_EXTAL;
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}
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/* RTC clock for CPM,INTC,RTC,TCU,WDT */
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static __inline__ unsigned int __cpm_get_rtcclk(void)
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{
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return JZ_EXTAL_RTC;
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}
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/*
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* Output 24MHz for SD and 16MHz for MMC.
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*/
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static inline void __cpm_select_msc_clk(int sd)
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{
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unsigned int pllout2 = __cpm_get_pllout2();
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unsigned int div = 0;
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if (sd) {
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div = pllout2 / 24000000;
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}
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else {
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div = pllout2 / 16000000;
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}
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REG_CPM_MSCCDR = div - 1;
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}
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JZ4740_WAIT_MODE_IDLE,
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JZ4740_WAIT_MODE_SLEEP,
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};
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int jz_init_clocks(unsigned long ext_rate);
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void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
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void jz4740_clock_udc_enable_auto_suspend(void);
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void jz4740_clock_udc_disable_auto_suspend(void);
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#endif /* __ASM_JZ4740_CLOCK_H__ */
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@@ -52,162 +52,6 @@
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#define IPU_BASE 0xB3080000
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#define ETH_BASE 0xB3100000
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/*************************************************************************
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* CPM (Clock reset and Power control Management)
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*************************************************************************/
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#define CPM_CPCCR (CPM_BASE+0x00)
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#define CPM_CPPCR (CPM_BASE+0x10)
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#define CPM_I2SCDR (CPM_BASE+0x60)
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#define CPM_LPCDR (CPM_BASE+0x64)
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#define CPM_MSCCDR (CPM_BASE+0x68)
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#define CPM_UHCCDR (CPM_BASE+0x6C)
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#define CPM_SSICDR (CPM_BASE+0x74)
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#define CPM_LCR (CPM_BASE+0x04)
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#define CPM_CLKGR (CPM_BASE+0x20)
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#define CPM_SCR (CPM_BASE+0x24)
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#define CPM_HCR (CPM_BASE+0x30)
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#define CPM_HWFCR (CPM_BASE+0x34)
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#define CPM_HRCR (CPM_BASE+0x38)
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#define CPM_HWCR (CPM_BASE+0x3c)
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#define CPM_HWSR (CPM_BASE+0x40)
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#define CPM_HSPR (CPM_BASE+0x44)
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#define CPM_RSR (CPM_BASE+0x08)
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#define REG_CPM_CPCCR REG32(CPM_CPCCR)
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#define REG_CPM_CPPCR REG32(CPM_CPPCR)
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#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
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#define REG_CPM_LPCDR REG32(CPM_LPCDR)
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#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
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#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
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#define REG_CPM_SSICDR REG32(CPM_SSICDR)
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#define REG_CPM_LCR REG32(CPM_LCR)
|
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#define REG_CPM_CLKGR REG32(CPM_CLKGR)
|
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#define REG_CPM_SCR REG32(CPM_SCR)
|
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#define REG_CPM_HCR REG32(CPM_HCR)
|
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#define REG_CPM_HWFCR REG32(CPM_HWFCR)
|
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#define REG_CPM_HRCR REG32(CPM_HRCR)
|
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#define REG_CPM_HWCR REG32(CPM_HWCR)
|
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#define REG_CPM_HWSR REG32(CPM_HWSR)
|
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#define REG_CPM_HSPR REG32(CPM_HSPR)
|
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|
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#define REG_CPM_RSR REG32(CPM_RSR)
|
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|
||||
/* Clock Control Register */
|
||||
#define CPM_CPCCR_I2CS (1 << 31)
|
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#define CPM_CPCCR_CLKOEN (1 << 30)
|
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#define CPM_CPCCR_UCS (1 << 29)
|
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#define CPM_CPCCR_UDIV_BIT 23
|
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#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
|
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#define CPM_CPCCR_CE (1 << 22)
|
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#define CPM_CPCCR_PCS (1 << 21)
|
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#define CPM_CPCCR_LDIV_BIT 16
|
||||
#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
|
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#define CPM_CPCCR_MDIV_BIT 12
|
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#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
|
||||
#define CPM_CPCCR_PDIV_BIT 8
|
||||
#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
|
||||
#define CPM_CPCCR_HDIV_BIT 4
|
||||
#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
|
||||
#define CPM_CPCCR_CDIV_BIT 0
|
||||
#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
|
||||
|
||||
/* I2S Clock Divider Register */
|
||||
#define CPM_I2SCDR_I2SDIV_BIT 0
|
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#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
|
||||
|
||||
/* LCD Pixel Clock Divider Register */
|
||||
#define CPM_LPCDR_PIXDIV_BIT 0
|
||||
#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
|
||||
|
||||
/* MSC Clock Divider Register */
|
||||
#define CPM_MSCCDR_MSCDIV_BIT 0
|
||||
#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
|
||||
|
||||
/* UHC Clock Divider Register */
|
||||
#define CPM_UHCCDR_UHCDIV_BIT 0
|
||||
#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
|
||||
|
||||
/* SSI Clock Divider Register */
|
||||
#define CPM_SSICDR_SCS (1<<31) /* SSI clock source selection, 0:EXCLK, 1: PLL */
|
||||
#define CPM_SSICDR_SSIDIV_BIT 0
|
||||
#define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT)
|
||||
|
||||
/* PLL Control Register */
|
||||
#define CPM_CPPCR_PLLM_BIT 23
|
||||
#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
|
||||
#define CPM_CPPCR_PLLN_BIT 18
|
||||
#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
|
||||
#define CPM_CPPCR_PLLOD_BIT 16
|
||||
#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
|
||||
#define CPM_CPPCR_PLLS (1 << 10)
|
||||
#define CPM_CPPCR_PLLBP (1 << 9)
|
||||
#define CPM_CPPCR_PLLEN (1 << 8)
|
||||
#define CPM_CPPCR_PLLST_BIT 0
|
||||
#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
|
||||
|
||||
/* Low Power Control Register */
|
||||
#define CPM_LCR_DOZE_DUTY_BIT 3
|
||||
#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
|
||||
#define CPM_LCR_DOZE_ON (1 << 2)
|
||||
#define CPM_LCR_LPM_BIT 0
|
||||
#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
|
||||
#define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
|
||||
#define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
|
||||
|
||||
/* Clock Gate Register */
|
||||
#define CPM_CLKGR_UART1 (1 << 15)
|
||||
#define CPM_CLKGR_UHC (1 << 14)
|
||||
#define CPM_CLKGR_IPU (1 << 13)
|
||||
#define CPM_CLKGR_DMAC (1 << 12)
|
||||
#define CPM_CLKGR_UDC (1 << 11)
|
||||
#define CPM_CLKGR_LCD (1 << 10)
|
||||
#define CPM_CLKGR_CIM (1 << 9)
|
||||
#define CPM_CLKGR_SADC (1 << 8)
|
||||
#define CPM_CLKGR_MSC (1 << 7)
|
||||
#define CPM_CLKGR_AIC1 (1 << 6)
|
||||
#define CPM_CLKGR_AIC2 (1 << 5)
|
||||
#define CPM_CLKGR_SSI (1 << 4)
|
||||
#define CPM_CLKGR_I2C (1 << 3)
|
||||
#define CPM_CLKGR_RTC (1 << 2)
|
||||
#define CPM_CLKGR_TCU (1 << 1)
|
||||
#define CPM_CLKGR_UART0 (1 << 0)
|
||||
|
||||
/* Sleep Control Register */
|
||||
#define CPM_SCR_O1ST_BIT 8
|
||||
#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
|
||||
#define CPM_SCR_USBPHY_ENABLE (1 << 6)
|
||||
#define CPM_SCR_OSC_ENABLE (1 << 4)
|
||||
|
||||
/* Hibernate Control Register */
|
||||
#define CPM_HCR_PD (1 << 0)
|
||||
|
||||
/* Wakeup Filter Counter Register in Hibernate Mode */
|
||||
#define CPM_HWFCR_TIME_BIT 0
|
||||
#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
|
||||
|
||||
/* Reset Counter Register in Hibernate Mode */
|
||||
#define CPM_HRCR_TIME_BIT 0
|
||||
#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
|
||||
|
||||
/* Wakeup Control Register in Hibernate Mode */
|
||||
#define CPM_HWCR_WLE_LOW (0 << 2)
|
||||
#define CPM_HWCR_WLE_HIGH (1 << 2)
|
||||
#define CPM_HWCR_PIN_WAKEUP (1 << 1)
|
||||
#define CPM_HWCR_RTC_WAKEUP (1 << 0)
|
||||
|
||||
/* Wakeup Status Register in Hibernate Mode */
|
||||
#define CPM_HWSR_WSR_PIN (1 << 1)
|
||||
#define CPM_HWSR_WSR_RTC (1 << 0)
|
||||
|
||||
/* Reset Status Register */
|
||||
#define CPM_RSR_HR (1 << 2)
|
||||
#define CPM_RSR_WR (1 << 1)
|
||||
#define CPM_RSR_PR (1 << 0)
|
||||
|
||||
/*************************************************************************
|
||||
* UART
|
||||
*************************************************************************/
|
||||
|
||||
Reference in New Issue
Block a user