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strip the kernel version suffix from target directories, except for brcm-2.4 (the -2.4 will be included in the board name here). CONFIG_LINUX_<ver>_<board> becomes CONFIG_TARGET_<board>, same for profiles.

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8653 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
2007-09-06 16:27:37 +00:00
parent 5389989aba
commit 17c7b6c3fd
701 changed files with 48 additions and 105 deletions
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16
target/linux/ar7/files/arch/mips/ar7/Makefile Normal file
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@@ -0,0 +1,16 @@
obj-y := \
prom.o \
setup.o \
memory.o \
irq.o \
time.o \
platform.o \
gpio.o \
clock.o \
vlynq.o
obj-$(CONFIG_PCI) += \
vlynq-pci.o
EXTRA_AFLAGS := $(CFLAGS)

470
target/linux/ar7/files/arch/mips/ar7/clock.c Normal file
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@@ -0,0 +1,470 @@
/*
* $Id$
*
* Copyright (C) 2007 OpenWrt.org
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/ar7/ar7.h>
#define BOOT_PLL_SOURCE_MASK 0x3
#define CPU_PLL_SOURCE_SHIFT 16
#define BUS_PLL_SOURCE_SHIFT 14
#define USB_PLL_SOURCE_SHIFT 18
#define DSP_PLL_SOURCE_SHIFT 22
#define BOOT_PLL_SOURCE_AFE 0
#define BOOT_PLL_SOURCE_BUS 0
#define BOOT_PLL_SOURCE_REF 1
#define BOOT_PLL_SOURCE_XTAL 2
#define BOOT_PLL_SOURCE_CPU 3
#define BOOT_PLL_BYPASS 0x00000020
#define BOOT_PLL_ASYNC_MODE 0x02000000
#define BOOT_PLL_2TO1_MODE 0x00008000
#define TNETD7200_CLOCK_ID_CPU 0
#define TNETD7200_CLOCK_ID_DSP 1
#define TNETD7200_CLOCK_ID_USB 2
#define TNETD7200_DEF_CPU_CLK 211000000
#define TNETD7200_DEF_DSP_CLK 125000000
#define TNETD7200_DEF_USB_CLK 48000000
struct tnetd7300_clock {
volatile u32 ctrl;
#define PREDIV_MASK 0x001f0000
#define PREDIV_SHIFT 16
#define POSTDIV_MASK 0x0000001f
u32 unused1[3];
volatile u32 pll;
#define MUL_MASK 0x0000f000
#define MUL_SHIFT 12
#define PLL_MODE_MASK 0x00000001
#define PLL_NDIV 0x00000800
#define PLL_DIV 0x00000002
#define PLL_STATUS 0x00000001
u32 unused2[3];
} __attribute__ ((packed));
struct tnetd7300_clocks {
struct tnetd7300_clock bus;
struct tnetd7300_clock cpu;
struct tnetd7300_clock usb;
struct tnetd7300_clock dsp;
} __attribute__ ((packed));
struct tnetd7200_clock {
volatile u32 ctrl;
u32 unused1[3];
#define DIVISOR_ENABLE_MASK 0x00008000
volatile u32 mul;
volatile u32 prediv;
volatile u32 postdiv;
volatile u32 postdiv2;
u32 unused2[6];
volatile u32 cmd;
volatile u32 status;
volatile u32 cmden;
u32 padding[15];
} __attribute__ ((packed));
struct tnetd7200_clocks {
struct tnetd7200_clock cpu;
struct tnetd7200_clock dsp;
struct tnetd7200_clock usb;
} __attribute__ ((packed));
int ar7_cpu_clock = 150000000;
EXPORT_SYMBOL(ar7_cpu_clock);
int ar7_bus_clock = 125000000;
EXPORT_SYMBOL(ar7_bus_clock);
int ar7_dsp_clock = 0;
EXPORT_SYMBOL(ar7_dsp_clock);
static int gcd(int a, int b)
{
int c;
if (a < b) {
c = a;
a = b;
b = c;
}
while ((c = (a % b))) {
a = b;
b = c;
}
return b;
}
static void approximate(int base, int target, int *prediv,
int *postdiv, int *mul)
{
int i, j, k, freq, res = target;
for (i = 1; i <= 16; i++) {
for (j = 1; j <= 32; j++) {
for (k = 1; k <= 32; k++) {
freq = abs(base / j * i / k - target);
if (freq < res) {
res = freq;
*mul = i;
*prediv = j;
*postdiv = k;
}
}
}
}
}
static void calculate(int base, int target, int *prediv, int *postdiv,
int *mul)
{
int tmp_gcd, tmp_base, tmp_freq;
for (*prediv = 1; *prediv <= 32; (*prediv)++) {
tmp_base = base / *prediv;
tmp_gcd = gcd(target, tmp_base);
*mul = target / tmp_gcd;
*postdiv = tmp_base / tmp_gcd;
if ((*mul < 1) || (*mul >= 16))
continue;
if ((*postdiv > 0) & (*postdiv <= 32))
break;
}
if (base / (*prediv) * (*mul) / (*postdiv) != target) {
approximate(base, target, prediv, postdiv, mul);
tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
printk(KERN_WARNING
"Adjusted requested frequency %d to %d\n",
target, tmp_freq);
}
printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
*prediv, *postdiv, *mul);
}
static int tnetd7300_dsp_clock(void)
{
u32 didr1, didr2;
u8 rev = ar7_chip_rev();
didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
if (didr2 & (1 << 23))
return 0;
if ((rev >= 0x23) && (rev != 0x57))
return 250000000;
if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
> 4208000)
return 250000000;
return 0;
}
static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
u32 *bootcr, u32 bus_clock)
{
int product;
int base_clock = AR7_REF_CLOCK;
u32 ctrl = clock->ctrl;
u32 pll = clock->pll;
int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
int postdiv = (ctrl & POSTDIV_MASK) + 1;
int divisor = prediv * postdiv;
int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
case BOOT_PLL_SOURCE_BUS:
base_clock = bus_clock;
break;
case BOOT_PLL_SOURCE_REF:
base_clock = AR7_REF_CLOCK;
break;
case BOOT_PLL_SOURCE_XTAL:
base_clock = AR7_XTAL_CLOCK;
break;
case BOOT_PLL_SOURCE_CPU:
base_clock = ar7_cpu_clock;
break;
}
if (*bootcr & BOOT_PLL_BYPASS)
return base_clock / divisor;
if ((pll & PLL_MODE_MASK) == 0)
return (base_clock >> (mul / 16 + 1)) / divisor;
if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
product = (mul & 1) ?
(base_clock * mul) >> 1 :
(base_clock * (mul - 1)) >> 2;
return product / divisor;
}
if (mul == 16)
return base_clock / divisor;
return base_clock * mul / divisor;
}
static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
u32 *bootcr, u32 frequency)
{
u32 status;
int prediv, postdiv, mul;
int base_clock = ar7_bus_clock;
switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
case BOOT_PLL_SOURCE_BUS:
base_clock = ar7_bus_clock;
break;
case BOOT_PLL_SOURCE_REF:
base_clock = AR7_REF_CLOCK;
break;
case BOOT_PLL_SOURCE_XTAL:
base_clock = AR7_XTAL_CLOCK;
break;
case BOOT_PLL_SOURCE_CPU:
base_clock = ar7_cpu_clock;
break;
}
calculate(base_clock, frequency, &prediv, &postdiv, &mul);
clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
mdelay(1);
clock->pll = 4;
do {
status = clock->pll;
} while (status & PLL_STATUS);
clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
mdelay(75);
}
static void __init tnetd7300_init_clocks(void)
{
u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
struct tnetd7300_clocks *clocks = (struct tnetd7300_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x20, sizeof(struct tnetd7300_clocks));
ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
&clocks->bus, bootcr, AR7_AFE_CLOCK);
if (*bootcr & BOOT_PLL_ASYNC_MODE) {
ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
&clocks->cpu, bootcr, AR7_AFE_CLOCK);
} else {
ar7_cpu_clock = ar7_bus_clock;
}
#if 0
tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
bootcr, 48000000);
#endif
if (ar7_dsp_clock == 250000000)
tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
bootcr, ar7_dsp_clock);
iounmap(clocks);
iounmap(bootcr);
}
static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
u32 *bootcr, u32 bus_clock)
{
int divisor = ((clock->prediv & 0x1f) + 1) *
((clock->postdiv & 0x1f) + 1);
if (*bootcr & BOOT_PLL_BYPASS)
return base / divisor;
return base * ((clock->mul & 0xf) + 1) / divisor;
}
static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
{
printk("Clocks: base = %d, frequency = %u, prediv = %d, postdiv = %d, postdiv2 = %d, mul = %d\n",
base, frequency, prediv, postdiv, postdiv2, mul);
clock->ctrl = 0;
clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
clock->mul = ((mul - 1) & 0xF);
for(mul = 0; mul < 2000; mul++) /* nop */;
while(clock->status & 0x1) /* nop */;
clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
clock->cmden |= 1;
clock->cmd |= 1;
while(clock->status & 0x1) /* nop */;
clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
clock->cmden |= 1;
clock->cmd |= 1;
while(clock->status & 0x1) /* nop */;
clock->ctrl |= 1;
}
static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
{
if (*bootcr & BOOT_PLL_ASYNC_MODE) {
// Async
switch (clock_id) {
case TNETD7200_CLOCK_ID_DSP:
return AR7_REF_CLOCK;
default:
return AR7_AFE_CLOCK;
}
} else {
// Sync
if (*bootcr & BOOT_PLL_2TO1_MODE) {
// 2:1
switch (clock_id) {
case TNETD7200_CLOCK_ID_DSP:
return AR7_REF_CLOCK;
default:
return AR7_AFE_CLOCK;
}
} else {
// 1:1
return AR7_REF_CLOCK;
}
}
}
static void __init tnetd7200_init_clocks(void)
{
u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
struct tnetd7200_clocks *clocks = (struct tnetd7200_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x80, sizeof(struct tnetd7200_clocks));
int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
int usb_base, usb_mul, usb_prediv, usb_postdiv;
/*
Log from Fritz!Box 7170 Annex B:
CPU revision is: 00018448
Clocks: Async mode
Clocks: Setting DSP clock
Clocks: prediv: 1, postdiv: 1, mul: 5
Clocks: base = 25000000, frequency = 125000000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
Clocks: Setting CPU clock
Adjusted requested frequency 211000000 to 211968000
Clocks: prediv: 1, postdiv: 1, mul: 6
Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
Clocks: Setting USB clock
Adjusted requested frequency 48000000 to 48076920
Clocks: prediv: 13, postdiv: 1, mul: 5
Clocks: base = 125000000, frequency = 48000000, prediv = 13, postdiv = 1, postdiv2 = -1, mul = 5
DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination, driver hung on startup.
Haven't tested this on a synchronous board, neither do i know what to do with ar7_dsp_clock
*/
cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
if (*bootcr & BOOT_PLL_ASYNC_MODE) {
printk("Clocks: Async mode\n");
printk("Clocks: Setting DSP clock\n");
calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
tnetd7200_set_clock(dsp_base, &clocks->dsp,
dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
ar7_bus_clock);
printk("Clocks: Setting CPU clock\n");
calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
tnetd7200_set_clock(cpu_base, &clocks->cpu,
cpu_prediv, cpu_postdiv, -1, cpu_mul,
ar7_cpu_clock);
} else {
if (*bootcr & BOOT_PLL_2TO1_MODE) {
printk("Clocks: Sync 2:1 mode\n");
printk("Clocks: Setting CPU clock\n");
calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
tnetd7200_set_clock(cpu_base, &clocks->cpu,
cpu_prediv, cpu_postdiv, -1, cpu_mul,
ar7_cpu_clock);
printk("Clocks: Setting DSP clock\n");
calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
ar7_bus_clock = ar7_cpu_clock / 2;
tnetd7200_set_clock(dsp_base, &clocks->dsp,
dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
ar7_bus_clock);
} else {
printk("Clocks: Sync 1:1 mode\n");
printk("Clocks: Setting DSP clock\n");
calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
tnetd7200_set_clock(dsp_base, &clocks->dsp,
dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
ar7_bus_clock);
ar7_cpu_clock = ar7_bus_clock;
}
}
printk("Clocks: Setting USB clock\n");
usb_base = ar7_bus_clock;
calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, &usb_postdiv, &usb_mul);
tnetd7200_set_clock(usb_base, &clocks->usb,
usb_prediv, usb_postdiv, -1, usb_mul,
TNETD7200_DEF_USB_CLK);
#warning FIXME: ????! Hrmm
ar7_dsp_clock = ar7_cpu_clock;
iounmap(clocks);
iounmap(bootcr);
}
void __init ar7_init_clocks(void)
{
switch (ar7_chip_id()) {
case AR7_CHIP_7100:
#warning FIXME: Check if the new 7200 clock init works for 7100
tnetd7200_init_clocks();
break;
case AR7_CHIP_7200:
tnetd7200_init_clocks();
break;
case AR7_CHIP_7300:
ar7_dsp_clock = tnetd7300_dsp_clock();
tnetd7300_init_clocks();
break;
default:
break;
}
}

56
target/linux/ar7/files/arch/mips/ar7/gpio.c Normal file
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@@ -0,0 +1,56 @@
/*
* $Id$
*
* Copyright (C) 2007 OpenWrt.org
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/ar7/ar7.h>
#include <asm/ar7/gpio.h>
static char *ar7_gpio_list[AR7_GPIO_MAX] = { 0, };
int gpio_request(unsigned gpio, char *label)
{
if (gpio >= AR7_GPIO_MAX)
return -EINVAL;
if (ar7_gpio_list[gpio])
return -EBUSY;
if (label) {
ar7_gpio_list[gpio] = label;
} else {
ar7_gpio_list[gpio] = "busy";
}
return 0;
}
EXPORT_SYMBOL(gpio_request);
void gpio_free(unsigned gpio)
{
BUG_ON(!ar7_gpio_list[gpio]);
ar7_gpio_list[gpio] = NULL;
}
EXPORT_SYMBOL(gpio_free);

205
target/linux/ar7/files/arch/mips/ar7/irq.c Normal file
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@@ -0,0 +1,205 @@
/*
* $Id$
*
* Copyright (C) 2006, 2007 OpenWrt.org
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <asm/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/ar7/ar7.h>
#define EXCEPT_OFFSET 0x80
#define PACE_OFFSET 0xA0
#define CHNLS_OFFSET 0x200
#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
#define PIR_OFFSET (0x40)
#define MSR_OFFSET (0x44)
#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
#define REG(addr) (*(volatile u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
static void ar7_unmask_irq(unsigned int irq_nr);
static void ar7_mask_irq(unsigned int irq_nr);
static void ar7_unmask_secondary_irq(unsigned int irq_nr);
static void ar7_mask_secondary_irq(unsigned int irq_nr);
static irqreturn_t ar7_cascade(int interrupt, void *dev);
static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev);
static void ar7_irq_init(int base);
static int ar7_irq_base;
static struct irq_chip ar7_irq_type = {
.typename = "AR7",
.name = "AR7",
.unmask = ar7_unmask_irq,
.mask = ar7_mask_irq,
};
static struct irq_chip ar7_secondary_irq_type = {
.name = "AR7",
.unmask = ar7_unmask_secondary_irq,
.mask = ar7_mask_secondary_irq,
};
static struct irqaction ar7_cascade_action = {
.handler = ar7_cascade,
.name = "AR7 cascade interrupt"
};
static struct irqaction ar7_secondary_cascade_action = {
.handler = ar7_secondary_cascade,
.name = "AR7 secondary cascade interrupt"
};
static void ar7_unmask_irq(unsigned int irq)
{
unsigned long flags;
local_irq_save(flags);
/* enable the interrupt channel bit */
REG(ESR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32);
local_irq_restore(flags);
}
static void ar7_mask_irq(unsigned int irq)
{
unsigned long flags;
local_irq_save(flags);
/* disable the interrupt channel bit */
REG(ECR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32);
local_irq_restore(flags);
}
static void ar7_unmask_secondary_irq(unsigned int irq)
{
unsigned long flags;
local_irq_save(flags);
/* enable the interrupt channel bit */
REG(SEC_ESR_OFFSET) = 1 << (irq - ar7_irq_base - 40);
local_irq_restore(flags);
}
static void ar7_mask_secondary_irq(unsigned int irq)
{
unsigned long flags;
local_irq_save(flags);
/* disable the interrupt channel bit */
REG(SEC_ECR_OFFSET) = 1 << (irq - ar7_irq_base - 40);
local_irq_restore(flags);
}
void __init arch_init_irq(void) {
mips_cpu_irq_init();
ar7_irq_init(8);
}
static void __init ar7_irq_init(int base)
{
int i;
/*
Disable interrupts and clear pending
*/
REG(ECR_OFFSET(0)) = 0xffffffff;
REG(ECR_OFFSET(32)) = 0xff;
REG(SEC_ECR_OFFSET) = 0xffffffff;
REG(CR_OFFSET(0)) = 0xffffffff;
REG(CR_OFFSET(32)) = 0xff;
REG(SEC_CR_OFFSET) = 0xffffffff;
ar7_irq_base = base;
for(i = 0; i < 40; i++) {
REG(CHNL_OFFSET(i)) = i;
/* Primary IRQ's */
irq_desc[i + base].status = IRQ_DISABLED;
irq_desc[i + base].action = NULL;
irq_desc[i + base].depth = 1;
irq_desc[i + base].chip = &ar7_irq_type;
/* Secondary IRQ's */
if (i < 32) {
irq_desc[i + base + 40].status = IRQ_DISABLED;
irq_desc[i + base + 40].action = NULL;
irq_desc[i + base + 40].depth = 1;
irq_desc[i + base + 40].chip = &ar7_secondary_irq_type;
}
}
setup_irq(2, &ar7_cascade_action);
setup_irq(ar7_irq_base, &ar7_secondary_cascade_action);
set_c0_status(IE_IRQ0);
}
static irqreturn_t ar7_cascade(int interrupt, void *dev)
{
int irq;
irq = (REG(PIR_OFFSET) & 0x3F);
REG(CR_OFFSET(irq)) = 1 << (irq % 32);
do_IRQ(irq + ar7_irq_base);
return IRQ_HANDLED;
}
static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev)
{
int irq = 0, i;
unsigned long status;
status = REG(SEC_SR_OFFSET);
if (unlikely(!status)) {
spurious_interrupt();
return IRQ_NONE;
}
for (i = 0; i < 32; i++)
if (status & (i << 1)) {
irq = i + 40;
REG(SEC_CR_OFFSET) = 1 << i;
break;
}
do_IRQ(irq + ar7_irq_base);
return IRQ_HANDLED;
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
if (pending & STATUSF_IP7) /* cpu timer */
do_IRQ(7);
else if (pending & STATUSF_IP2) /* int0 hardware line */
do_IRQ(2);
else
spurious_interrupt();
}

75
target/linux/ar7/files/arch/mips/ar7/memory.c Normal file
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/*
* $Id$
*
* Copyright (C) 2007 OpenWrt.org
*
* Based on arch/mips/mm/init.c
* Copyright (C) 1994 - 2000 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/bootmem.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/pfn.h>
#include <linux/proc_fs.h>
#include <linux/string.h>
#include <linux/swap.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/sections.h>
#include <asm/mips-boards/prom.h>
static int __init memsize(void)
{
u32 size = (64 << 20);
volatile u32 *addr = (u32 *)KSEG1ADDR(0x14000000 + size - 4);
u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end));
while (addr > kernel_end) {
*addr = (u32)addr;
size >>= 1;
addr -= size >> 2;
}
do {
addr += size >> 2;
if (*addr != (u32)addr)
break;
size <<= 1;
} while (size < (64 << 20));
return size;
}
void __init prom_meminit(void)
{
unsigned long pages;
pages = memsize() >> PAGE_SHIFT;
add_memory_region(ARCH_PFN_OFFSET << PAGE_SHIFT, pages <<
PAGE_SHIFT, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
return;
}

412
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/*
* $Id$
*
* Copyright (C) 2006, 2007 OpenWrt.org
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/ioport.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/ar7/ar7.h>
#include <asm/ar7/gpio.h>
#include <asm/ar7/prom.h>
#include <asm/ar7/vlynq.h>
struct plat_vlynq_data {
struct plat_vlynq_ops ops;
int gpio_bit;
int reset_bit;
};
static int vlynq_on(struct vlynq_device *dev)
{
int result;
struct plat_vlynq_data *pdata = dev->dev.platform_data;
if ((result = gpio_request(pdata->gpio_bit, "vlynq")))
goto out;
ar7_device_reset(pdata->reset_bit);
if ((result = ar7_gpio_disable(pdata->gpio_bit)))
goto out_enabled;
if ((result = ar7_gpio_enable(pdata->gpio_bit)))
goto out_enabled;
if ((result = gpio_direction_output(pdata->gpio_bit)))
goto out_gpio_enabled;
gpio_set_value(pdata->gpio_bit, 0);
mdelay(50);
gpio_set_value(pdata->gpio_bit, 1);
mdelay(50);
return 0;
out_gpio_enabled:
ar7_gpio_disable(pdata->gpio_bit);
out_enabled:
ar7_device_disable(pdata->reset_bit);
gpio_free(pdata->gpio_bit);
out:
return result;
}
static void vlynq_off(struct vlynq_device *dev)
{
struct plat_vlynq_data *pdata = dev->dev.platform_data;
ar7_gpio_disable(pdata->gpio_bit);
gpio_free(pdata->gpio_bit);
ar7_device_disable(pdata->reset_bit);
}
static struct resource physmap_flash_resource = {
.name = "mem",
.flags = IORESOURCE_MEM,
.start = 0x10000000,
.end = 0x107fffff,
};
static struct resource cpmac_low_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_MAC0,
.end = AR7_REGS_MAC0 + 0x7FF,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 27,
.end = 27,
},
};
static struct resource cpmac_high_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_MAC1,
.end = AR7_REGS_MAC1 + 0x7FF,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 41,
.end = 41,
},
};
static struct resource vlynq_low_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_VLYNQ0,
.end = AR7_REGS_VLYNQ0 + 0xff,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 29,
.end = 29,
},
{
.name = "mem",
.flags = IORESOURCE_MEM,
.start = 0x04000000,
.end = 0x04ffffff,
},
{
.name = "devirq",
.flags = IORESOURCE_IRQ,
.start = 80,
.end = 111,
},
};
static struct resource vlynq_high_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_VLYNQ1,
.end = AR7_REGS_VLYNQ1 + 0xFF,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 33,
.end = 33,
},
{
.name = "mem",
.flags = IORESOURCE_MEM,
.start = 0x0c000000,
.end = 0x0cffffff,
},
{
.name = "devirq",
.flags = IORESOURCE_IRQ,
.start = 112,
.end = 143,
},
};
static struct physmap_flash_data physmap_flash_data = {
.width = 2,
};
static struct plat_cpmac_data cpmac_low_data = {
.reset_bit = 17,
.power_bit = 20,
.phy_mask = 0x80000000,
};
static struct plat_cpmac_data cpmac_high_data = {
.reset_bit = 21,
.power_bit = 22,
.phy_mask = 0x7fffffff,
};
static struct plat_vlynq_data vlynq_low_data = {
.ops.on = vlynq_on,
.ops.off = vlynq_off,
.reset_bit = 20,
.gpio_bit = 18,
};
static struct plat_vlynq_data vlynq_high_data = {
.ops.on = vlynq_on,
.ops.off = vlynq_off,
.reset_bit = 16,
.gpio_bit = 19,
};
static struct platform_device physmap_flash = {
.id = 0,
.name = "physmap-flash",
.dev.platform_data = &physmap_flash_data,
.resource = &physmap_flash_resource,
.num_resources = 1,
};
static struct platform_device cpmac_low = {
.id = 0,
.name = "cpmac",
.dev.platform_data = &cpmac_low_data,
.resource = cpmac_low_res,
.num_resources = ARRAY_SIZE(cpmac_low_res),
};
static struct platform_device cpmac_high = {
.id = 1,
.name = "cpmac",
.dev.platform_data = &cpmac_high_data,
.resource = cpmac_high_res,
.num_resources = ARRAY_SIZE(cpmac_high_res),
};
static struct platform_device vlynq_low = {
.id = 0,
.name = "vlynq",
.dev.platform_data = &vlynq_low_data,
.resource = vlynq_low_res,
.num_resources = ARRAY_SIZE(vlynq_low_res),
};
static struct platform_device vlynq_high = {
.id = 1,
.name = "vlynq",
.dev.platform_data = &vlynq_high_data,
.resource = vlynq_high_res,
.num_resources = ARRAY_SIZE(vlynq_high_res),
};
/* This is proper way to define uart ports, but they are then detected
* as xscale and, obviously, don't work...
*/
#if !defined(CONFIG_SERIAL_8250)
static struct plat_serial8250_port uart0_data =
{
.mapbase = AR7_REGS_UART0,
.irq = AR7_IRQ_UART0,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
};
static struct plat_serial8250_port uart1_data =
{
.mapbase = UR8_REGS_UART1,
.irq = AR7_IRQ_UART1,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
};
static struct plat_serial8250_port uart_data[] = {
uart0_data,
uart1_data,
{ .flags = 0 }
};
static struct plat_serial8250_port uart_data_single[] = {
uart0_data,
{ .flags = 0 }
};
static struct platform_device uart = {
.id = 0,
.name = "serial8250",
.dev.platform_data = uart_data_single
};
#endif
static inline unsigned char char2hex(char h)
{
switch (h) {
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
return h - '0';
case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
return h - 'A' + 10;
case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
return h - 'a' + 10;
default:
return 0;
}
}
static void cpmac_get_mac(int instance, unsigned char *dev_addr)
{
int i;
char name[5], default_mac[] = "00:00:00:12:34:56", *mac;
mac = NULL;
sprintf(name, "mac%c", 'a' + instance);
mac = prom_getenv(name);
if (!mac) {
sprintf(name, "mac%c", 'a');
mac = prom_getenv(name);
}
if (!mac)
mac = default_mac;
for (i = 0; i < 6; i++)
dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
char2hex(mac[i * 3 + 1]);
}
static int __init ar7_register_devices(void)
{
int res;
#ifdef CONFIG_SERIAL_8250
static struct uart_port uart_port[2];
memset(uart_port, 0, sizeof(struct uart_port) * 2);
uart_port[0].type = PORT_AR7;
uart_port[0].line = 0;
uart_port[0].irq = AR7_IRQ_UART0;
uart_port[0].uartclk = ar7_bus_freq() / 2;
uart_port[0].iotype = UPIO_MEM;
uart_port[0].mapbase = AR7_REGS_UART0;
uart_port[0].membase = ioremap(uart_port[0].mapbase, 256);
uart_port[0].regshift = 2;
res = early_serial_setup(&uart_port[0]);
if (res)
return res;
// Only TNETD73xx have a second serial port
if (ar7_has_second_uart()) {
uart_port[1].type = PORT_AR7;
uart_port[1].line = 1;
uart_port[1].irq = AR7_IRQ_UART1;
uart_port[1].uartclk = ar7_bus_freq() / 2;
uart_port[1].iotype = UPIO_MEM;
uart_port[1].mapbase = UR8_REGS_UART1;
uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
uart_port[1].regshift = 2;
res = early_serial_setup(&uart_port[1]);
if (res)
return res;
}
#else // !CONFIG_SERIAL_8250
uart_data[0].uartclk = ar7_bus_freq() / 2;
uart_data[1].uartclk = uart_data[0].uartclk;
// Only TNETD73xx have a second serial port
if (ar7_has_second_uart()) {
uart.dev.platform_data = uart_data;
}
res = platform_device_register(&uart);
if (res)
return res;
#endif // CONFIG_SERIAL_8250
res = platform_device_register(&physmap_flash);
if (res)
return res;
res = platform_device_register(&vlynq_low);
if (res)
return res;
ar7_device_disable(vlynq_low_data.reset_bit);
if (ar7_has_high_vlynq()) {
ar7_device_disable(vlynq_high_data.reset_bit);
res = platform_device_register(&vlynq_high);
if (res)
return res;
}
if (ar7_has_high_cpmac()) {
cpmac_get_mac(1, cpmac_high_data.dev_addr);
res = platform_device_register(&cpmac_high);
if (res)
return res;
} else {
cpmac_low_data.phy_mask = 0xffffffff;
}
cpmac_get_mac(0, cpmac_low_data.dev_addr);
res = platform_device_register(&cpmac_low);
return res;
}
arch_initcall(ar7_register_devices);

327
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/*
* $Id$
*
* Copyright (C) 2006, 2007 OpenWrt.org
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Putting things on the screen/serial line using YAMONs facilities.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/serial_reg.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/string.h>
#include <asm/io.h>
#include <asm/bootinfo.h>
#include <asm/mips-boards/prom.h>
#include <asm/gdb-stub.h>
#include <asm/ar7/ar7.h>
#include <asm/ar7/prom.h>
#define MAX_ENTRY 80
struct env_var {
char *name;
char *value;
};
static struct env_var adam2_env[MAX_ENTRY] = { { 0, }, };
char * prom_getenv(char *name)
{
int i;
for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++)
if (!strcmp(name, adam2_env[i].name))
return adam2_env[i].value;
return NULL;
}
char * __init prom_getcmdline(void)
{
return &(arcs_cmdline[0]);
}
static void __init ar7_init_cmdline(int argc, char *argv[])
{
char *cp;
int actr;
actr = 1; /* Always ignore argv[0] */
cp = &(arcs_cmdline[0]);
while(actr < argc) {
strcpy(cp, argv[actr]);
cp += strlen(argv[actr]);
*cp++ = ' ';
actr++;
}
if (cp != &(arcs_cmdline[0])) {
/* get rid of trailing space */
--cp;
*cp = '\0';
}
}
struct psbl_rec {
u32 psbl_size;
u32 env_base;
u32 env_size;
u32 ffs_base;
u32 ffs_size;
};
static __initdata char psp_env_version[] = "TIENV0.8";
struct psp_env_chunk {
u8 num;
u8 ctrl;
u16 csum;
u8 len;
char data[11];
} __attribute__ ((packed));
struct psp_var_map_entry {
u8 num;
char *value;
};
static struct psp_var_map_entry psp_var_map[] = {
{ 1, "cpufrequency" },
{ 2, "memsize" },
{ 3, "flashsize" },
{ 4, "modetty0" },
{ 5, "modetty1" },
{ 8, "maca" },
{ 9, "macb" },
{ 28, "sysfrequency" },
{ 38, "mipsfrequency" },
};
/*
Well-known variable (num is looked up in table above for matching variable name)
Example: cpufrequency=211968000
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| 01 |CTRL|CHECKSUM | 01 | _2 | _1 | _1 | _9 | _6 | _8 | _0 | _0 | _0 | \0 | FF |
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
Name=Value pair in a single chunk
Example: NAME=VALUE
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| 00 |CTRL|CHECKSUM | 01 | _N | _A | _M | _E | _0 | _V | _A | _L | _U | _E | \0 |
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
Name=Value pair in 2 chunks (len is the number of chunks)
Example: bootloaderVersion=1.3.7.15
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| 00 |CTRL|CHECKSUM | 02 | _b | _o | _o | _t | _l | _o | _a | _d | _e | _r | _V |
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| _e | _r | _s | _i | _o | _n | \0 | _1 | _. | _3 | _. | _7 | _. | _1 | _5 | \0 |
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
Data is padded with 0xFF
*/
#define PSP_ENV_SIZE 4096
static char psp_env_data[PSP_ENV_SIZE] = { 0, };
static char * __init lookup_psp_var_map(u8 num)
{
int i;
for (i = 0; i < sizeof(psp_var_map); i++)
if (psp_var_map[i].num == num)
return psp_var_map[i].value;
return NULL;
}
static void __init add_adam2_var(char *name, char *value)
{
int i;
for (i = 0; i < MAX_ENTRY; i++) {
if (!adam2_env[i].name) {
adam2_env[i].name = name;
adam2_env[i].value = value;
return;
} else if (!strcmp(adam2_env[i].name, name)) {
adam2_env[i].value = value;
return;
}
}
}
static int __init parse_psp_env(void *psp_env_base)
{
int i, n;
char *name, *value;
struct psp_env_chunk *chunks = (struct psp_env_chunk *)psp_env_data;
memcpy_fromio(chunks, psp_env_base, PSP_ENV_SIZE);
i = 1;
n = PSP_ENV_SIZE / sizeof(struct psp_env_chunk);
while (i < n) {
if ((chunks[i].num == 0xff) || ((i + chunks[i].len) > n))
break;
value = chunks[i].data;
if (chunks[i].num) {
name = lookup_psp_var_map(chunks[i].num);
} else {
name = value;
value += strlen(name) + 1;
}
if (name)
add_adam2_var(name, value);
i += chunks[i].len;
}
return 0;
}
static void __init ar7_init_env(struct env_var *env)
{
int i;
struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300));
void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
if(strcmp(psp_env, psp_env_version) == 0) {
parse_psp_env(psp_env);
} else {
for (i = 0; i < MAX_ENTRY; i++, env++)
if (env->name)
add_adam2_var(env->name, env->value);
}
}
static void __init console_config(void)
{
#ifdef CONFIG_SERIAL_8250_CONSOLE
char console_string[40];
int baud = 0;
char parity = '\0', bits = '\0', flow = '\0';
char *s, *p;
if (strstr(prom_getcmdline(), "console="))
return;
#ifdef CONFIG_KGDB
if (!strstr(prom_getcmdline(), "nokgdb"))
{
strcat(prom_getcmdline(), " console=kgdb");
kgdb_enabled = 1;
return;
}
#endif
if ((s = prom_getenv("modetty0"))) {
baud = simple_strtoul(s, &p, 10);
s = p;
if (*s == ',') s++;
if (*s) parity = *s++;
if (*s == ',') s++;
if (*s) bits = *s++;
if (*s == ',') s++;
if (*s == 'h') flow = 'r';
}
if (baud == 0)
baud = 38400;
if (parity != 'n' && parity != 'o' && parity != 'e')
parity = 'n';
if (bits != '7' && bits != '8')
bits = '8';
if (flow == '\0')
flow = 'r';
sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
parity, bits, flow);
strcat(prom_getcmdline(), console_string);
#endif
}
void __init prom_init(void)
{
ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
ar7_init_env((struct env_var *)fw_arg2);
console_config();
}
#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
static inline unsigned int serial_in(int offset)
{
return readb((void *)PORT(offset));
}
static inline void serial_out(int offset, int value)
{
writeb(value, (void *)PORT(offset));
}
char prom_getchar(void)
{
while (!(serial_in(UART_LSR) & UART_LSR_DR));
return serial_in(UART_RX);
}
int prom_putchar(char c)
{
while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0);
serial_out(UART_TX, c);
return 1;
}
// from adm5120/prom.c
void prom_printf(char *fmt, ...)
{
va_list args;
int l;
char *p, *buf_end;
char buf[1024];
va_start(args, fmt);
l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */
va_end(args);
buf_end = buf + l;
for (p = buf; p < buf_end; p++) {
/* Crude cr/nl handling is better than none */
if (*p == '\n')
prom_putchar('\r');
prom_putchar(*p);
}
}
#ifdef CONFIG_KGDB
int putDebugChar(char c)
{
return prom_putchar(c);
}
char getDebugChar(void)
{
return prom_getchar();
}
#endif
EXPORT_SYMBOL(prom_getenv);

124
target/linux/ar7/files/arch/mips/ar7/setup.c Normal file
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/*
* $Id$
*
* Copyright (C) 2006, 2007 OpenWrt.org
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/tty.h>
#include <linux/pm.h>
#include <linux/serial_8250.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/serial_reg.h>
#include <asm/cpu.h>
#include <asm/irq.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
#include <asm/dma.h>
#include <asm/time.h>
#include <asm/traps.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/ar7/ar7.h>
extern void ar7_time_init(void);
static void ar7_machine_restart(char *command);
static void ar7_machine_halt(void);
static void ar7_machine_power_off(void);
static void ar7_machine_restart(char *command)
{
volatile u32 *softres_reg = (u32 *)ioremap(AR7_REGS_RESET +
AR7_RESET_SOFTWARE, 1);
*softres_reg = 1;
}
static void ar7_machine_halt(void)
{
while (1);
}
static void ar7_machine_power_off(void)
{
volatile u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
u32 power_state = *power_reg | (3 << 30);
*power_reg = power_state;
ar7_machine_halt();
}
const char *get_system_type(void)
{
u16 chip_id = ar7_chip_id();
switch (chip_id) {
case AR7_CHIP_7300:
return "TI AR7 (TNETD7300)";
case AR7_CHIP_7100:
return "TI AR7 (TNETD7100)";
case AR7_CHIP_7200:
return "TI AR7 (TNETD7200)";
default:
return "TI AR7 (Unknown)";
}
}
static int __init ar7_init_console(void)
{
return 0;
}
/*
* Initializes basic routines and structures pointers, memory size (as
* given by the bios and saves the command line.
*/
extern void ar7_init_clocks(void);
void __init plat_mem_setup(void)
{
unsigned long io_base;
_machine_restart = ar7_machine_restart;
_machine_halt = ar7_machine_halt;
pm_power_off = ar7_machine_power_off;
board_time_init = ar7_time_init;
panic_timeout = 3;
io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
if (!io_base) panic("Can't remap IO base!\n");
set_io_port_base(io_base);
prom_meminit();
#warning FIXME: clock initialisation
ar7_init_clocks();
ioport_resource.start = 0;
ioport_resource.end = ~0;
iomem_resource.start = 0;
iomem_resource.end = ~0;
printk("%s, ID: 0x%04x, Revision: 0x%02x\n", get_system_type(),
ar7_chip_id(), ar7_chip_rev());
}
console_initcall(ar7_init_console);

59
target/linux/ar7/files/arch/mips/ar7/time.c Normal file
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/*
* $Id$
*
* Copyright (C) 2006, 2007 OpenWrt.org
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Setting up the clock on the MIPS boards.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/mc146818rtc.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/hardirq.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <asm/mc146818-time.h>
#include <asm/msc01_ic.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mc146818-time.h>
#include <asm/ar7/ar7.h>
void __init ar7_time_init(void)
{
mips_hpt_frequency = ar7_cpu_freq() / 2;
}
void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(7, irq);
}

402
target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c Normal file
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/*
* $Id$
*
* Copyright (C) 2006, 2007 OpenWrt.org
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/ar7/vlynq.h>
#define VLYNQ_PCI_SLOTS 2
struct vlynq_reg_config {
u32 offset;
u32 value;
};
struct vlynq_pci_config {
u32 chip_id;
char name[32];
struct vlynq_mapping rx_mapping[4];
int irq;
int irq_type;
u32 chip;
u32 class;
int num_regs;
struct vlynq_reg_config regs[10];
};
struct vlynq_pci_private {
u32 latency;
u32 cache_line;
u32 command;
u32 sz_mask;
struct vlynq_pci_config *config;
};
static struct vlynq_pci_config known_devices[] = {
{
.chip_id = 0x00000009, .name = "TI ACX111",
.rx_mapping = {
{ .size = 0x22000, .offset = 0xf0000000 },
{ .size = 0x40000, .offset = 0xc0000000 },
{ .size = 0x0, .offset = 0x0 },
{ .size = 0x0, .offset = 0x0 },
},
.irq = 0, .chip = 0x9066104c,
.irq_type = IRQ_TYPE_EDGE_RISING,
.class = PCI_CLASS_NETWORK_OTHER,
.num_regs = 5,
.regs = {
{ .offset = 0x790, .value = (0xd0000000 - (ARCH_PFN_OFFSET << PAGE_SHIFT)) },
{ .offset = 0x794, .value = (0xd0000000 - (ARCH_PFN_OFFSET << PAGE_SHIFT)) },
{ .offset = 0x740, .value = 0 },
{ .offset = 0x744, .value = 0x00010000 },
{ .offset = 0x764, .value = 0x00010000 },
},
},
};
static struct vlynq_device *slots[VLYNQ_PCI_SLOTS] = { NULL, };
static struct resource vlynq_io_resource = {
.start = 0x00000000,
.end = 0x00000000,
.name = "pci IO space",
.flags = IORESOURCE_IO
};
static struct resource vlynq_mem_resource = {
.start = 0x00000000,
.end = 0x00000000,
.name = "pci memory space",
.flags = IORESOURCE_MEM
};
static inline u32 vlynq_get_mapped(struct vlynq_device *dev, int res)
{
int i;
struct vlynq_pci_private *priv = dev->priv;
u32 ret = dev->mem_start;
if (!priv->config->rx_mapping[res].size) return 0;
for (i = 0; i < res; i++)
ret += priv->config->rx_mapping[i].size;
return ret;
}
static inline u32 vlynq_read(u32 val, int size) {
switch (size) {
case 1:
return *(u8 *)&val;
case 2:
return *(u16 *)&val;
}
return val;
}
static int vlynq_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
{
struct vlynq_device *dev;
struct vlynq_pci_private *priv;
int resno, slot = PCI_SLOT(devfn);
if ((size == 2) && (where & 1))
return PCIBIOS_BAD_REGISTER_NUMBER;
else if ((size == 4) && (where & 3))
return PCIBIOS_BAD_REGISTER_NUMBER;
if (slot >= VLYNQ_PCI_SLOTS)
return PCIBIOS_DEVICE_NOT_FOUND;
dev = slots[slot];
if (!dev || (PCI_FUNC(devfn) > 0))
return PCIBIOS_DEVICE_NOT_FOUND;
priv = dev->priv;
switch (where) {
case PCI_VENDOR_ID:
*val = vlynq_read(priv->config->chip, size);
break;
case PCI_DEVICE_ID:
*val = priv->config->chip & 0xffff;
case PCI_COMMAND:
*val = priv->command;
case PCI_STATUS:
/* *val = PCI_STATUS_CAP_LIST;*/
*val = 0;
break;
case PCI_CLASS_REVISION:
*val = priv->config->class;
break;
case PCI_LATENCY_TIMER:
*val = priv->latency;
break;
case PCI_HEADER_TYPE:
*val = PCI_HEADER_TYPE_NORMAL;
break;
case PCI_CACHE_LINE_SIZE:
*val = priv->cache_line;
break;
case PCI_BASE_ADDRESS_0:
case PCI_BASE_ADDRESS_1:
case PCI_BASE_ADDRESS_2:
case PCI_BASE_ADDRESS_3:
resno = (where - PCI_BASE_ADDRESS_0) >> 2;
if (priv->sz_mask & (1 << resno)) {
priv->sz_mask &= ~(1 << resno);
*val = priv->config->rx_mapping[resno].size;
} else {
*val = vlynq_get_mapped(dev, resno);
}
break;
case PCI_BASE_ADDRESS_4:
case PCI_BASE_ADDRESS_5:
case PCI_SUBSYSTEM_VENDOR_ID:
case PCI_SUBSYSTEM_ID:
case PCI_ROM_ADDRESS:
case PCI_INTERRUPT_LINE:
case PCI_CARDBUS_CIS:
case PCI_CAPABILITY_LIST:
*val = 0;
break;
case PCI_INTERRUPT_PIN:
*val = 1;
break;
default:
printk("%s: Read of unknown register 0x%x (size %d)\n",
dev->dev.bus_id, where, size);
return PCIBIOS_BAD_REGISTER_NUMBER;
}
return PCIBIOS_SUCCESSFUL;
}
static int vlynq_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
{
struct vlynq_device *dev;
struct vlynq_pci_private *priv;
int resno, slot = PCI_SLOT(devfn);
if ((size == 2) && (where & 1))
return PCIBIOS_BAD_REGISTER_NUMBER;
else if ((size == 4) && (where & 3))
return PCIBIOS_BAD_REGISTER_NUMBER;
if (slot >= VLYNQ_PCI_SLOTS)
return PCIBIOS_DEVICE_NOT_FOUND;
dev = slots[slot];
if (!dev || (PCI_FUNC(devfn) > 0))
return PCIBIOS_DEVICE_NOT_FOUND;
priv = dev->priv;
switch (where) {
case PCI_VENDOR_ID:
case PCI_DEVICE_ID:
case PCI_STATUS:
case PCI_CLASS_REVISION:
case PCI_HEADER_TYPE:
case PCI_CACHE_LINE_SIZE:
case PCI_SUBSYSTEM_VENDOR_ID:
case PCI_SUBSYSTEM_ID:
case PCI_INTERRUPT_LINE:
case PCI_INTERRUPT_PIN:
case PCI_CARDBUS_CIS:
case PCI_CAPABILITY_LIST:
return PCIBIOS_FUNC_NOT_SUPPORTED;
case PCI_COMMAND:
priv->command = val;
case PCI_LATENCY_TIMER:
priv->latency = val;
break;
case PCI_BASE_ADDRESS_0:
case PCI_BASE_ADDRESS_1:
case PCI_BASE_ADDRESS_2:
case PCI_BASE_ADDRESS_3:
if (val == 0xffffffff) {
resno = (where - PCI_BASE_ADDRESS_0) >> 2;
priv->sz_mask |= (1 << resno);
break;
}
case PCI_BASE_ADDRESS_4:
case PCI_BASE_ADDRESS_5:
case PCI_ROM_ADDRESS:
break;
default:
printk("%s: Write to unknown register 0x%x (size %d) value=0x%x\n",
dev->dev.bus_id, where, size, val);
return PCIBIOS_BAD_REGISTER_NUMBER;
}
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops vlynq_pci_ops = {
vlynq_config_read,
vlynq_config_write
};
static struct pci_controller vlynq_controller = {
.pci_ops = &vlynq_pci_ops,
.io_resource = &vlynq_io_resource,
.mem_resource = &vlynq_mem_resource,
};
static int vlynq_pci_probe(struct vlynq_device *dev)
{
int result, i;
u32 chip_id, addr;
struct vlynq_pci_private *priv;
struct vlynq_mapping mapping[4] = { { 0, }, };
struct vlynq_pci_config *config = NULL;
result = vlynq_set_local_irq(dev, 31);
if (result)
return result;
result = vlynq_set_remote_irq(dev, 30);
if (result)
return result;
result = vlynq_device_enable(dev);
if (result)
return result;
chip_id = vlynq_remote_id(dev);
for (i = 0; i < ARRAY_SIZE(known_devices); i++)
if (chip_id == known_devices[i].chip_id)
config = &known_devices[i];
if (!config) {
printk("vlynq-pci: skipping unknown device "
"%04x:%04x at %s\n", chip_id >> 16,
chip_id & 0xffff, dev->dev.bus_id);
result = -ENODEV;
goto fail;
}
printk("vlynq-pci: attaching device %s at %s\n",
config->name, dev->dev.bus_id);
priv = kmalloc(sizeof(struct vlynq_pci_private), GFP_KERNEL);
if (!priv) {
printk(KERN_ERR "%s: failed to allocate private data\n",
dev->dev.bus_id);
result = -ENOMEM;
goto fail;
}
memset(priv, 0, sizeof(struct vlynq_pci_private));
priv->latency = 64;
priv->cache_line = 32;
priv->config = config;
mapping[0].offset = ARCH_PFN_OFFSET << PAGE_SHIFT;
mapping[0].size = 0x02000000;
vlynq_set_local_mapping(dev, dev->mem_start, mapping);
vlynq_set_remote_mapping(dev, 0, config->rx_mapping);
set_irq_type(vlynq_virq_to_irq(dev, config->irq), config->irq_type);
addr = (u32)ioremap_nocache(dev->mem_start, 0x10000);
if (!addr) {
printk(KERN_ERR "%s: failed to remap io memory\n",
dev->dev.bus_id);
result = -ENXIO;
goto fail;
}
for (i = 0; i < config->num_regs; i++)
*(volatile u32 *)(addr + config->regs[i].offset) =
config->regs[i].value;
dev->priv = priv;
for (i = 0; i < VLYNQ_PCI_SLOTS; i++) {
if (!slots[i]) {
slots[i] = dev;
break;
}
}
return 0;
fail:
vlynq_device_disable(dev);
return result;
}
static int vlynq_pci_remove(struct vlynq_device *dev)
{
int i;
struct vlynq_pci_private *priv = dev->priv;
for (i = 0; i < VLYNQ_PCI_SLOTS; i++)
if (slots[i] == dev)
slots[i] = NULL;
vlynq_device_disable(dev);
kfree(priv);
return 0;
}
static struct vlynq_driver vlynq_pci = {
.name = "PCI over VLYNQ emulation",
.probe = vlynq_pci_probe,
.remove = vlynq_pci_remove,
};
int vlynq_pci_init(void)
{
int res;
res = vlynq_register_driver(&vlynq_pci);
if (res)
return res;
register_pci_controller(&vlynq_controller);
return 0;
}
int pcibios_map_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
struct vlynq_device *dev;
struct vlynq_pci_private *priv;
dev = slots[slot];
if (!dev)
return 0;
priv = dev->priv;
return vlynq_virq_to_irq(dev, priv->config->irq);
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}

553
target/linux/ar7/files/arch/mips/ar7/vlynq.c Normal file
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@@ -0,0 +1,553 @@
/*
* $Id$
*
* Copyright (C) 2006, 2007 OpenWrt.org
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/ar7/ar7.h>
#include <asm/ar7/vlynq.h>
#define PER_DEVICE_IRQS 32
#define VLYNQ_CTRL_PM_ENABLE 0x80000000
#define VLYNQ_CTRL_CLOCK_INT 0x00008000
#define VLYNQ_CTRL_CLOCK_DIV(x) ((x & 7) << 16)
#define VLYNQ_CTRL_INT_LOCAL 0x00004000
#define VLYNQ_CTRL_INT_ENABLE 0x00002000
#define VLYNQ_CTRL_INT_VECTOR(x) ((x & 0x1f) << 8)
#define VLYNQ_CTRL_INT2CFG 0x00000080
#define VLYNQ_CTRL_RESET 0x00000001
#define VLYNQ_STATUS_RERROR 0x00000100
#define VLYNQ_STATUS_LERROR 0x00000080
#define VLYNQ_STATUS_LINK 0x00000001
#define VINT_ENABLE 0x00000100
#define VINT_TYPE_EDGE 0x00000080
#define VINT_LEVEL_LOW 0x00000040
#define VINT_VECTOR(x) (x & 0x1f)
#define VINT_OFFSET(irq) (8 * ((irq) % 4))
#define VLYNQ_AUTONEGO_V2 0x00010000
struct vlynq_regs {
volatile u32 revision;
volatile u32 control;
volatile u32 status;
volatile u32 int_prio;
volatile u32 int_status;
volatile u32 int_pending;
volatile u32 int_ptr;
volatile u32 tx_offset;
volatile struct vlynq_mapping rx_mapping[4];
volatile u32 chip;
volatile u32 autonego;
volatile u32 unused[6];
volatile u32 int_device[8];
} __attribute__ ((packed));
#ifdef VLYNQ_DEBUG
static void vlynq_dump_regs(struct vlynq_device *dev)
{
int i;
printk("VLYNQ local=%p remote=%p\n", dev->local, dev->remote);
for (i = 0; i < 32; i++) {
printk("VLYNQ: local %d: %08x\n", i + 1, ((u32 *)dev->local)[i]);
printk("VLYNQ: remote %d: %08x\n", i + 1, ((u32 *)dev->remote)[i]);
}
}
static void vlynq_dump_mem(u32 *base, int count)
{
int i;
for (i = 0; i < (count + 3) / 4; i++) {
if (i % 4 == 0) printk("\nMEM[0x%04x]:", i * 4);
printk(" 0x%08x", *(base + i));
}
printk("\n");
}
#endif
int vlynq_linked(struct vlynq_device *dev)
{
int i;
for (i = 0; i < 10; i++)
if (dev->local->status & VLYNQ_STATUS_LINK) {
printk("%s: linked\n", dev->dev.bus_id);
return 1;
} else {
mdelay(1);
}
return 0;
}
static void vlynq_irq_unmask(unsigned int irq)
{
volatile u32 val;
struct vlynq_device *dev = irq_desc[irq].chip_data;
int virq;
BUG_ON(!dev);
virq = irq - dev->irq_start;
val = dev->remote->int_device[virq >> 2];
val |= (VINT_ENABLE | virq) << VINT_OFFSET(virq);
dev->remote->int_device[virq >> 2] = val;
}
static void vlynq_irq_mask(unsigned int irq)
{
volatile u32 val;
struct vlynq_device *dev = irq_desc[irq].chip_data;
int virq;
BUG_ON(!dev);
virq = irq - dev->irq_start;
val = dev->remote->int_device[virq >> 2];
val &= ~(VINT_ENABLE << VINT_OFFSET(virq));
dev->remote->int_device[virq >> 2] = val;
}
static int vlynq_irq_type(unsigned int irq, unsigned int flow_type)
{
volatile u32 val;
struct vlynq_device *dev = irq_desc[irq].chip_data;
int virq;
BUG_ON(!dev);
virq = irq - dev->irq_start;
val = dev->remote->int_device[virq >> 2];
switch (flow_type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
val |= VINT_TYPE_EDGE << VINT_OFFSET(virq);
val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq));
break;
case IRQ_TYPE_LEVEL_HIGH:
val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq));
val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq));
break;
case IRQ_TYPE_LEVEL_LOW:
val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq));
val |= VINT_LEVEL_LOW << VINT_OFFSET(virq);
break;
default:
return -EINVAL;
}
dev->remote->int_device[virq >> 2] = val;
return 0;
}
static irqreturn_t vlynq_irq(int irq, void *dev_id)
{
struct vlynq_device *dev = dev_id;
u32 status, ack;
int virq = 0;
status = dev->local->int_status;
dev->local->int_status = status;
if (status & (1 << dev->local_irq)) { /* Local vlynq IRQ. Ack */
ack = dev->local->status;
dev->local->status = ack;
}
if (status & (1 << dev->remote_irq)) { /* Remote vlynq IRQ. Ack */
ack = dev->remote->status;
dev->remote->status = ack;
}
status &= ~((1 << dev->local_irq) | (1 << dev->remote_irq));
while (status) {
if (status & 1) /* Remote device IRQ. Pass. */
do_IRQ(dev->irq_start + virq);
status >>= 1;
virq++;
}
return IRQ_HANDLED;
}
static struct irq_chip vlynq_irq_chip = {
.typename = "VLYNQ",
.name = "vlynq",
.unmask = vlynq_irq_unmask,
.mask = vlynq_irq_mask,
.set_type = vlynq_irq_type,
};
static int vlynq_setup_irq(struct vlynq_device *dev)
{
u32 val;
int i;
if (dev->local_irq == dev->remote_irq) {
printk("%s: local vlynq irq should be different from remote\n",
dev->dev.bus_id);
return -EINVAL;
}
val = VLYNQ_CTRL_INT_VECTOR(dev->local_irq);
val |= VLYNQ_CTRL_INT_ENABLE | VLYNQ_CTRL_INT_LOCAL |
VLYNQ_CTRL_INT2CFG;
dev->local->int_ptr = 0x14;
dev->local->control |= val;
val = VLYNQ_CTRL_INT_VECTOR(dev->remote_irq);
val |= VLYNQ_CTRL_INT_ENABLE;
dev->remote->int_ptr = 0x14;
dev->remote->control |= val;
for (i = 0; i < PER_DEVICE_IRQS; i++) {
if ((i == dev->local_irq) || (i == dev->remote_irq))
continue;
irq_desc[dev->irq_start + i].status = IRQ_DISABLED;
irq_desc[dev->irq_start + i].action = 0;
irq_desc[dev->irq_start + i].depth = 1;
irq_desc[dev->irq_start + i].chip = &vlynq_irq_chip;
irq_desc[dev->irq_start + i].chip_data = dev;
dev->remote->int_device[i >> 2] = 0;
}
if (request_irq(dev->irq, vlynq_irq, SA_SHIRQ, "vlynq", dev)) {
printk("%s: request_irq failed\n", dev->dev.bus_id);
return -EAGAIN;
}
return 0;
}
static void vlynq_free_irq(struct vlynq_device *dev)
{
free_irq(dev->irq, dev);
}
static void vlynq_device_release(struct device *dev)
{
struct vlynq_device *vdev = to_vlynq_device(dev);
kfree(vdev);
}
static int vlynq_device_probe(struct device *dev)
{
struct vlynq_driver *drv = to_vlynq_driver(dev->driver);
if (drv->probe)
return drv->probe(to_vlynq_device(dev));
return 0;
}
static int vlynq_device_remove(struct device *dev)
{
struct vlynq_driver *drv = to_vlynq_driver(dev->driver);
if (drv->remove)
return drv->remove(to_vlynq_device(dev));
return 0;
}
int __vlynq_register_driver(struct vlynq_driver *driver, struct module *owner)
{
driver->driver.name = driver->name;
driver->driver.bus = &vlynq_bus_type;
/* driver->driver.owner = owner;*/
return driver_register(&driver->driver);
}
EXPORT_SYMBOL(__vlynq_register_driver);
void vlynq_unregister_driver(struct vlynq_driver *driver)
{
driver_unregister(&driver->driver);
}
EXPORT_SYMBOL(vlynq_unregister_driver);
int vlynq_device_enable(struct vlynq_device *dev)
{
u32 div;
int result;
struct plat_vlynq_ops *ops = dev->dev.platform_data;
result = ops->on(dev);
if (result)
return result;
dev->local->control = 0;
dev->remote->control = 0;
dev->local->control = VLYNQ_CTRL_CLOCK_INT;
div = ar7_dsp_freq() / 62500000;
if (div != 0 ) {
if (ar7_dsp_freq() / div != 62500000) {
printk(KERN_WARNING
"VLYNQ: Adjusted requested frequency %d to %d\n",
62500000, ar7_dsp_freq() / div);
}
printk("VLYNQ: Setting clock to %d (clock divider %u)\n",
ar7_dsp_freq() / div, div);
dev->local->control |= VLYNQ_CTRL_CLOCK_DIV((div - 1));
}
if (vlynq_linked(dev))
return vlynq_setup_irq(dev);
return -ENODEV;
}
void vlynq_device_disable(struct vlynq_device *dev)
{
struct plat_vlynq_ops *ops = dev->dev.platform_data;
vlynq_free_irq(dev);
ops->off(dev);
}
u32 vlynq_local_id(struct vlynq_device *dev)
{
return dev->local->chip;
}
u32 vlynq_remote_id(struct vlynq_device *dev)
{
return dev->remote->chip;
}
void vlynq_set_local_mapping(struct vlynq_device *dev, u32 tx_offset,
struct vlynq_mapping *mapping)
{
int i;
dev->local->tx_offset = tx_offset;
for (i = 0; i < 4; i++) {
dev->local->rx_mapping[i].offset = mapping[i].offset;
dev->local->rx_mapping[i].size = mapping[i].size;
}
}
void vlynq_set_remote_mapping(struct vlynq_device *dev, u32 tx_offset,
struct vlynq_mapping *mapping)
{
int i;
dev->remote->tx_offset = tx_offset;
for (i = 0; i < 4; i++) {
dev->remote->rx_mapping[i].offset = mapping[i].offset;
dev->remote->rx_mapping[i].size = mapping[i].size;
}
}
int vlynq_virq_to_irq(struct vlynq_device *dev, int virq)
{
if ((virq < 0) || (virq >= PER_DEVICE_IRQS))
return -EINVAL;
if ((virq == dev->local_irq) || (virq == dev->remote_irq))
return -EINVAL;
return dev->irq_start + virq;
}
int vlynq_irq_to_virq(struct vlynq_device *dev, int irq)
{
if ((irq < dev->irq_start) || (irq >= dev->irq_start + PER_DEVICE_IRQS))
return -EINVAL;
return irq - dev->irq_start;
}
int vlynq_set_local_irq(struct vlynq_device *dev, int virq)
{
if ((virq < 0) || (virq >= PER_DEVICE_IRQS))
return -EINVAL;
if (virq == dev->remote_irq)
return -EINVAL;
dev->local_irq = virq;
return 0;
}
int vlynq_set_remote_irq(struct vlynq_device *dev, int virq)
{
if ((virq < 0) || (virq >= PER_DEVICE_IRQS))
return -EINVAL;
if (virq == dev->local_irq)
return -EINVAL;
dev->remote_irq = virq;
return 0;
}
static int vlynq_probe(struct platform_device *pdev)
{
struct vlynq_device *dev;
struct resource *regs_res, *mem_res, *irq_res;
int len, result;
if (strcmp(pdev->name, "vlynq"))
return -ENODEV;
regs_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
if (!regs_res)
return -ENODEV;
mem_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
if (!mem_res)
return -ENODEV;
irq_res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "devirq");
if (!irq_res)
return -ENODEV;
dev = kmalloc(sizeof(struct vlynq_device), GFP_KERNEL);
if (!dev) {
printk(KERN_ERR "vlynq: failed to allocate device structure\n");
return -ENOMEM;
}
memset(dev, 0, sizeof(struct vlynq_device));
dev->id = pdev->id;
dev->dev.bus = &vlynq_bus_type;
dev->dev.parent = &pdev->dev;
snprintf(dev->dev.bus_id, BUS_ID_SIZE, "vlynq%d", dev->id);
dev->dev.bus_id[BUS_ID_SIZE - 1] = 0;
dev->dev.platform_data = pdev->dev.platform_data;
dev->dev.release = vlynq_device_release;
dev->regs_start = regs_res->start;
dev->regs_end = regs_res->end;
dev->mem_start = mem_res->start;
dev->mem_end = mem_res->end;
len = regs_res->end - regs_res->start;
if (!request_mem_region(regs_res->start, len, dev->dev.bus_id)) {
printk("%s: Can't request vlynq registers\n", dev->dev.bus_id);
result = -ENXIO;
goto fail_request;
}
dev->local = ioremap_nocache(regs_res->start, len);
if (!dev->local) {
printk("%s: Can't remap vlynq registers\n", dev->dev.bus_id);
result = -ENXIO;
goto fail_remap;
}
dev->remote = (struct vlynq_regs *)((u32)dev->local + 128);
dev->irq = platform_get_irq_byname(pdev, "irq");
dev->irq_start = irq_res->start;
dev->irq_end = irq_res->end;
dev->local_irq = 31;
dev->remote_irq = 30;
if (device_register(&dev->dev))
goto fail_register;
platform_set_drvdata(pdev, dev);
printk("%s: regs 0x%p, irq %d, mem 0x%p\n",
dev->dev.bus_id, (void *)dev->regs_start, dev->irq,
(void *)dev->mem_start);
return 0;
fail_register:
fail_remap:
iounmap(dev->local);
fail_request:
release_mem_region(regs_res->start, len);
kfree(dev);
return result;
}
static int vlynq_remove(struct platform_device *pdev)
{
struct vlynq_device *dev = platform_get_drvdata(pdev);
device_unregister(&dev->dev);
release_mem_region(dev->regs_start, dev->regs_end - dev->regs_start);
kfree(dev);
return 0;
}
static struct platform_driver vlynq_driver = {
.driver.name = "vlynq",
.probe = vlynq_probe,
.remove = vlynq_remove,
};
struct bus_type vlynq_bus_type = {
.name = "vlynq",
.probe = vlynq_device_probe,
.remove = vlynq_device_remove,
};
EXPORT_SYMBOL(vlynq_bus_type);
#ifdef CONFIG_PCI
extern void vlynq_pci_init(void);
#endif
int __init vlynq_init(void)
{
int res = 0;
res = bus_register(&vlynq_bus_type);
if (res)
goto fail_bus;
res = platform_driver_register(&vlynq_driver);
if (res)
goto fail_platform;
#ifdef CONFIG_PCI
vlynq_pci_init();
#endif
return 0;
fail_platform:
bus_unregister(&vlynq_bus_type);
fail_bus:
return res;
}
/*
void __devexit vlynq_exit(void)
{
platform_driver_unregister(&vlynq_driver);
bus_unregister(&vlynq_bus_type);
}
*/
subsys_initcall(vlynq_init);