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linux/brcm47xx: mainline 2.6.37 602977b0d672687909b0cb0542ede134ed6ef858 commit broke CPU revision: 00024000, MIPS (cc 0x805, rev 0x00, vendor
0x4243) functionality. Revert that patch until we get a proper fix. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24096 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@@ -299,7 +299,7 @@
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* silly idea of putting something else there ...
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*/
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switch (current_cpu_type()) {
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+ case CPU_BMIPS3300:
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+ case CPU_BCM3302:
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+ {
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+ u32 cm;
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+ cm = read_c0_diag();
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@@ -319,7 +319,7 @@
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+ /* Check if special workarounds are required */
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+#ifdef CONFIG_BCM47XX
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+ if (current_cpu_data.cputype == CPU_4KC && (current_cpu_data.processor_id & 0xff) == 0) {
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+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ bcm4710 = 1;
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+ } else
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@@ -345,7 +345,7 @@
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}
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -872,6 +872,9 @@ static void __cpuinit build_r4000_tlb_re
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@@ -873,6 +873,9 @@ static void __cpuinit build_r4000_tlb_re
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/* No need for uasm_i_nop */
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}
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@@ -355,7 +355,7 @@
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#ifdef CONFIG_64BIT
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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#else
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@@ -1322,6 +1325,9 @@ build_r4000_tlbchange_handler_head(u32 *
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@@ -1323,6 +1326,9 @@ build_r4000_tlbchange_handler_head(u32 *
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struct uasm_reloc **r, unsigned int pte,
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unsigned int ptr)
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{
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