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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-28 08:19:21 +02:00
add BCM4710A0 cache workarounds (#143)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@2717 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
parent
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commit
1b0d8a2ab5
@ -0,0 +1,316 @@
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diff -urN linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
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--- linux.old/arch/mips/kernel/genex.S 2005-12-04 06:10:42.000000000 +0100
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+++ linux.dev/arch/mips/kernel/genex.S 2005-12-18 05:30:48.564937750 +0100
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@@ -72,6 +72,10 @@
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.set push
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.set mips3
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.set noat
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+#ifdef CONFIG_BCM4710
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+ nop
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+ nop
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+#endif
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mfc0 k1, CP0_CAUSE
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li k0, 31<<2
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andi k1, k1, 0x7c
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2005-12-04 06:10:42.000000000 +0100
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-12-18 06:08:19.112437750 +0100
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@@ -14,6 +14,12 @@
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#include <linux/mm.h>
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#include <linux/bitops.h>
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+#ifdef CONFIG_BCM4710
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+#include "../bcm947xx/include/typedefs.h"
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+#include "../bcm947xx/include/sbconfig.h"
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+#include <asm/paccess.h>
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+#endif
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+
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/cache.h>
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@@ -29,6 +35,9 @@
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#include <asm/war.h>
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#include <asm/cacheflush.h> /* for run_uncached() */
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+/* For enabling BCM4710 cache workarounds */
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+int bcm4710 = 0;
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+
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/*
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* Must die.
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*/
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@@ -73,7 +82,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache_page = blast_dcache_page;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache_page = blast_dcache16_page;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
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@@ -85,7 +96,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
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@@ -97,7 +110,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache = blast_dcache;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache = blast_dcache16;
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else if (dc_lsize == 32)
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r4k_blast_dcache = blast_dcache32;
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@@ -486,6 +501,9 @@
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addr = start & ~(dc_lsize - 1);
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aend = (end - 1) & ~(dc_lsize - 1);
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(aend);
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+
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while (1) {
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/* Hit_Writeback_Inv_D */
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protected_writeback_dcache_line(addr);
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@@ -657,6 +675,10 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -702,6 +724,10 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -727,6 +753,8 @@
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unsigned long addr = (unsigned long) arg;
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R4600_HIT_CACHEOP_WAR_IMPL;
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store)
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protected_writeback_scache_line(addr & ~(sc_lsize - 1));
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@@ -1202,6 +1230,16 @@
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static inline void coherency_setup(void)
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{
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
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+ if (BCM330X(current_cpu_data.processor_id)) {
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+ __u32 cm = read_c0_diag();
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+ /* Enable icache */
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+ cm |= (1 << 31);
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+ /* Enable dcache */
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+ cm |= (1 << 30);
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+ write_c0_diag(cm);
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+ }
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+#endif
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/*
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* c0_status.cu=0 specifies that updates by the sc instruction use
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@@ -1231,6 +1269,15 @@
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/* Default cache error handler for R4000 and R5000 family */
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set_uncached_handler (0x100, &except_vec2_generic, 0x80);
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+
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+ /* Check if special workarounds are required */
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+#ifdef CONFIG_BCM4710
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+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ bcm4710 = 1;
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+ } else
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+#endif
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+ bcm4710 = 0;
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probe_pcache();
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setup_scache();
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diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
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--- linux.old/arch/mips/mm/tlbex.c 2005-12-15 12:57:27.945158000 +0100
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+++ linux.dev/arch/mips/mm/tlbex.c 2005-12-18 06:06:17.916863500 +0100
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@@ -28,6 +28,10 @@
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/* #define DEBUG_TLB */
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+#ifdef CONFIG_BCM4710
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+extern int bcm4710;
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+#endif
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+
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static __init int __attribute__((unused)) r45k_bvahwbug(void)
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{
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/* XXX: We should probe for the presence of this bug, but we don't. */
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@@ -1152,6 +1156,12 @@
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memset(relocs, 0, sizeof(relocs));
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memset(final_handler, 0, sizeof(final_handler));
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+#ifdef CONFIG_BCM4710
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+ if (bcm4710) {
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+ i_nop(&p);
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+ }
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+#endif
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+
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/*
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* create the plain linear handler
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*/
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diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
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--- linux.old/include/asm-mips/r4kcache.h 2005-12-17 22:39:19.281320000 +0100
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+++ linux.dev/include/asm-mips/r4kcache.h 2005-12-18 05:22:06.020280750 +0100
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@@ -15,6 +15,18 @@
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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+#ifdef CONFIG_BCM4710
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+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
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+
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+#else
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+#define BCM4710_DUMMY_RREG()
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+
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+#define BCM4710_FILL_TLB(addr)
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+#define BCM4710_PROTECTED_FILL_TLB(addr)
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+#endif
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+
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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@@ -45,6 +57,7 @@
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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cache_op(Index_Writeback_Inv_D, addr);
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}
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@@ -60,11 +73,13 @@
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static inline void flush_dcache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Invalidate_D, addr);
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}
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@@ -104,6 +119,7 @@
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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@@ -166,6 +182,49 @@
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: "r" (base), \
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"i" (op));
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+static inline void blast_dcache(void)
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+{
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+ unsigned long start = KSEG0;
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+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
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+ unsigned long end = (start + dcache_size);
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+
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+ do {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Index_Writeback_Inv_D, start);
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+ start += current_cpu_data.dcache.linesz;
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+ } while(start < end);
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+}
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+
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+static inline void blast_dcache_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+
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+ BCM4710_FILL_TLB(start);
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+ do {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Hit_Writeback_Inv_D, start);
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+ start += current_cpu_data.dcache.linesz;
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+ } while(start < end);
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+}
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+
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+static inline void blast_dcache_page_indexed(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+ for (ws = 0; ws < ws_end; ws += ws_inc) {
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+ start = page + ws;
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+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Index_Writeback_Inv_D, addr);
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+ }
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+ }
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+}
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+
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static inline void blast_dcache16(void)
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{
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unsigned long start = INDEX_BASE;
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@@ -213,7 +272,8 @@
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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-
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+
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+ BCM4710_FILL_TLB(start);
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Invalidate_I);
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@@ -357,6 +417,7 @@
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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+ BCM4710_FILL_TLB(start);
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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@@ -471,6 +532,7 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+ BCM4710_FILL_TLB(start);
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do {
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cache64_unroll32(start,Hit_Invalidate_I);
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start += 0x800;
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diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
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--- linux.old/include/asm-mips/stackframe.h 2005-12-04 06:10:42.000000000 +0100
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+++ linux.dev/include/asm-mips/stackframe.h 2005-12-18 05:33:02.405302250 +0100
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@@ -285,6 +285,10 @@
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.macro RESTORE_SP_AND_RET
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LONG_L sp, PT_R29(sp)
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.set mips3
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+#ifdef CONFIG_BCM4710
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+ nop
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+ nop
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+#endif
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eret
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.set mips0
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.endm
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