mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 10:30:38 +02:00
[ppc40x] backport support of the OpenRB Lite board to 2.6.28
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16912 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
parent
6f552b2cec
commit
1b11ae512b
@ -117,6 +117,7 @@ CONFIG_NOT_COHERENT_CACHE=y
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CONFIG_OF=y
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CONFIG_OF=y
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CONFIG_OF_DEVICE=y
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CONFIG_OF_DEVICE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_GPIO=y
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CONFIG_OPENRB_LIGHT=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PAGE_OFFSET=0xc0000000
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CONFIG_PAGE_OFFSET=0xc0000000
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CONFIG_PCI=y
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CONFIG_PCI=y
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340
target/linux/ppc40x/patches/007-openrb-light.patch
Normal file
340
target/linux/ppc40x/patches/007-openrb-light.patch
Normal file
@ -0,0 +1,340 @@
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--- a/arch/powerpc/boot/Makefile
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+++ b/arch/powerpc/boot/Makefile
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@@ -70,7 +70,8 @@ src-plat := of.c cuboot-52xx.c cuboot-82
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cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
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cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
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virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
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- cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c
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+ cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c \
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+ cuboot-openrb-light.c
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src-boot := $(src-wlib) $(src-plat) empty.c
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src-boot := $(addprefix $(obj)/, $(src-boot))
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@@ -216,6 +217,7 @@ image-$(CONFIG_WALNUT) += treeImage.wa
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image-$(CONFIG_ACADIA) += cuImage.acadia
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image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
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image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2
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+image-$(CONFIG_OPENRB_LIGHT) += cuImage.openrb-light
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# Board ports in arch/powerpc/platform/44x/Kconfig
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image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
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--- a/arch/powerpc/platforms/40x/Kconfig
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+++ b/arch/powerpc/platforms/40x/Kconfig
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@@ -79,6 +79,16 @@ config MAKALU
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help
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This option enables support for the AMCC PPC405EX board.
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+config OPENRB_LIGHT
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+ bool "OpenRB Light"
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+ depends on 40x
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+ default n
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+ select PPC40x_SIMPLE
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+ select 405EP
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+ select PCI
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+ help
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+ This option enables support for the OpenRB Light board.
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+
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#config REDWOOD_5
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# bool "Redwood-5"
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# depends on 40x
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--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
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+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
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@@ -54,6 +54,7 @@ static char *board[] __initdata = {
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"amcc,acadia",
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"magicboxv1",
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"magicboxv2",
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+ "openrb,light",
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};
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static int __init ppc40x_probe(void)
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--- /dev/null
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+++ b/arch/powerpc/boot/cuboot-openrb-light.c
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@@ -0,0 +1,41 @@
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+/*
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+ * Old U-boot compatibility for OpenRB Light board
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+ *
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+ * Author: Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include "ops.h"
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+#include "io.h"
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+#include "dcr.h"
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+#include "stdio.h"
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+#include "4xx.h"
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+#include "44x.h"
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+#include "cuboot.h"
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+
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+#define TARGET_4xx
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+#define TARGET_405EP
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+#include "ppcboot.h"
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+
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+static bd_t bd;
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+
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+static void openrb_light_fixups(void)
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+{
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+ ibm405ep_fixup_clocks(33333000);
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+ ibm4xx_sdram_fixup_memsize();
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+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
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+}
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+
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+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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+ unsigned long r6, unsigned long r7)
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+{
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+ CUBOOT_INIT();
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+ platform_ops.fixups = openrb_light_fixups;
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+ platform_ops.exit = ibm40x_dbcr_reset;
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+ fdt_init(_dtb_start);
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+ serial_console_init();
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+}
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+
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--- /dev/null
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+++ b/arch/powerpc/boot/dts/openrb-light.dts
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@@ -0,0 +1,244 @@
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+/*
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+ * Device Tree Source for OpenRB Light board
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+ *
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+ * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * Based on magicboxv2.dts
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without
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+ * any warranty of any kind, whether express or implied.
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+ */
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+
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+/dts-v1/;
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ model = "openrb,light";
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+ compatible = "openrb,light";
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+ dcr-parent = <&{/cpus/cpu@0}>;
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+
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+ aliases {
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+ ethernet0 = &EMAC0;
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+ serial0 = &UART0;
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+ serial1 = &UART1;
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ model = "PowerPC,405EP";
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+ reg = <0x00000000>;
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+ clock-frequency = <0xbebc200>; /* Filled in by zImage */
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+ timebase-frequency = <0>; /* Filled in by zImage */
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+ i-cache-line-size = <20>;
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+ d-cache-line-size = <20>;
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+ i-cache-size = <4000>;
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+ d-cache-size = <4000>;
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+ dcr-controller;
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+ dcr-access-method = "native";
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+ };
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x00000000 0x00000000>; /* Filled in by zImage */
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+ };
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+
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+ UIC0: interrupt-controller {
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+ compatible = "ibm,uic";
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+ interrupt-controller;
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+ cell-index = <0>;
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+ dcr-reg = <0x0c0 0x009>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ plb {
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+ compatible = "ibm,plb3";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ clock-frequency = <0>; /* Filled in by zImage */
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+
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+ SDRAM0: memory-controller {
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+ compatible = "ibm,sdram-405ep";
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+ dcr-reg = <0x010 0x002>;
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+ };
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+
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+ MAL: mcmal {
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+ compatible = "ibm,mcmal-405ep", "ibm,mcmal";
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+ dcr-reg = <0x180 0x062>;
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+ num-tx-chans = <4>;
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+ num-rx-chans = <2>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <
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+ 0xb 0x4 /* TXEOB */
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+ 0xc 0x4 /* RXEOB */
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+ 0xa 0x4 /* SERR */
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+ 0xd 0x4 /* TXDE */
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+ 0xe 0x4 /* RXDE */>;
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+ };
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+
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+ OPB0: opb {
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+ compatible = "ibm,opb-405ep", "ibm,opb";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0xef600000 0xef600000 0x00a00000>;
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+ dcr-reg = <0x0a0 0x005>;
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+ clock-frequency = <0>; /* Filled in by zImage */
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+
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+ UART0: serial@ef600300 {
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+ device_type = "serial";
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+ compatible = "ns16550";
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+ reg = <0xef600300 0x00000008>;
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+ virtual-reg = <0xef600300>;
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+ clock-frequency = <0>; /* Filled in by zImage */
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+ current-speed = <115200>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x0 0x4>;
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+ };
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+
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+ UART1: serial@ef600400 {
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+ device_type = "serial";
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+ compatible = "ns16550";
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+ reg = <0xef600400 0x00000008>;
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+ virtual-reg = <0xef600400>;
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+ clock-frequency = <0>; /* Filled in by zImage */
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+ current-speed = <115200>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x1 0x4>;
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+ };
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+
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+ IIC: i2c@ef600500 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "ibm,iic-405ep", "ibm,iic";
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+ reg = <0xef600500 0x00000011>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x2 0x4>;
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+
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+ eeprom@50 {
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+ compatible = "at24,24c16";
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+ reg = <0x50>;
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+ };
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+ };
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+
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+ GPIO0: gpio-controller@ef600700 {
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+ compatible = "ibm,ppc4xx-gpio";
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+ reg = <0xef600700 0x00000020>;
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+ #gpio-cells = <2>;
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+ gpio-controller;
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+ };
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+
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+ EMAC0: ethernet@ef600800 {
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+ linux,network-index = <0x0>;
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+ device_type = "network";
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+ compatible = "ibm,emac-405ep", "ibm,emac";
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <
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+ 0xf 0x4 /* Ethernet */
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+ 0x9 0x4 /* Ethernet Wake Up */>;
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+ local-mac-address = [000000000000]; /* Filled in by zImage */
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+ reg = <0xef600800 0x00000070>;
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+ mal-device = <&MAL>;
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+ mal-tx-channel = <0>;
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+ mal-rx-channel = <0>;
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+ cell-index = <0>;
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+ max-frame-size = <0x5dc>;
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+ rx-fifo-size = <0x1000>;
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+ tx-fifo-size = <0x800>;
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+ phy-mode = "mii";
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+ phy-map = <0x00000000>;
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ user {
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+ label = "openrb:green:user";
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+ gpios = <&GPIO0 2 1>;
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+ };
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+ };
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+ };
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+
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+ EBC0: ebc {
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+ compatible = "ibm,ebc-405ep", "ibm,ebc";
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+ dcr-reg = <0x012 0x002>;
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ /* The ranges property is supplied by the bootwrapper
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+ * and is based on the firmware's configuration of the
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+ * EBC bridge
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+ */
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+ clock-frequency = <0>; /* Filled in by zImage */
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+
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+ nor_flash@ff800000 {
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+ compatible = "cfi-flash";
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+ bank-width = <2>;
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+ reg = <0x00000000 0xff800000 0x00800000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ partition@0 {
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+ label = "linux";
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+ reg = <0x0 0x120000>;
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+ };
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+ partition@120000 {
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+ label = "rootfs";
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+ reg = <0x120000 0x6a0000>;
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+ };
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+ partition@7c0000 {
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+ label = "u-boot";
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+ reg = <0x7c0000 0x30000>;
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+ read-only;
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+ };
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+ };
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+ };
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+
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+ PCI0: pci@ec000000 {
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+ device_type = "pci";
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ #address-cells = <3>;
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+ compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
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+ primary;
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+ reg = <0xeec00000 0x00000008 /* Config space access */
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+ 0xeed80000 0x00000004 /* IACK */
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+ 0xeed80000 0x00000004 /* Special cycle */
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+ 0xef480000 0x00000040>; /* Internal registers */
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+
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+ /* Outbound ranges, one memory and one IO,
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+ * later cannot be changed. Chip supports a second
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+ * IO range but we don't use it for now
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+ */
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+ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
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+ 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
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+
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+ /* Inbound 2GB range starting at 0 */
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+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
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+
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+ interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
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+ interrupt-map = <
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+ /* IDSEL 1 */
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+ 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
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+
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+ /* IDSEL 2 */
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+ 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
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+
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+ /* IDSEL 3 */
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+ 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
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+
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+ /* IDSEL 4 */
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+ 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
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+ >;
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+ };
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+ };
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+
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+ chosen {
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+ linux,stdout-path = "/plb/opb/serial@ef600300";
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+ };
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+};
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