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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 15:35:30 +02:00
brcm47xx: fix build of tg3 for kernel 2.6.34
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20994 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
e5c8c6677a
commit
1ff112ddd2
@ -8,7 +8,7 @@
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#include <net/checksum.h>
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#include <net/checksum.h>
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#include <net/ip.h>
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#include <net/ip.h>
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@@ -471,8 +472,9 @@
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@@ -471,8 +472,9 @@ static void _tw32_flush(struct tg3 *tp,
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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{
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{
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tp->write32_mbox(tp, off, val);
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tp->write32_mbox(tp, off, val);
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@ -20,7 +20,7 @@
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tp->read32_mbox(tp, off);
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tp->read32_mbox(tp, off);
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}
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}
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@@ -482,7 +484,7 @@
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@@ -482,7 +484,7 @@ static void tg3_write32_tx_mbox(struct t
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writel(val, mbox);
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writel(val, mbox);
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if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
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if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
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writel(val, mbox);
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writel(val, mbox);
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@ -29,7 +29,7 @@
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readl(mbox);
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readl(mbox);
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}
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}
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@@ -783,7 +785,7 @@
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@@ -783,7 +785,7 @@ static void tg3_switch_clocks(struct tg3
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#define PHY_BUSY_LOOPS 5000
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#define PHY_BUSY_LOOPS 5000
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@ -38,7 +38,7 @@
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{
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{
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u32 frame_val;
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u32 frame_val;
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unsigned int loops;
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unsigned int loops;
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@@ -797,7 +799,7 @@
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@@ -797,7 +799,7 @@ static int tg3_readphy(struct tg3 *tp, i
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*val = 0x0;
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*val = 0x0;
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@ -47,7 +47,7 @@
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MI_COM_PHY_ADDR_MASK);
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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MI_COM_REG_ADDR_MASK);
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@@ -832,7 +834,12 @@
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@@ -832,7 +834,12 @@ static int tg3_readphy(struct tg3 *tp, i
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return ret;
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return ret;
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}
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}
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@ -61,7 +61,7 @@
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{
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{
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u32 frame_val;
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u32 frame_val;
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unsigned int loops;
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unsigned int loops;
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@@ -848,7 +855,7 @@
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@@ -848,7 +855,7 @@ static int tg3_writephy(struct tg3 *tp,
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udelay(80);
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udelay(80);
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}
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}
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@ -70,7 +70,7 @@
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MI_COM_PHY_ADDR_MASK);
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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MI_COM_REG_ADDR_MASK);
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@@ -881,6 +888,11 @@
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@@ -881,6 +888,11 @@ static int tg3_writephy(struct tg3 *tp,
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return ret;
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return ret;
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}
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}
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@ -82,7 +82,7 @@
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static int tg3_bmcr_reset(struct tg3 *tp)
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static int tg3_bmcr_reset(struct tg3 *tp)
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{
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{
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u32 phy_control;
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u32 phy_control;
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@@ -2389,6 +2401,9 @@
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@@ -2389,6 +2401,9 @@ static int tg3_nvram_read(struct tg3 *tp
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{
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{
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int ret;
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int ret;
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@ -92,20 +92,20 @@
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if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
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if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
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return tg3_nvram_read_using_eeprom(tp, offset, val);
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return tg3_nvram_read_using_eeprom(tp, offset, val);
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@@ -2720,8 +2735,10 @@
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@@ -2720,8 +2735,10 @@ static int tg3_set_power_state(struct tg
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tg3_frob_aux_power(tp);
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tg3_frob_aux_power(tp);
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/* Workaround for unstable PLL clock */
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/* Workaround for unstable PLL clock */
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- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
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- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
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+ if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
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+ if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
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+ /* !!! FIXME !!! */
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+ /* !!! FIXME !!! */
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+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
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+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
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u32 val = tr32(0x7d00);
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u32 val = tr32(0x7d00);
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val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
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val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
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@@ -3214,6 +3231,14 @@
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@@ -3214,6 +3231,14 @@ relink:
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tg3_phy_copper_begin(tp);
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tg3_phy_copper_begin(tp);
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@ -120,7 +120,7 @@
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tg3_readphy(tp, MII_BMSR, &tmp);
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tg3_readphy(tp, MII_BMSR, &tmp);
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if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
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if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
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(tmp & BMSR_LSTATUS))
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(tmp & BMSR_LSTATUS))
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@@ -6675,6 +6700,11 @@
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@@ -6675,6 +6700,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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int i;
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int i;
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u32 val;
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u32 val;
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@ -132,7 +132,7 @@
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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for (i = 0; i < 200; i++) {
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@@ -6958,6 +6988,14 @@
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@@ -6958,6 +6988,14 @@ static int tg3_chip_reset(struct tg3 *tp
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tw32(0x5000, 0x400);
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tw32(0x5000, 0x400);
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}
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}
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@ -147,7 +147,7 @@
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tw32(GRC_MODE, tp->grc_mode);
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tw32(GRC_MODE, tp->grc_mode);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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@@ -7135,9 +7173,12 @@
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@@ -7135,9 +7173,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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return -ENODEV;
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return -ENODEV;
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}
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}
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@ -163,7 +163,7 @@
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return 0;
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return 0;
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}
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}
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@@ -7199,6 +7240,11 @@
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@@ -7199,6 +7240,11 @@ static int tg3_load_5701_a0_firmware_fix
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const __be32 *fw_data;
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const __be32 *fw_data;
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int err, i;
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int err, i;
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@ -175,7 +175,7 @@
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fw_data = (void *)tp->fw->data;
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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/* Firmware blob starts with version numbers, followed by
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@@ -7256,6 +7302,11 @@
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@@ -7256,6 +7302,11 @@ static int tg3_load_tso_firmware(struct
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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int err, i;
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int err, i;
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@ -187,7 +187,7 @@
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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return 0;
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return 0;
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@@ -8380,6 +8431,11 @@
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@@ -8380,6 +8431,11 @@ static void tg3_timer(unsigned long __op
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spin_lock(&tp->lock);
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spin_lock(&tp->lock);
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@ -199,7 +199,7 @@
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if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
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if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
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/* All of this garbage is because when using non-tagged
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/* All of this garbage is because when using non-tagged
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* IRQ status the mailbox/status_block protocol the chip
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* IRQ status the mailbox/status_block protocol the chip
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@@ -10278,6 +10334,11 @@
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@@ -10278,6 +10334,11 @@ static int tg3_test_nvram(struct tg3 *tp
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if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
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if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
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return 0;
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return 0;
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@ -211,7 +211,7 @@
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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return -EIO;
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return -EIO;
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@@ -11097,7 +11158,7 @@
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@@ -11097,7 +11158,7 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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spin_lock_bh(&tp->lock);
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@ -220,7 +220,7 @@
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spin_unlock_bh(&tp->lock);
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spin_unlock_bh(&tp->lock);
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data->val_out = mii_regval;
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data->val_out = mii_regval;
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@@ -11113,7 +11174,7 @@
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@@ -11113,7 +11174,7 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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spin_lock_bh(&tp->lock);
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@ -229,7 +229,7 @@
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spin_unlock_bh(&tp->lock);
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spin_unlock_bh(&tp->lock);
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return err;
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return err;
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@@ -11758,6 +11819,12 @@
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@@ -11758,6 +11819,12 @@ static void __devinit tg3_get_5717_nvram
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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{
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@ -242,7 +242,7 @@
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tw32_f(GRC_EEPROM_ADDR,
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@@ -12019,6 +12086,9 @@
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@@ -12019,6 +12086,9 @@ static int tg3_nvram_write_block(struct
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{
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{
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int ret;
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int ret;
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@ -252,7 +252,7 @@
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@@ -13359,6 +13429,11 @@
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@@ -13359,6 +13429,11 @@ static int __devinit tg3_get_invariants(
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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@ -264,7 +264,7 @@
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/* Get eeprom hw config before calling tg3_set_power_state().
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLG2_IS_NIC flag must be
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* In particular, the TG3_FLG2_IS_NIC flag must be
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* determined before calling tg3_set_power_state() so that
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* determined before calling tg3_set_power_state() so that
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@@ -13752,6 +13827,10 @@
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@@ -13752,6 +13827,10 @@ static int __devinit tg3_get_device_addr
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}
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}
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if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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@ -275,7 +275,7 @@
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#ifdef CONFIG_SPARC
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#ifdef CONFIG_SPARC
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if (!tg3_get_default_macaddr_sparc(tp))
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if (!tg3_get_default_macaddr_sparc(tp))
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return 0;
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return 0;
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@@ -14271,6 +14350,7 @@
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@@ -14271,6 +14350,7 @@ static char * __devinit tg3_phy_string(s
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case TG3_PHY_ID_BCM5704: return "5704";
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case TG3_PHY_ID_BCM5704: return "5704";
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case TG3_PHY_ID_BCM5705: return "5705";
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case TG3_PHY_ID_BCM5705: return "5705";
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case TG3_PHY_ID_BCM5750: return "5750";
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case TG3_PHY_ID_BCM5750: return "5750";
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@ -283,7 +283,7 @@
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case TG3_PHY_ID_BCM5752: return "5752";
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case TG3_PHY_ID_BCM5752: return "5752";
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case TG3_PHY_ID_BCM5714: return "5714";
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case TG3_PHY_ID_BCM5714: return "5714";
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case TG3_PHY_ID_BCM5780: return "5780";
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case TG3_PHY_ID_BCM5780: return "5780";
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@@ -14480,6 +14560,13 @@
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@@ -14480,6 +14560,13 @@ static int __devinit tg3_init_one(struct
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tp->msg_enable = tg3_debug;
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tp->msg_enable = tg3_debug;
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else
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else
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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@ -309,7 +309,7 @@
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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@@ -2930,6 +2933,7 @@
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@@ -2930,6 +2933,7 @@ struct tg3 {
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#define TG3_PHY_ID_BCM5704 0x60008190
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#define TG3_PHY_ID_BCM5704 0x60008190
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#define TG3_PHY_ID_BCM5705 0x600081a0
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#define TG3_PHY_ID_BCM5705 0x600081a0
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#define TG3_PHY_ID_BCM5750 0x60008180
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#define TG3_PHY_ID_BCM5750 0x60008180
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@ -317,12 +317,12 @@
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#define TG3_PHY_ID_BCM5752 0x60008100
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#define TG3_PHY_ID_BCM5752 0x60008100
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#define TG3_PHY_ID_BCM5714 0x60008340
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#define TG3_PHY_ID_BCM5714 0x60008340
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#define TG3_PHY_ID_BCM5780 0x60008350
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#define TG3_PHY_ID_BCM5780 0x60008350
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@@ -2964,7 +2968,8 @@
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@@ -2964,7 +2968,8 @@ struct tg3 {
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(X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
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(X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
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(X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
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(X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
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(X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
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(X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
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- (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002)
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- (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002)
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+ (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002) || \
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+ (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002 || \
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+ (X) == TG3_PHY_ID_BCM5750_2)
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+ (X) == TG3_PHY_ID_BCM5750_2)
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u32 led_ctrl;
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u32 led_ctrl;
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