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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 03:18:26 +02:00
ar71xx: set MII interface speed from the set_speed callbacks
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29013 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -206,6 +206,36 @@ static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
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iounmap(base);
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iounmap(base);
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}
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}
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static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
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{
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void __iomem *base;
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unsigned int mii_speed;
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u32 t;
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switch (speed) {
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case SPEED_10:
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mii_speed = MII_CTRL_SPEED_10;
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break;
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case SPEED_100:
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mii_speed = MII_CTRL_SPEED_100;
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break;
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case SPEED_1000:
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mii_speed = MII_CTRL_SPEED_1000;
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break;
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default:
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BUG();
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}
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base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
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t = __raw_readl(base + reg);
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t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
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t |= mii_speed << MII_CTRL_SPEED_SHIFT;
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__raw_writel(t, base + reg);
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iounmap(base);
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}
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void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
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void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
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{
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{
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struct platform_device *mdio_dev;
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struct platform_device *mdio_dev;
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@ -321,6 +351,7 @@ static void ar71xx_set_speed_ge0(int speed)
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR71XX_ETH0_PLL_SHIFT);
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val, AR71XX_ETH0_PLL_SHIFT);
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ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
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}
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}
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static void ar71xx_set_speed_ge1(int speed)
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static void ar71xx_set_speed_ge1(int speed)
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@ -329,6 +360,7 @@ static void ar71xx_set_speed_ge1(int speed)
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR71XX_ETH1_PLL_SHIFT);
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val, AR71XX_ETH1_PLL_SHIFT);
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ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
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}
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}
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static void ar724x_set_speed_ge0(int speed)
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static void ar724x_set_speed_ge0(int speed)
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@ -357,6 +389,7 @@ static void ar91xx_set_speed_ge0(int speed)
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR91XX_ETH0_PLL_SHIFT);
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val, AR91XX_ETH0_PLL_SHIFT);
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ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
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}
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}
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static void ar91xx_set_speed_ge1(int speed)
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static void ar91xx_set_speed_ge1(int speed)
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@ -365,6 +398,7 @@ static void ar91xx_set_speed_ge1(int speed)
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR91XX_ETH1_PLL_SHIFT);
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val, AR91XX_ETH1_PLL_SHIFT);
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ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
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}
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}
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static void ar933x_set_speed_ge0(int speed)
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static void ar933x_set_speed_ge0(int speed)
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@ -817,6 +817,11 @@ void ar71xx_flash_release(void);
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#define MII_REG_MII1_CTRL 0x04
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#define MII_REG_MII1_CTRL 0x04
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#define MII_CTRL_IF_MASK 3
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#define MII_CTRL_IF_MASK 3
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#define MII_CTRL_SPEED_SHIFT 4
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#define MII_CTRL_SPEED_MASK 3
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#define MII_CTRL_SPEED_10 0
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#define MII_CTRL_SPEED_100 1
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#define MII_CTRL_SPEED_1000 2
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#define MII0_CTRL_IF_GMII 0
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#define MII0_CTRL_IF_GMII 0
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#define MII0_CTRL_IF_MII 1
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#define MII0_CTRL_IF_MII 1
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@ -533,7 +533,6 @@ void ag71xx_link_adjust(struct ag71xx *ag)
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u32 cfg2;
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u32 cfg2;
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u32 ifctl;
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u32 ifctl;
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u32 fifo5;
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u32 fifo5;
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u32 mii_speed;
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if (!ag->link) {
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if (!ag->link) {
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ag71xx_hw_stop(ag);
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ag71xx_hw_stop(ag);
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@ -558,17 +557,14 @@ void ag71xx_link_adjust(struct ag71xx *ag)
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switch (ag->speed) {
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switch (ag->speed) {
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case SPEED_1000:
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case SPEED_1000:
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mii_speed = MII_CTRL_SPEED_1000;
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cfg2 |= MAC_CFG2_IF_1000;
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cfg2 |= MAC_CFG2_IF_1000;
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fifo5 |= FIFO_CFG5_BM;
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fifo5 |= FIFO_CFG5_BM;
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break;
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break;
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case SPEED_100:
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case SPEED_100:
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mii_speed = MII_CTRL_SPEED_100;
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cfg2 |= MAC_CFG2_IF_10_100;
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cfg2 |= MAC_CFG2_IF_10_100;
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ifctl |= MAC_IFCTL_SPEED;
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ifctl |= MAC_IFCTL_SPEED;
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break;
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break;
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case SPEED_10:
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case SPEED_10:
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mii_speed = MII_CTRL_SPEED_10;
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cfg2 |= MAC_CFG2_IF_10_100;
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cfg2 |= MAC_CFG2_IF_10_100;
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break;
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break;
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default:
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default:
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@ -586,8 +582,6 @@ void ag71xx_link_adjust(struct ag71xx *ag)
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if (pdata->set_speed)
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if (pdata->set_speed)
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pdata->set_speed(ag->speed);
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pdata->set_speed(ag->speed);
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ag71xx_mii_ctrl_set_speed(ag, mii_speed);
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
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ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
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ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
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