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ar71xx: move arch specific files to files-2.6.39
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29867 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
@@ -1,933 +0,0 @@
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/*
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* Atheros AR71xx SoC specific definitions
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros 2.6.15 BSP
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* Parts of this file are based on Atheros 2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_AR71XX_H
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#define __ASM_MACH_AR71XX_H
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#ifndef __ASSEMBLER__
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#define AR71XX_PCI_MEM_BASE 0x10000000
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#define AR71XX_PCI_MEM_SIZE 0x08000000
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#define AR71XX_APB_BASE 0x18000000
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#define AR71XX_GE0_BASE 0x19000000
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#define AR71XX_GE0_SIZE 0x01000000
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#define AR71XX_GE1_BASE 0x1a000000
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#define AR71XX_GE1_SIZE 0x01000000
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#define AR71XX_EHCI_BASE 0x1b000000
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#define AR71XX_EHCI_SIZE 0x01000000
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#define AR71XX_OHCI_BASE 0x1c000000
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#define AR71XX_OHCI_SIZE 0x01000000
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#define AR7240_OHCI_BASE 0x1b000000
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#define AR7240_OHCI_SIZE 0x01000000
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#define AR71XX_SPI_BASE 0x1f000000
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#define AR71XX_SPI_SIZE 0x01000000
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#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
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#define AR71XX_DDR_CTRL_SIZE 0x10000
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#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
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#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR71XX_UART_SIZE 0x10000
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#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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#define AR71XX_USB_CTRL_SIZE 0x10000
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#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
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#define AR71XX_GPIO_SIZE 0x10000
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#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
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#define AR71XX_PLL_SIZE 0x10000
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#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
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#define AR71XX_RESET_SIZE 0x10000
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#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
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#define AR71XX_MII_SIZE 0x10000
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#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
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#define AR71XX_SLIC_SIZE 0x10000
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#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
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#define AR71XX_DMA_SIZE 0x10000
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#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
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#define AR71XX_STEREO_SIZE 0x10000
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#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR724X_PCI_CRP_SIZE 0x100
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#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
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#define AR724X_PCI_CTRL_SIZE 0x100
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#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR91XX_WMAC_SIZE 0x30000
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#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR933X_UART_SIZE 0x14
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#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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#define AR933X_GMAC_SIZE 0x04
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#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR933X_WMAC_SIZE 0x20000
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#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR934X_WMAC_SIZE 0x20000
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#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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#define AR934X_GMAC_SIZE 0x14
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#define AR71XX_MEM_SIZE_MIN 0x0200000
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#define AR71XX_MEM_SIZE_MAX 0x10000000
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#define AR71XX_CPU_IRQ_BASE 0
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#define AR71XX_MISC_IRQ_BASE 8
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#define AR71XX_MISC_IRQ_COUNT 32
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#define AR71XX_GPIO_IRQ_BASE 40
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#define AR71XX_GPIO_IRQ_COUNT 32
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#define AR71XX_PCI_IRQ_BASE 72
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#define AR71XX_PCI_IRQ_COUNT 6
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#define AR934X_IP2_IRQ_BASE 78
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#define AR934X_IP2_IRQ_COUNT 2
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#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
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#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
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#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
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#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
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#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
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#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
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#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
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#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
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#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
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#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
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#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
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#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
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#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
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#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
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#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8)
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#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9)
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#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10)
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#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11)
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#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12)
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#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
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#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
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#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
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#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
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#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
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#define AR934X_IP2_IRQ_WMAC (AR934X_IP2_IRQ_BASE + 0)
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#define AR934X_IP2_IRQ_PCIE (AR934X_IP2_IRQ_BASE + 1)
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extern u32 ar71xx_ahb_freq;
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extern u32 ar71xx_cpu_freq;
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extern u32 ar71xx_ddr_freq;
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extern u32 ar71xx_ref_freq;
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enum ar71xx_soc_type {
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AR71XX_SOC_UNKNOWN,
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AR71XX_SOC_AR7130,
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AR71XX_SOC_AR7141,
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AR71XX_SOC_AR7161,
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AR71XX_SOC_AR7240,
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AR71XX_SOC_AR7241,
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AR71XX_SOC_AR7242,
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AR71XX_SOC_AR9130,
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AR71XX_SOC_AR9132,
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AR71XX_SOC_AR9330,
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AR71XX_SOC_AR9331,
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AR71XX_SOC_AR9341,
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AR71XX_SOC_AR9342,
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AR71XX_SOC_AR9344,
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};
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extern u32 ar71xx_soc_rev;
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extern enum ar71xx_soc_type ar71xx_soc;
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/*
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* PLL block
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*/
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#define AR71XX_PLL_REG_CPU_CONFIG 0x00
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#define AR71XX_PLL_REG_SEC_CONFIG 0x04
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#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
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#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
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#define AR71XX_PLL_DIV_SHIFT 3
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#define AR71XX_PLL_DIV_MASK 0x1f
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#define AR71XX_CPU_DIV_SHIFT 16
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#define AR71XX_CPU_DIV_MASK 0x3
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#define AR71XX_DDR_DIV_SHIFT 18
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#define AR71XX_DDR_DIV_MASK 0x3
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#define AR71XX_AHB_DIV_SHIFT 20
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#define AR71XX_AHB_DIV_MASK 0x7
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#define AR71XX_ETH0_PLL_SHIFT 17
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#define AR71XX_ETH1_PLL_SHIFT 19
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#define AR724X_PLL_REG_CPU_CONFIG 0x00
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#define AR724X_PLL_REG_PCIE_CONFIG 0x18
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#define AR724X_PLL_DIV_SHIFT 0
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#define AR724X_PLL_DIV_MASK 0x3ff
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#define AR724X_PLL_REF_DIV_SHIFT 10
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#define AR724X_PLL_REF_DIV_MASK 0xf
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#define AR724X_AHB_DIV_SHIFT 19
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#define AR724X_AHB_DIV_MASK 0x1
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#define AR724X_DDR_DIV_SHIFT 22
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#define AR724X_DDR_DIV_MASK 0x3
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#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
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#define AR91XX_PLL_REG_CPU_CONFIG 0x00
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#define AR91XX_PLL_REG_ETH_CONFIG 0x04
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#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
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#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
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#define AR91XX_PLL_DIV_SHIFT 0
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#define AR91XX_PLL_DIV_MASK 0x3ff
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#define AR91XX_DDR_DIV_SHIFT 22
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#define AR91XX_DDR_DIV_MASK 0x3
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#define AR91XX_AHB_DIV_SHIFT 19
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#define AR91XX_AHB_DIV_MASK 0x1
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#define AR91XX_ETH0_PLL_SHIFT 20
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#define AR91XX_ETH1_PLL_SHIFT 22
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#define AR933X_PLL_CPU_CONFIG_REG 0x00
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#define AR933X_PLL_CLOCK_CTRL_REG 0x08
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#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
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#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
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#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
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#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
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#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
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#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
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#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
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#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
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#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
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#define AR934X_PLL_REG_CPU_CONFIG 0x00
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#define AR934X_PLL_REG_DDR_CONFIG 0x04
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#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
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#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
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#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19
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#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000
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#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \
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(((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \
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AR934X_CPU_PLL_CFG_OUTDIV_LSB)
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#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25
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#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23
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#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000
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#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \
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(((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \
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AR934X_DDR_PLL_CFG_OUTDIV_LSB)
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#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \
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(((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \
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AR934X_DDR_PLL_CFG_OUTDIV_MASK)
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#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16
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#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12
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#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000
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#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \
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(((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \
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AR934X_CPU_PLL_CFG_REFDIV_LSB)
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#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \
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(((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \
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AR934X_CPU_PLL_CFG_REFDIV_MASK)
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#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2
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#define AR934X_CPU_PLL_CFG_NINT_MSB 11
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#define AR934X_CPU_PLL_CFG_NINT_LSB 6
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#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0
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#define AR934X_CPU_PLL_CFG_NINT_GET(x) \
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(((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \
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AR934X_CPU_PLL_CFG_NINT_LSB)
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#define AR934X_CPU_PLL_CFG_NINT_SET(x) \
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(((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \
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AR934X_CPU_PLL_CFG_NINT_MASK)
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#define AR934X_CPU_PLL_CFG_NINT_RESET 20
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#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5
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#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0
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#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f
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#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \
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(((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \
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AR934X_CPU_PLL_CFG_NFRAC_LSB)
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#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \
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(((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \
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AR934X_CPU_PLL_CFG_NFRAC_MASK)
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#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20
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#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16
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#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000
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#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \
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(((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \
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AR934X_DDR_PLL_CFG_REFDIV_LSB)
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#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \
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(((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \
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AR934X_DDR_PLL_CFG_REFDIV_MASK)
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#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2
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#define AR934X_DDR_PLL_CFG_NINT_MSB 15
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#define AR934X_DDR_PLL_CFG_NINT_LSB 10
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#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00
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#define AR934X_DDR_PLL_CFG_NINT_GET(x) \
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(((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \
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AR934X_DDR_PLL_CFG_NINT_LSB)
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#define AR934X_DDR_PLL_CFG_NINT_SET(x) \
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(((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \
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AR934X_DDR_PLL_CFG_NINT_MASK)
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#define AR934X_DDR_PLL_CFG_NINT_RESET 20
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#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9
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#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0
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#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff
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#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \
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(((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \
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AR934X_DDR_PLL_CFG_NFRAC_LSB)
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#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \
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(((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \
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AR934X_DDR_PLL_CFG_NFRAC_MASK)
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#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \
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(((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \
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AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB)
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \
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(((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \
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AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \
|
||||
(((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \
|
||||
AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB)
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \
|
||||
(((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \
|
||||
AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \
|
||||
(((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \
|
||||
AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB)
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \
|
||||
(((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \
|
||||
AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \
|
||||
(((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \
|
||||
AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB)
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \
|
||||
(((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \
|
||||
AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
|
||||
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
||||
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
||||
|
||||
extern void __iomem *ar71xx_pll_base;
|
||||
|
||||
static inline void ar71xx_pll_wr(unsigned reg, u32 val)
|
||||
{
|
||||
__raw_writel(val, ar71xx_pll_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 ar71xx_pll_rr(unsigned reg)
|
||||
{
|
||||
return __raw_readl(ar71xx_pll_base + reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* USB_CONFIG block
|
||||
*/
|
||||
#define USB_CTRL_REG_FLADJ 0x00
|
||||
#define USB_CTRL_REG_CONFIG 0x04
|
||||
|
||||
extern void __iomem *ar71xx_usb_ctrl_base;
|
||||
|
||||
static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
|
||||
{
|
||||
__raw_writel(val, ar71xx_usb_ctrl_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
|
||||
{
|
||||
return __raw_readl(ar71xx_usb_ctrl_base + reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* GPIO block
|
||||
*/
|
||||
#define AR71XX_GPIO_REG_OE 0x00
|
||||
#define AR71XX_GPIO_REG_IN 0x04
|
||||
#define AR71XX_GPIO_REG_OUT 0x08
|
||||
#define AR71XX_GPIO_REG_SET 0x0c
|
||||
#define AR71XX_GPIO_REG_CLEAR 0x10
|
||||
#define AR71XX_GPIO_REG_INT_MODE 0x14
|
||||
#define AR71XX_GPIO_REG_INT_TYPE 0x18
|
||||
#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
|
||||
#define AR71XX_GPIO_REG_INT_PENDING 0x20
|
||||
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
|
||||
#define AR71XX_GPIO_REG_FUNC 0x28
|
||||
|
||||
#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
|
||||
#define AR934X_GPIO_REG_OUT_FUNC1 0x30
|
||||
#define AR934X_GPIO_REG_OUT_FUNC2 0x34
|
||||
#define AR934X_GPIO_REG_OUT_FUNC3 0x38
|
||||
#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
|
||||
#define AR934X_GPIO_REG_OUT_FUNC5 0x40
|
||||
#define AR934X_GPIO_REG_FUNC 0x6c
|
||||
|
||||
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
|
||||
#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
|
||||
#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
|
||||
#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
|
||||
#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
|
||||
#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
|
||||
#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
|
||||
|
||||
#define AR71XX_GPIO_COUNT 16
|
||||
|
||||
#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
|
||||
#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
|
||||
#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
|
||||
#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
|
||||
#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
|
||||
#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
|
||||
#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
|
||||
#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
|
||||
#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
|
||||
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
|
||||
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
|
||||
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
|
||||
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
|
||||
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
|
||||
#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
|
||||
#define AR724X_GPIO_FUNC_UART_EN BIT(1)
|
||||
#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
|
||||
|
||||
#define AR7240_GPIO_COUNT 18
|
||||
#define AR7241_GPIO_COUNT 20
|
||||
|
||||
#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
|
||||
#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
|
||||
#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
|
||||
#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
|
||||
#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
|
||||
#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
|
||||
#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
|
||||
#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
|
||||
#define AR91XX_GPIO_FUNC_UART_EN BIT(8)
|
||||
#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
|
||||
|
||||
#define AR91XX_GPIO_COUNT 22
|
||||
|
||||
#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
|
||||
#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
|
||||
#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
|
||||
#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
|
||||
#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
|
||||
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
|
||||
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
|
||||
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
|
||||
#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
|
||||
#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
|
||||
#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
|
||||
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
|
||||
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
|
||||
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
|
||||
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
|
||||
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
|
||||
#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
|
||||
#define AR933X_GPIO_FUNC_UART_EN BIT(1)
|
||||
#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
|
||||
|
||||
#define AR933X_GPIO_COUNT 30
|
||||
|
||||
#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
|
||||
#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
|
||||
|
||||
#define AR934X_GPIO_COUNT 23
|
||||
#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
|
||||
|
||||
#define AR934X_GPIO_OUT_GPIO 0x00
|
||||
|
||||
extern void __iomem *ar71xx_gpio_base;
|
||||
|
||||
static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
|
||||
{
|
||||
__raw_writel(value, ar71xx_gpio_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 ar71xx_gpio_rr(unsigned reg)
|
||||
{
|
||||
return __raw_readl(ar71xx_gpio_base + reg);
|
||||
}
|
||||
|
||||
void ar71xx_gpio_init(void) __init;
|
||||
void ar71xx_gpio_function_enable(u32 mask);
|
||||
void ar71xx_gpio_function_disable(u32 mask);
|
||||
void ar71xx_gpio_function_setup(u32 set, u32 clear);
|
||||
void ar71xx_gpio_output_select(unsigned gpio, u8 val);
|
||||
|
||||
/*
|
||||
* DDR_CTRL block
|
||||
*/
|
||||
#define AR71XX_DDR_REG_PCI_WIN0 0x7c
|
||||
#define AR71XX_DDR_REG_PCI_WIN1 0x80
|
||||
#define AR71XX_DDR_REG_PCI_WIN2 0x84
|
||||
#define AR71XX_DDR_REG_PCI_WIN3 0x88
|
||||
#define AR71XX_DDR_REG_PCI_WIN4 0x8c
|
||||
#define AR71XX_DDR_REG_PCI_WIN5 0x90
|
||||
#define AR71XX_DDR_REG_PCI_WIN6 0x94
|
||||
#define AR71XX_DDR_REG_PCI_WIN7 0x98
|
||||
#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
|
||||
#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
|
||||
#define AR71XX_DDR_REG_FLUSH_USB 0xa4
|
||||
#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
|
||||
|
||||
#define AR724X_DDR_REG_FLUSH_GE0 0x7c
|
||||
#define AR724X_DDR_REG_FLUSH_GE1 0x80
|
||||
#define AR724X_DDR_REG_FLUSH_USB 0x84
|
||||
#define AR724X_DDR_REG_FLUSH_PCIE 0x88
|
||||
|
||||
#define AR91XX_DDR_REG_FLUSH_GE0 0x7c
|
||||
#define AR91XX_DDR_REG_FLUSH_GE1 0x80
|
||||
#define AR91XX_DDR_REG_FLUSH_USB 0x84
|
||||
#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
|
||||
|
||||
#define AR933X_DDR_REG_FLUSH_GE0 0x7c
|
||||
#define AR933X_DDR_REG_FLUSH_GE1 0x80
|
||||
#define AR933X_DDR_REG_FLUSH_USB 0x84
|
||||
#define AR933X_DDR_REG_FLUSH_WMAC 0x88
|
||||
|
||||
#define AR934X_DDR_REG_FLUSH_GE0 0x9c
|
||||
#define AR934X_DDR_REG_FLUSH_GE1 0xa0
|
||||
#define AR934X_DDR_REG_FLUSH_USB 0xa4
|
||||
#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
|
||||
#define AR934X_DDR_REG_FLUSH_WMAC 0xac
|
||||
|
||||
|
||||
#define PCI_WIN0_OFFS 0x10000000
|
||||
#define PCI_WIN1_OFFS 0x11000000
|
||||
#define PCI_WIN2_OFFS 0x12000000
|
||||
#define PCI_WIN3_OFFS 0x13000000
|
||||
#define PCI_WIN4_OFFS 0x14000000
|
||||
#define PCI_WIN5_OFFS 0x15000000
|
||||
#define PCI_WIN6_OFFS 0x16000000
|
||||
#define PCI_WIN7_OFFS 0x07000000
|
||||
|
||||
extern void __iomem *ar71xx_ddr_base;
|
||||
|
||||
static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
|
||||
{
|
||||
__raw_writel(val, ar71xx_ddr_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 ar71xx_ddr_rr(unsigned reg)
|
||||
{
|
||||
return __raw_readl(ar71xx_ddr_base + reg);
|
||||
}
|
||||
|
||||
void ar71xx_ddr_flush(u32 reg);
|
||||
|
||||
/*
|
||||
* PCI block
|
||||
*/
|
||||
#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
|
||||
#define AR71XX_PCI_CFG_SIZE 0x100
|
||||
|
||||
#define PCI_REG_CRP_AD_CBE 0x00
|
||||
#define PCI_REG_CRP_WRDATA 0x04
|
||||
#define PCI_REG_CRP_RDDATA 0x08
|
||||
#define PCI_REG_CFG_AD 0x0c
|
||||
#define PCI_REG_CFG_CBE 0x10
|
||||
#define PCI_REG_CFG_WRDATA 0x14
|
||||
#define PCI_REG_CFG_RDDATA 0x18
|
||||
#define PCI_REG_PCI_ERR 0x1c
|
||||
#define PCI_REG_PCI_ERR_ADDR 0x20
|
||||
#define PCI_REG_AHB_ERR 0x24
|
||||
#define PCI_REG_AHB_ERR_ADDR 0x28
|
||||
|
||||
#define PCI_CRP_CMD_WRITE 0x00010000
|
||||
#define PCI_CRP_CMD_READ 0x00000000
|
||||
#define PCI_CFG_CMD_READ 0x0000000a
|
||||
#define PCI_CFG_CMD_WRITE 0x0000000b
|
||||
|
||||
#define PCI_IDSEL_ADL_START 17
|
||||
|
||||
#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
|
||||
#define AR724X_PCI_CFG_SIZE 0x1000
|
||||
|
||||
#define AR724X_PCI_REG_APP 0x00
|
||||
#define AR724X_PCI_REG_RESET 0x18
|
||||
#define AR724X_PCI_REG_INT_STATUS 0x4c
|
||||
#define AR724X_PCI_REG_INT_MASK 0x50
|
||||
|
||||
#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
|
||||
#define AR724X_PCI_RESET_LINK_UP BIT(0)
|
||||
|
||||
#define AR724X_PCI_INT_DEV0 BIT(14)
|
||||
|
||||
/*
|
||||
* RESET block
|
||||
*/
|
||||
#define AR71XX_RESET_REG_TIMER 0x00
|
||||
#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
|
||||
#define AR71XX_RESET_REG_WDOG_CTRL 0x08
|
||||
#define AR71XX_RESET_REG_WDOG 0x0c
|
||||
#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
|
||||
#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
|
||||
#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
|
||||
#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
|
||||
#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
|
||||
#define AR71XX_RESET_REG_RESET_MODULE 0x24
|
||||
#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
|
||||
#define AR71XX_RESET_REG_PERFC0 0x30
|
||||
#define AR71XX_RESET_REG_PERFC1 0x34
|
||||
#define AR71XX_RESET_REG_REV_ID 0x90
|
||||
|
||||
#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
|
||||
#define AR91XX_RESET_REG_RESET_MODULE 0x1c
|
||||
#define AR91XX_RESET_REG_PERF_CTRL 0x20
|
||||
#define AR91XX_RESET_REG_PERFC0 0x24
|
||||
#define AR91XX_RESET_REG_PERFC1 0x28
|
||||
|
||||
#define AR724X_RESET_REG_RESET_MODULE 0x1c
|
||||
|
||||
#define AR933X_RESET_REG_RESET_MODULE 0x1c
|
||||
#define AR933X_RESET_REG_BOOTSTRAP 0xac
|
||||
#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
|
||||
#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
|
||||
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
|
||||
|
||||
#define AR934X_RESET_REG_RESET_MODULE 0x1c
|
||||
|
||||
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
|
||||
#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
|
||||
#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
|
||||
#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
|
||||
#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
|
||||
#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
|
||||
(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
|
||||
AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
|
||||
|
||||
#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
|
||||
(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
|
||||
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
|
||||
AR934X_PCIE_WMAC_INT_PCIE_RC3)
|
||||
|
||||
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
||||
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
|
||||
#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
|
||||
#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
|
||||
#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
|
||||
#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
|
||||
#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
|
||||
#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
|
||||
#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
|
||||
#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
|
||||
#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
|
||||
#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
|
||||
#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
||||
#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
|
||||
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
||||
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
||||
|
||||
#define WDOG_CTRL_LAST_RESET BIT(31)
|
||||
#define WDOG_CTRL_ACTION_MASK 3
|
||||
#define WDOG_CTRL_ACTION_NONE 0 /* no action */
|
||||
#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
|
||||
#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
|
||||
#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
|
||||
|
||||
#define MISC_INT_ENET_LINK BIT(12)
|
||||
#define MISC_INT_DDR_PERF BIT(11)
|
||||
#define MISC_INT_TIMER4 BIT(10)
|
||||
#define MISC_INT_TIMER3 BIT(9)
|
||||
#define MISC_INT_TIMER2 BIT(8)
|
||||
#define MISC_INT_DMA BIT(7)
|
||||
#define MISC_INT_OHCI BIT(6)
|
||||
#define MISC_INT_PERFC BIT(5)
|
||||
#define MISC_INT_WDOG BIT(4)
|
||||
#define MISC_INT_UART BIT(3)
|
||||
#define MISC_INT_GPIO BIT(2)
|
||||
#define MISC_INT_ERROR BIT(1)
|
||||
#define MISC_INT_TIMER BIT(0)
|
||||
|
||||
#define PCI_INT_CORE BIT(4)
|
||||
#define PCI_INT_DEV2 BIT(2)
|
||||
#define PCI_INT_DEV1 BIT(1)
|
||||
#define PCI_INT_DEV0 BIT(0)
|
||||
|
||||
#define RESET_MODULE_EXTERNAL BIT(28)
|
||||
#define RESET_MODULE_FULL_CHIP BIT(24)
|
||||
#define RESET_MODULE_AMBA2WMAC BIT(22)
|
||||
#define RESET_MODULE_CPU_NMI BIT(21)
|
||||
#define RESET_MODULE_CPU_COLD BIT(20)
|
||||
#define RESET_MODULE_DMA BIT(19)
|
||||
#define RESET_MODULE_SLIC BIT(18)
|
||||
#define RESET_MODULE_STEREO BIT(17)
|
||||
#define RESET_MODULE_DDR BIT(16)
|
||||
#define RESET_MODULE_GE1_MAC BIT(13)
|
||||
#define RESET_MODULE_GE1_PHY BIT(12)
|
||||
#define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
|
||||
#define RESET_MODULE_GE0_MAC BIT(9)
|
||||
#define RESET_MODULE_GE0_PHY BIT(8)
|
||||
#define RESET_MODULE_USB_OHCI_DLL BIT(6)
|
||||
#define RESET_MODULE_USB_HOST BIT(5)
|
||||
#define RESET_MODULE_USB_PHY BIT(4)
|
||||
#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
|
||||
#define RESET_MODULE_PCI_BUS BIT(1)
|
||||
#define RESET_MODULE_PCI_CORE BIT(0)
|
||||
|
||||
#define AR724X_RESET_GE1_MDIO BIT(23)
|
||||
#define AR724X_RESET_GE0_MDIO BIT(22)
|
||||
#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
|
||||
#define AR724X_RESET_PCIE_PHY BIT(7)
|
||||
#define AR724X_RESET_PCIE BIT(6)
|
||||
#define AR724X_RESET_USB_HOST BIT(5)
|
||||
#define AR724X_RESET_USB_PHY BIT(4)
|
||||
#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
|
||||
|
||||
#define AR933X_RESET_WMAC BIT(11)
|
||||
#define AR933X_RESET_GE1_MDIO BIT(23)
|
||||
#define AR933X_RESET_GE0_MDIO BIT(22)
|
||||
#define AR933X_RESET_GE1_MAC BIT(13)
|
||||
#define AR933X_RESET_GE0_MAC BIT(9)
|
||||
#define AR933X_RESET_USB_HOST BIT(5)
|
||||
#define AR933X_RESET_USB_PHY BIT(4)
|
||||
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
|
||||
|
||||
#define AR934X_RESET_HOST BIT(31)
|
||||
#define AR934X_RESET_SLIC BIT(30)
|
||||
#define AR934X_RESET_HDMA BIT(29)
|
||||
#define AR934X_RESET_EXTERNAL BIT(28)
|
||||
#define AR934X_RESET_RTC BIT(27)
|
||||
#define AR934X_RESET_PCIE_EP_INT BIT(26)
|
||||
#define AR934X_RESET_CHKSUM_ACC BIT(25)
|
||||
#define AR934X_RESET_FULL_CHIP BIT(24)
|
||||
#define AR934X_RESET_GE1_MDIO BIT(23)
|
||||
#define AR934X_RESET_GE0_MDIO BIT(22)
|
||||
#define AR934X_RESET_CPU_NMI BIT(21)
|
||||
#define AR934X_RESET_CPU_COLD BIT(20)
|
||||
#define AR934X_RESET_HOST_RESET_INT BIT(19)
|
||||
#define AR934X_RESET_PCIE_EP BIT(18)
|
||||
#define AR934X_RESET_UART1 BIT(17)
|
||||
#define AR934X_RESET_DDR BIT(16)
|
||||
#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
|
||||
#define AR934X_RESET_NANDF BIT(14)
|
||||
#define AR934X_RESET_GE1_MAC BIT(13)
|
||||
#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
|
||||
#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
|
||||
#define AR934X_RESET_HOST_DMA_INT BIT(10)
|
||||
#define AR934X_RESET_GE0_MAC BIT(9)
|
||||
#define AR934X_RESET_ETH_SIWTCH BIT(8)
|
||||
#define AR934X_RESET_PCIE_PHY BIT(7)
|
||||
#define AR934X_RESET_PCIE BIT(6)
|
||||
#define AR934X_RESET_USB_HOST BIT(5)
|
||||
#define AR934X_RESET_USB_PHY BIT(4)
|
||||
#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
|
||||
#define AR934X_RESET_LUT BIT(2)
|
||||
#define AR934X_RESET_MBOX BIT(1)
|
||||
#define AR934X_RESET_I2S BIT(0)
|
||||
|
||||
#define REV_ID_MAJOR_MASK 0xfff0
|
||||
#define REV_ID_MAJOR_AR71XX 0x00a0
|
||||
#define REV_ID_MAJOR_AR913X 0x00b0
|
||||
#define REV_ID_MAJOR_AR7240 0x00c0
|
||||
#define REV_ID_MAJOR_AR7241 0x0100
|
||||
#define REV_ID_MAJOR_AR7242 0x1100
|
||||
#define REV_ID_MAJOR_AR9330 0x0110
|
||||
#define REV_ID_MAJOR_AR9331 0x1110
|
||||
#define REV_ID_MAJOR_AR9341 0x0120
|
||||
#define REV_ID_MAJOR_AR9342 0x1120
|
||||
#define REV_ID_MAJOR_AR9344 0x2120
|
||||
|
||||
#define AR71XX_REV_ID_MINOR_MASK 0x3
|
||||
#define AR71XX_REV_ID_MINOR_AR7130 0x0
|
||||
#define AR71XX_REV_ID_MINOR_AR7141 0x1
|
||||
#define AR71XX_REV_ID_MINOR_AR7161 0x2
|
||||
#define AR71XX_REV_ID_REVISION_MASK 0x3
|
||||
#define AR71XX_REV_ID_REVISION_SHIFT 2
|
||||
|
||||
#define AR91XX_REV_ID_MINOR_MASK 0x3
|
||||
#define AR91XX_REV_ID_MINOR_AR9130 0x0
|
||||
#define AR91XX_REV_ID_MINOR_AR9132 0x1
|
||||
#define AR91XX_REV_ID_REVISION_MASK 0x3
|
||||
#define AR91XX_REV_ID_REVISION_SHIFT 2
|
||||
|
||||
#define AR724X_REV_ID_REVISION_MASK 0x3
|
||||
|
||||
#define AR933X_REV_ID_REVISION_MASK 0xf
|
||||
|
||||
#define AR934X_REV_ID_REVISION_MASK 0xf
|
||||
|
||||
extern void __iomem *ar71xx_reset_base;
|
||||
|
||||
static inline void ar71xx_reset_wr(unsigned reg, u32 val)
|
||||
{
|
||||
__raw_writel(val, ar71xx_reset_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 ar71xx_reset_rr(unsigned reg)
|
||||
{
|
||||
return __raw_readl(ar71xx_reset_base + reg);
|
||||
}
|
||||
|
||||
void ar71xx_device_stop(u32 mask);
|
||||
void ar71xx_device_start(u32 mask);
|
||||
void ar71xx_device_reset_rmw(u32 clear, u32 set);
|
||||
int ar71xx_device_stopped(u32 mask);
|
||||
|
||||
/*
|
||||
* SPI block
|
||||
*/
|
||||
#define SPI_REG_FS 0x00 /* Function Select */
|
||||
#define SPI_REG_CTRL 0x04 /* SPI Control */
|
||||
#define SPI_REG_IOC 0x08 /* SPI I/O Control */
|
||||
#define SPI_REG_RDS 0x0c /* Read Data Shift */
|
||||
|
||||
#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
|
||||
|
||||
#define SPI_CTRL_RD BIT(6) /* Remap Disable */
|
||||
#define SPI_CTRL_DIV_MASK 0x3f
|
||||
|
||||
#define SPI_IOC_DO BIT(0) /* Data Out pin */
|
||||
#define SPI_IOC_CLK BIT(8) /* CLK pin */
|
||||
#define SPI_IOC_CS(n) BIT(16 + (n))
|
||||
#define SPI_IOC_CS0 SPI_IOC_CS(0)
|
||||
#define SPI_IOC_CS1 SPI_IOC_CS(1)
|
||||
#define SPI_IOC_CS2 SPI_IOC_CS(2)
|
||||
#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
|
||||
|
||||
void ar71xx_flash_acquire(void);
|
||||
void ar71xx_flash_release(void);
|
||||
|
||||
/*
|
||||
* MII_CTRL block
|
||||
*/
|
||||
#define MII_REG_MII0_CTRL 0x00
|
||||
#define MII_REG_MII1_CTRL 0x04
|
||||
|
||||
#define MII_CTRL_IF_MASK 3
|
||||
#define MII_CTRL_SPEED_SHIFT 4
|
||||
#define MII_CTRL_SPEED_MASK 3
|
||||
#define MII_CTRL_SPEED_10 0
|
||||
#define MII_CTRL_SPEED_100 1
|
||||
#define MII_CTRL_SPEED_1000 2
|
||||
|
||||
#define MII0_CTRL_IF_GMII 0
|
||||
#define MII0_CTRL_IF_MII 1
|
||||
#define MII0_CTRL_IF_RGMII 2
|
||||
#define MII0_CTRL_IF_RMII 3
|
||||
|
||||
#define MII1_CTRL_IF_RGMII 0
|
||||
#define MII1_CTRL_IF_RMII 1
|
||||
|
||||
/*
|
||||
* AR933X GMAC
|
||||
*/
|
||||
#define AR933X_GMAC_REG_ETH_CFG 0x00
|
||||
|
||||
#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
|
||||
#define AR933X_ETH_CFG_MII_GE0 BIT(1)
|
||||
#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
|
||||
#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
|
||||
#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
|
||||
#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
|
||||
#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
||||
#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
|
||||
#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
|
||||
#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
|
||||
#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
|
||||
|
||||
/*
|
||||
* AR934X GMAC Interface
|
||||
*/
|
||||
#define AR934X_GMAC_REG_ETH_CFG 0x00
|
||||
|
||||
#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
|
||||
#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
|
||||
#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
|
||||
#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
|
||||
#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
|
||||
#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
|
||||
#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
|
||||
#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
||||
#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
|
||||
#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
|
||||
#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
|
||||
#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
|
||||
#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_H */
|
||||
@@ -1,26 +0,0 @@
|
||||
/*
|
||||
* AR91xx parallel flash driver platform data definitions
|
||||
*
|
||||
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __AR91XX_FLASH_H
|
||||
#define __AR91XX_FLASH_H
|
||||
|
||||
struct mtd_partition;
|
||||
|
||||
struct ar91xx_flash_platform_data {
|
||||
unsigned int width;
|
||||
u8 is_shared:1;
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
unsigned int nr_parts;
|
||||
struct mtd_partition *parts;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* __AR91XX_FLASH_H */
|
||||
@@ -1,67 +0,0 @@
|
||||
/*
|
||||
* Atheros AR933X UART defines
|
||||
*
|
||||
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __AR933X_UART_H
|
||||
#define __AR933X_UART_H
|
||||
|
||||
#define AR933X_UART_REGS_SIZE 20
|
||||
#define AR933X_UART_FIFO_SIZE 16
|
||||
|
||||
#define AR933X_UART_DATA_REG 0x00
|
||||
#define AR933X_UART_CS_REG 0x04
|
||||
#define AR933X_UART_CLOCK_REG 0x08
|
||||
#define AR933X_UART_INT_REG 0x0c
|
||||
#define AR933X_UART_INT_EN_REG 0x10
|
||||
|
||||
#define AR933X_UART_DATA_TX_RX_MASK 0xff
|
||||
#define AR933X_UART_DATA_RX_CSR BIT(8)
|
||||
#define AR933X_UART_DATA_TX_CSR BIT(9)
|
||||
|
||||
#define AR933X_UART_CS_PARITY_S 0
|
||||
#define AR933X_UART_CS_PARITY_M 0x3
|
||||
#define AR933X_UART_CS_PARITY_NONE 0
|
||||
#define AR933X_UART_CS_PARITY_ODD 1
|
||||
#define AR933X_UART_CS_PARITY_EVEN 2
|
||||
#define AR933X_UART_CS_IF_MODE_S 2
|
||||
#define AR933X_UART_CS_IF_MODE_M 0x3
|
||||
#define AR933X_UART_CS_IF_MODE_NONE 0
|
||||
#define AR933X_UART_CS_IF_MODE_DTE 1
|
||||
#define AR933X_UART_CS_IF_MODE_DCE 2
|
||||
#define AR933X_UART_CS_FLOW_CTRL_S 4
|
||||
#define AR933X_UART_CS_FLOW_CTRL_M 0x3
|
||||
#define AR933X_UART_CS_DMA_EN BIT(6)
|
||||
#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
|
||||
#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
|
||||
#define AR933X_UART_CS_TX_READY BIT(9)
|
||||
#define AR933X_UART_CS_RX_BREAK BIT(10)
|
||||
#define AR933X_UART_CS_TX_BREAK BIT(11)
|
||||
#define AR933X_UART_CS_HOST_INT BIT(12)
|
||||
#define AR933X_UART_CS_HOST_INT_EN BIT(13)
|
||||
#define AR933X_UART_CS_TX_BUSY BIT(14)
|
||||
#define AR933X_UART_CS_RX_BUSY BIT(15)
|
||||
|
||||
#define AR933X_UART_CLOCK_STEP_M 0xffff
|
||||
#define AR933X_UART_CLOCK_SCALE_M 0xfff
|
||||
#define AR933X_UART_CLOCK_SCALE_S 16
|
||||
#define AR933X_UART_CLOCK_STEP_M 0xffff
|
||||
|
||||
#define AR933X_UART_INT_RX_VALID BIT(0)
|
||||
#define AR933X_UART_INT_TX_READY BIT(1)
|
||||
#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
|
||||
#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
|
||||
#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
|
||||
#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
|
||||
#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
|
||||
#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
|
||||
#define AR933X_UART_INT_RX_FULL BIT(8)
|
||||
#define AR933X_UART_INT_TX_EMPTY BIT(9)
|
||||
#define AR933X_UART_INT_ALLINTS 0x3ff
|
||||
|
||||
#endif /* __AR933X_UART_H */
|
||||
@@ -1,18 +0,0 @@
|
||||
/*
|
||||
* Platform data definition for Atheros AR933X UART
|
||||
*
|
||||
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _AR933X_UART_PLATFORM_H
|
||||
#define _AR933X_UART_PLATFORM_H
|
||||
|
||||
struct ar933x_uart_platform_data {
|
||||
unsigned uartclk;
|
||||
};
|
||||
|
||||
#endif /* _AR933X_UART_PLATFORM_H */
|
||||
@@ -1,56 +0,0 @@
|
||||
/*
|
||||
* Atheros AR71xx specific CPU feature overrides
|
||||
*
|
||||
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This file was derived from: include/asm-mips/cpu-features.h
|
||||
* Copyright (C) 2003, 2004 Ralf Baechle
|
||||
* Copyright (C) 2004 Maciej W. Rozycki
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
#define cpu_has_tlb 1
|
||||
#define cpu_has_4kex 1
|
||||
#define cpu_has_3k_cache 0
|
||||
#define cpu_has_4k_cache 1
|
||||
#define cpu_has_tx39_cache 0
|
||||
#define cpu_has_sb1_cache 0
|
||||
#define cpu_has_fpu 0
|
||||
#define cpu_has_32fpr 0
|
||||
#define cpu_has_counter 1
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_has_divec 1
|
||||
|
||||
#define cpu_has_prefetch 1
|
||||
#define cpu_has_ejtag 1
|
||||
#define cpu_has_llsc 1
|
||||
|
||||
#define cpu_has_mips16 1
|
||||
#define cpu_has_mdmx 0
|
||||
#define cpu_has_mips3d 0
|
||||
#define cpu_has_smartmips 0
|
||||
|
||||
#define cpu_has_mips32r1 1
|
||||
#define cpu_has_mips32r2 1
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_mipsmt 0
|
||||
|
||||
#define cpu_has_64bits 0
|
||||
#define cpu_has_64bit_zero_reg 0
|
||||
#define cpu_has_64bit_gp_regs 0
|
||||
#define cpu_has_64bit_addresses 0
|
||||
|
||||
#define cpu_dcache_line_size() 32
|
||||
#define cpu_icache_line_size() 32
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */
|
||||
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
* Atheros AR71xx GPIO API definitions
|
||||
*
|
||||
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_AR71XX_GPIO_H
|
||||
#define __ASM_MACH_AR71XX_GPIO_H
|
||||
|
||||
#define ARCH_NR_GPIOS 64
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
extern unsigned long ar71xx_gpio_count;
|
||||
extern void __ar71xx_gpio_set_value(unsigned gpio, int value);
|
||||
extern int __ar71xx_gpio_get_value(unsigned gpio);
|
||||
int gpio_to_irq(unsigned gpio);
|
||||
int irq_to_gpio(unsigned gpio);
|
||||
|
||||
static inline int gpio_get_value(unsigned gpio)
|
||||
{
|
||||
if (gpio < ar71xx_gpio_count)
|
||||
return __ar71xx_gpio_get_value(gpio);
|
||||
|
||||
return __gpio_get_value(gpio);
|
||||
}
|
||||
|
||||
static inline void gpio_set_value(unsigned gpio, int value)
|
||||
{
|
||||
if (gpio < ar71xx_gpio_count)
|
||||
__ar71xx_gpio_set_value(gpio, value);
|
||||
else
|
||||
__gpio_set_value(gpio, value);
|
||||
}
|
||||
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_GPIO_H */
|
||||
@@ -1,17 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __ASM_MACH_AR71XX_IRQ_H
|
||||
#define __ASM_MACH_AR71XX_IRQ_H
|
||||
|
||||
#define MIPS_CPU_IRQ_BASE 0
|
||||
#define NR_IRQS 80
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_IRQ_H */
|
||||
@@ -1,32 +0,0 @@
|
||||
/*
|
||||
* Atheros AR71xx specific kernel entry setup
|
||||
*
|
||||
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H
|
||||
#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H
|
||||
|
||||
/*
|
||||
* Some bootloaders set the 'Kseg0 coherency algorithm' to
|
||||
* 'Cacheable, noncoherent, write-through, no write allocate'
|
||||
* and this cause performance issues. Let's go and change it to
|
||||
* 'Cacheable, noncoherent, write-back, write allocate'
|
||||
*/
|
||||
.macro kernel_entry_setup
|
||||
mfc0 t0, CP0_CONFIG
|
||||
li t1, ~CONF_CM_CMASK
|
||||
and t0, t1
|
||||
ori t0, CONF_CM_CACHABLE_NONCOHERENT
|
||||
mtc0 t0, CP0_CONFIG
|
||||
nop
|
||||
.endm
|
||||
|
||||
.macro smp_slave_setup
|
||||
.endm
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */
|
||||
@@ -1,66 +0,0 @@
|
||||
/*
|
||||
* MikroTik RouterBOARD 750 definitions
|
||||
*
|
||||
* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef _MACH_RB750_H
|
||||
#define _MACH_RB750_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */
|
||||
#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */
|
||||
#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */
|
||||
#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */
|
||||
#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */
|
||||
#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */
|
||||
#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */
|
||||
#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */
|
||||
#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */
|
||||
#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */
|
||||
#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */
|
||||
#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */
|
||||
#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */
|
||||
#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */
|
||||
#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */
|
||||
|
||||
#define RB750_GPIO_BTN_RESET 1
|
||||
#define RB750_GPIO_SPI_CS0 2
|
||||
#define RB750_GPIO_LED_ACT 12
|
||||
#define RB750_GPIO_LED_PORT1 13
|
||||
#define RB750_GPIO_LED_PORT2 14
|
||||
#define RB750_GPIO_LED_PORT3 15
|
||||
#define RB750_GPIO_LED_PORT4 16
|
||||
#define RB750_GPIO_LED_PORT5 17
|
||||
|
||||
#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT)
|
||||
#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1)
|
||||
#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2)
|
||||
#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3)
|
||||
#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4)
|
||||
#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5)
|
||||
|
||||
#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE)
|
||||
|
||||
#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \
|
||||
RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT)
|
||||
|
||||
struct rb750_led_data {
|
||||
char *name;
|
||||
char *default_trigger;
|
||||
u32 mask;
|
||||
int active_low;
|
||||
};
|
||||
|
||||
struct rb750_led_platform_data {
|
||||
int num_leds;
|
||||
struct rb750_led_data *leds;
|
||||
};
|
||||
|
||||
int rb750_latch_change(u32 mask_clr, u32 mask_set);
|
||||
|
||||
#endif /* _MACH_RB750_H */
|
||||
@@ -1,45 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
|
||||
* Copyright (C) 2003, 2004 Ralf Baechle
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H
|
||||
#define __ASM_MACH_AR71XX_MANGLE_PORT_H
|
||||
|
||||
#define __swizzle_addr_b(port) ((port) ^ 3)
|
||||
#define __swizzle_addr_w(port) ((port) ^ 2)
|
||||
#define __swizzle_addr_l(port) (port)
|
||||
#define __swizzle_addr_q(port) (port)
|
||||
|
||||
#if defined(CONFIG_SWAP_IO_SPACE)
|
||||
|
||||
# define ioswabb(a, x) (x)
|
||||
# define __mem_ioswabb(a, x) (x)
|
||||
# define ioswabw(a, x) le16_to_cpu(x)
|
||||
# define __mem_ioswabw(a, x) (x)
|
||||
# define ioswabl(a, x) le32_to_cpu(x)
|
||||
# define __mem_ioswabl(a, x) (x)
|
||||
# define ioswabq(a, x) le64_to_cpu(x)
|
||||
# define __mem_ioswabq(a, x) (x)
|
||||
|
||||
#else
|
||||
|
||||
# define ioswabb(a, x) (x)
|
||||
# define __mem_ioswabb(a, x) (x)
|
||||
# define ioswabw(a, x) (x)
|
||||
# define __mem_ioswabw(a, x) cpu_to_le16(x)
|
||||
# define ioswabl(a, x) (x)
|
||||
# define __mem_ioswabl(a, x) cpu_to_le32(x)
|
||||
# define ioswabq(a, x) (x)
|
||||
# define __mem_ioswabq(a, x) cpu_to_le64(x)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */
|
||||
@@ -1,46 +0,0 @@
|
||||
/*
|
||||
* Atheros AR71xx SoC specific PCI definitions
|
||||
*
|
||||
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_AR71XX_PCI_H
|
||||
#define __ASM_MACH_AR71XX_PCI_H
|
||||
|
||||
struct pci_dev;
|
||||
|
||||
struct ar71xx_pci_irq {
|
||||
int irq;
|
||||
u8 slot;
|
||||
u8 pin;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
extern int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev);
|
||||
extern unsigned ar71xx_pci_nr_irqs __initdata;
|
||||
extern struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata;
|
||||
|
||||
int ar71xx_pcibios_map_irq(const struct pci_dev *dev,
|
||||
uint8_t slot, uint8_t pin) __init;
|
||||
int ar71xx_pcibios_init(void) __init;
|
||||
|
||||
int ar71xx_pci_be_handler(int is_fixup);
|
||||
|
||||
int ar724x_pcibios_map_irq(const struct pci_dev *dev,
|
||||
uint8_t slot, uint8_t pin) __init;
|
||||
int ar724x_pcibios_init(int irq) __init;
|
||||
|
||||
int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init;
|
||||
#else
|
||||
static inline int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_PCI_H */
|
||||
@@ -1,67 +0,0 @@
|
||||
/*
|
||||
* Atheros AR71xx SoC specific platform data definitions
|
||||
*
|
||||
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_AR71XX_PLATFORM_H
|
||||
#define __ASM_MACH_AR71XX_PLATFORM_H
|
||||
|
||||
#include <linux/if_ether.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
struct ag71xx_switch_platform_data {
|
||||
u8 phy4_mii_en:1;
|
||||
};
|
||||
|
||||
struct ag71xx_platform_data {
|
||||
phy_interface_t phy_if_mode;
|
||||
u32 phy_mask;
|
||||
int speed;
|
||||
int duplex;
|
||||
u32 reset_bit;
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
struct device *mii_bus_dev;
|
||||
|
||||
u8 has_gbit:1;
|
||||
u8 is_ar91xx:1;
|
||||
u8 is_ar7240:1;
|
||||
u8 is_ar724x:1;
|
||||
u8 has_ar8216:1;
|
||||
|
||||
struct ag71xx_switch_platform_data *switch_data;
|
||||
|
||||
void (*ddr_flush)(void);
|
||||
void (*set_speed)(int speed);
|
||||
|
||||
u32 fifo_cfg1;
|
||||
u32 fifo_cfg2;
|
||||
u32 fifo_cfg3;
|
||||
};
|
||||
|
||||
struct ag71xx_mdio_platform_data {
|
||||
u32 phy_mask;
|
||||
int is_ar7240;
|
||||
};
|
||||
|
||||
struct ar71xx_ehci_platform_data {
|
||||
u8 is_ar91xx;
|
||||
};
|
||||
|
||||
struct ar71xx_spi_platform_data {
|
||||
unsigned bus_num;
|
||||
unsigned num_chipselect;
|
||||
u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on);
|
||||
};
|
||||
|
||||
#define AR71XX_SPI_CS_INACTIVE 0
|
||||
#define AR71XX_SPI_CS_ACTIVE 1
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_PLATFORM_H */
|
||||
@@ -1,48 +0,0 @@
|
||||
/*
|
||||
* SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards
|
||||
*
|
||||
* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* This file was based on the patches for Linux 2.6.27.39 published by
|
||||
* MikroTik for their RouterBoard 4xx series devices.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#define CPLD_GPIO_nLED1 0
|
||||
#define CPLD_GPIO_nLED2 1
|
||||
#define CPLD_GPIO_nLED3 2
|
||||
#define CPLD_GPIO_nLED4 3
|
||||
#define CPLD_GPIO_FAN 4
|
||||
#define CPLD_GPIO_ALE 5
|
||||
#define CPLD_GPIO_CLE 6
|
||||
#define CPLD_GPIO_nCE 7
|
||||
#define CPLD_GPIO_nLED5 8
|
||||
|
||||
#define CPLD_NUM_GPIOS 9
|
||||
|
||||
#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1)
|
||||
#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2)
|
||||
#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3)
|
||||
#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4)
|
||||
#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN)
|
||||
#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE)
|
||||
#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE)
|
||||
#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE)
|
||||
#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5)
|
||||
|
||||
struct rb4xx_cpld_platform_data {
|
||||
unsigned gpio_base;
|
||||
};
|
||||
|
||||
extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value);
|
||||
extern int rb4xx_cpld_read(unsigned char *rx_buf,
|
||||
const unsigned char *verify_buf,
|
||||
unsigned cnt);
|
||||
extern int rb4xx_cpld_read_from(unsigned addr,
|
||||
unsigned char *rx_buf,
|
||||
const unsigned char *verify_buf,
|
||||
unsigned cnt);
|
||||
extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count);
|
||||
@@ -1,25 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MACH_AR71XX_WAR_H
|
||||
#define __ASM_MACH_AR71XX_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define RM9000_CDEX_SMP_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MACH_AR71XX_WAR_H */
|
||||
Reference in New Issue
Block a user