qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00
Code Activity

[adm5120] change switch register access macros

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9962 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2007-12-27 14:58:48 +00:00
parent 4bb1a03501
commit 23d61f22e9
9 changed files with 46 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c
View File

@@ -52,21 +52,21 @@ void adm5120_ndelay(u32 ns)
{
u32 t;
SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT);
SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
t = (ns+640) / 640;
t &= TIMER_PERIOD_MASK;
SW_WRITE_REG(TIMER, t | TIMER_TE);
SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
/* wait until the timer expires */
do {
t = SW_READ_REG(TIMER_INT);
t = SW_READ_REG(SWITCH_REG_TIMER_INT);
} while ((t & TIMER_INT_TOS) == 0);
/* leave the timer disabled */
SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT);
SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
}
void __init adm5120_soc_init(void)
@@ -74,7 +74,7 @@ void __init adm5120_soc_init(void)
u32 code;
u32 clks;
code = SW_READ_REG(CODE);
code = SW_READ_REG(SWITCH_REG_CODE);
adm5120_product_code = CODE_GET_PC(code);
adm5120_revision = CODE_GET_REV(code);

8
target/linux/adm5120/files/arch/mips/adm5120/gpio.c
View File

@@ -343,7 +343,7 @@ EXPORT_SYMBOL(adm5120_irq_to_gpio);
void __init adm5120_gpio_csx0_enable(void)
{
gpio_conf2 |= GPIO_CONF2_CSX0;
SW_WRITE_REG(GPIO_CONF2, gpio_conf2);
SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN1].flags &= ~GPIO_FLAG_VALID;
adm5120_gpio_map[ADM5120_GPIO_PIN2].irq = ADM5120_IRQ_GPIO2;
@@ -352,7 +352,7 @@ void __init adm5120_gpio_csx0_enable(void)
void __init adm5120_gpio_csx1_enable(void)
{
gpio_conf2 |= GPIO_CONF2_CSX1;
SW_WRITE_REG(GPIO_CONF2, gpio_conf2);
SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN3].flags &= ~GPIO_FLAG_VALID;
if (adm5120_package_bga())
@@ -362,7 +362,7 @@ void __init adm5120_gpio_csx1_enable(void)
void __init adm5120_gpio_ew_enable(void)
{
gpio_conf2 |= GPIO_CONF2_EW;
SW_WRITE_REG(GPIO_CONF2, gpio_conf2);
SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN0].flags &= ~GPIO_FLAG_VALID;
}
@@ -372,7 +372,7 @@ void __init adm5120_gpio_init(void)
int i;
gpio_conf2 = 0;
SW_WRITE_REG(GPIO_CONF2, gpio_conf2);
SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
for (i = 0; i < ADM5120_GPIO_COUNT; i++)
adm5120_gpio_map[i].flags = GPIO_FLAG_VALID;

4
target/linux/adm5120/files/arch/mips/adm5120/memory.c
View File

@@ -82,7 +82,7 @@ static void __init adm5120_detect_memsize(void)
u32 size, maxsize;
u8 *p;
memctrl = SW_READ_REG(MEMCTRL);
memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL);
switch (memctrl & MEMCTRL_SDRS_MASK) {
case MEMCTRL_SDRS_4M:
maxsize = 4 << 20;
@@ -148,7 +148,7 @@ static void __init adm5120_detect_memsize(void)
memctrl |= MEMCTRL_SDRS_64M;
break;
}
SW_WRITE_REG(MEMCTRL, memctrl);
SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl);
}
out:

2
target/linux/adm5120/files/arch/mips/adm5120/reset.c
View File

@@ -48,7 +48,7 @@ void adm5120_restart(char *command)
if (adm5120_board_reset)
adm5120_board_reset();
SW_WRITE_REG(SOFT_RESET, 1);
SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1);
}
void adm5120_halt(void)