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Code Activity

[adm5120] change switch register access macros

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9962 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2007-12-27 14:58:48 +00:00
parent 4bb1a03501
commit 23d61f22e9
9 changed files with 46 additions and 46 deletions
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12
target/linux/adm5120/files/drivers/char/watchdog/adm5120_wdt.c
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@@ -1,5 +1,5 @@
/*
* ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver
* ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver
* Copyright (c) Ondrej Zajicek <santiago@crfreenet.org>, 2007
*
* based on
@@ -47,26 +47,26 @@ MODULE_LICENSE("GPL");
static inline void wdt_set_timeout(void)
{
u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16);
SW_WRITE_REG(WDOG0, val);
SW_WRITE_REG(SWITCH_REG_WDOG0, val);
}
/*
/*
It looks like WDOG0-register-write don't modify counter,
but WDOG0-register-read resets counter.
*/
static inline void wdt_reset_counter(void)
{
SW_READ_REG(WDOG0);
SW_READ_REG(SWITCH_REG_WDOG0);
}
static inline void wdt_disable(void)
{
SW_WRITE_REG(WDOG0, 0x7FFF0000);
SW_WRITE_REG(SWITCH_REG_WDOG0, 0x7FFF0000);
}
static int wdt_open(struct inode *inode, struct file *file)
{
/* Allow only one person to hold it open */

2
target/linux/adm5120/files/drivers/mtd/maps/adm5120-flash.c
View File

@@ -261,7 +261,7 @@ static int adm5120_flash_initinfo(struct adm5120_flash_info *info,
if (info->amap.window_size == 0) {
/* get memory window size */
t = SW_READ_REG(MEMCTRL) >> fdesc->srs_shift;
t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift;
t &= MEMCTRL_SRS_MASK;
info->amap.window_size = flash_sizes[t];
}

42
target/linux/adm5120/files/drivers/net/adm5120sw.c
View File

@@ -280,56 +280,56 @@ static void sw_dump_regs(void)
{
u32 t;
t = SW_READ_REG(PHY_STATUS);
t = sw_read_reg(SWITCH_REG_PHY_STATUS);
SW_DBG("phy_status: %08X\n", t);
t = SW_READ_REG(CPUP_CONF);
t = sw_read_reg(SWITCH_REG_CPUP_CONF);
SW_DBG("cpup_conf: %08X%s%s%s\n", t,
(t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
(t & CPUP_CONF_CRCP) ? " CRCP" : "",
(t & CPUP_CONF_BTM) ? " BTM" : "");
t = SW_READ_REG(PORT_CONF0);
t = sw_read_reg(SWITCH_REG_PORT_CONF0);
SW_DBG("port_conf0: %08X\n", t);
t = SW_READ_REG(PORT_CONF1);
t = sw_read_reg(SWITCH_REG_PORT_CONF1);
SW_DBG("port_conf1: %08X\n", t);
t = SW_READ_REG(PORT_CONF2);
t = sw_read_reg(SWITCH_REG_PORT_CONF2);
SW_DBG("port_conf2: %08X\n", t);
t = SW_READ_REG(VLAN_G1);
t = sw_read_reg(SWITCH_REG_VLAN_G1);
SW_DBG("vlan g1: %08X\n", t);
t = SW_READ_REG(VLAN_G2);
t = sw_read_reg(SWITCH_REG_VLAN_G2);
SW_DBG("vlan g2: %08X\n", t);
t = SW_READ_REG(BW_CNTL0);
t = sw_read_reg(SWITCH_REG_BW_CNTL0);
SW_DBG("bw_cntl0: %08X\n", t);
t = SW_READ_REG(BW_CNTL1);
t = sw_read_reg(SWITCH_REG_BW_CNTL1);
SW_DBG("bw_cntl1: %08X\n", t);
t = SW_READ_REG(PHY_CNTL0);
t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
SW_DBG("phy_cntl0: %08X\n", t);
t = SW_READ_REG(PHY_CNTL1);
t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
SW_DBG("phy_cntl1: %08X\n", t);
t = SW_READ_REG(PHY_CNTL2);
t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
SW_DBG("phy_cntl2: %08X\n", t);
t = SW_READ_REG(PHY_CNTL3);
t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
SW_DBG("phy_cntl3: %08X\n", t);
t = SW_READ_REG(PHY_CNTL4);
t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
SW_DBG("phy_cntl4: %08X\n", t);
t = SW_READ_REG(INT_STATUS);
t = sw_read_reg(SWITCH_REG_INT_STATUS);
sw_dump_intr_mask("int_status: ", t);
t = SW_READ_REG(INT_MASK);
t = sw_read_reg(SWITCH_REG_INT_MASK);
sw_dump_intr_mask("int_mask: ", t);
t = SW_READ_REG(SHDA);
t = sw_read_reg(SWITCH_REG_SHDA);
SW_DBG("shda: %08X\n", t);
t = SW_READ_REG(SLDA);
t = sw_read_reg(SWITCH_REG_SLDA);
SW_DBG("slda: %08X\n", t);
t = SW_READ_REG(RHDA);
t = sw_read_reg(SWITCH_REG_RHDA);
SW_DBG("rhda: %08X\n", t);
t = SW_READ_REG(RLDA);
t = sw_read_reg(SWITCH_REG_RLDA);
SW_DBG("rlda: %08X\n", t);
}
@@ -1061,7 +1061,7 @@ static int __init adm5120_switch_probe(struct platform_device *pdev)
(SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
(SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
PHY_CNTL2_RMAE;
SW_WRITE_REG(PHY_CNTL2, t);
sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
t |= PHY_CNTL3_RNT;