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git://projects.qi-hardware.com/openwrt-xburst.git
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[adm5120] change switch register access macros
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9962 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@@ -280,56 +280,56 @@ static void sw_dump_regs(void)
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{
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u32 t;
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t = SW_READ_REG(PHY_STATUS);
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t = sw_read_reg(SWITCH_REG_PHY_STATUS);
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SW_DBG("phy_status: %08X\n", t);
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t = SW_READ_REG(CPUP_CONF);
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t = sw_read_reg(SWITCH_REG_CPUP_CONF);
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SW_DBG("cpup_conf: %08X%s%s%s\n", t,
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(t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
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(t & CPUP_CONF_CRCP) ? " CRCP" : "",
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(t & CPUP_CONF_BTM) ? " BTM" : "");
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t = SW_READ_REG(PORT_CONF0);
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t = sw_read_reg(SWITCH_REG_PORT_CONF0);
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SW_DBG("port_conf0: %08X\n", t);
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t = SW_READ_REG(PORT_CONF1);
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t = sw_read_reg(SWITCH_REG_PORT_CONF1);
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SW_DBG("port_conf1: %08X\n", t);
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t = SW_READ_REG(PORT_CONF2);
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t = sw_read_reg(SWITCH_REG_PORT_CONF2);
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SW_DBG("port_conf2: %08X\n", t);
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t = SW_READ_REG(VLAN_G1);
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t = sw_read_reg(SWITCH_REG_VLAN_G1);
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SW_DBG("vlan g1: %08X\n", t);
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t = SW_READ_REG(VLAN_G2);
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t = sw_read_reg(SWITCH_REG_VLAN_G2);
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SW_DBG("vlan g2: %08X\n", t);
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t = SW_READ_REG(BW_CNTL0);
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t = sw_read_reg(SWITCH_REG_BW_CNTL0);
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SW_DBG("bw_cntl0: %08X\n", t);
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t = SW_READ_REG(BW_CNTL1);
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t = sw_read_reg(SWITCH_REG_BW_CNTL1);
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SW_DBG("bw_cntl1: %08X\n", t);
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t = SW_READ_REG(PHY_CNTL0);
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t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
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SW_DBG("phy_cntl0: %08X\n", t);
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t = SW_READ_REG(PHY_CNTL1);
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t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
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SW_DBG("phy_cntl1: %08X\n", t);
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t = SW_READ_REG(PHY_CNTL2);
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t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
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SW_DBG("phy_cntl2: %08X\n", t);
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t = SW_READ_REG(PHY_CNTL3);
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t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
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SW_DBG("phy_cntl3: %08X\n", t);
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t = SW_READ_REG(PHY_CNTL4);
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t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
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SW_DBG("phy_cntl4: %08X\n", t);
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t = SW_READ_REG(INT_STATUS);
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t = sw_read_reg(SWITCH_REG_INT_STATUS);
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sw_dump_intr_mask("int_status: ", t);
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t = SW_READ_REG(INT_MASK);
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t = sw_read_reg(SWITCH_REG_INT_MASK);
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sw_dump_intr_mask("int_mask: ", t);
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t = SW_READ_REG(SHDA);
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t = sw_read_reg(SWITCH_REG_SHDA);
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SW_DBG("shda: %08X\n", t);
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t = SW_READ_REG(SLDA);
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t = sw_read_reg(SWITCH_REG_SLDA);
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SW_DBG("slda: %08X\n", t);
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t = SW_READ_REG(RHDA);
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t = sw_read_reg(SWITCH_REG_RHDA);
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SW_DBG("rhda: %08X\n", t);
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t = SW_READ_REG(RLDA);
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t = sw_read_reg(SWITCH_REG_RLDA);
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SW_DBG("rlda: %08X\n", t);
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}
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@@ -1061,7 +1061,7 @@ static int __init adm5120_switch_probe(struct platform_device *pdev)
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(SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
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(SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
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PHY_CNTL2_RMAE;
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SW_WRITE_REG(PHY_CNTL2, t);
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sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
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t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
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t |= PHY_CNTL3_RNT;
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