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Code

[adm5120] change switch register access macros

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9962 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg 2007-12-27 14:58:48 +00:00
parent 4bb1a03501
commit 23d61f22e9
9 changed files with 46 additions and 46 deletions
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14
target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c
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@ -52,21 +52,21 @@ void adm5120_ndelay(u32 ns)
{ {
u32 t; u32 t;
SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT); SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
t = (ns+640) / 640; t = (ns+640) / 640;
t &= TIMER_PERIOD_MASK; t &= TIMER_PERIOD_MASK;
SW_WRITE_REG(TIMER, t | TIMER_TE); SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
/* wait until the timer expires */ /* wait until the timer expires */
do { do {
t = SW_READ_REG(TIMER_INT); t = SW_READ_REG(SWITCH_REG_TIMER_INT);
} while ((t & TIMER_INT_TOS) == 0); } while ((t & TIMER_INT_TOS) == 0);
/* leave the timer disabled */ /* leave the timer disabled */
SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT); SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
} }
void __init adm5120_soc_init(void) void __init adm5120_soc_init(void)
@ -74,7 +74,7 @@ void __init adm5120_soc_init(void)
u32 code; u32 code;
u32 clks; u32 clks;
code = SW_READ_REG(CODE); code = SW_READ_REG(SWITCH_REG_CODE);
adm5120_product_code = CODE_GET_PC(code); adm5120_product_code = CODE_GET_PC(code);
adm5120_revision = CODE_GET_REV(code); adm5120_revision = CODE_GET_REV(code);

8
target/linux/adm5120/files/arch/mips/adm5120/gpio.c
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@ -343,7 +343,7 @@ EXPORT_SYMBOL(adm5120_irq_to_gpio);
void __init adm5120_gpio_csx0_enable(void) void __init adm5120_gpio_csx0_enable(void)
{ {
gpio_conf2 |= GPIO_CONF2_CSX0; gpio_conf2 |= GPIO_CONF2_CSX0;
SW_WRITE_REG(GPIO_CONF2, gpio_conf2); SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN1].flags &= ~GPIO_FLAG_VALID; adm5120_gpio_map[ADM5120_GPIO_PIN1].flags &= ~GPIO_FLAG_VALID;
adm5120_gpio_map[ADM5120_GPIO_PIN2].irq = ADM5120_IRQ_GPIO2; adm5120_gpio_map[ADM5120_GPIO_PIN2].irq = ADM5120_IRQ_GPIO2;
@ -352,7 +352,7 @@ void __init adm5120_gpio_csx0_enable(void)
void __init adm5120_gpio_csx1_enable(void) void __init adm5120_gpio_csx1_enable(void)
{ {
gpio_conf2 |= GPIO_CONF2_CSX1; gpio_conf2 |= GPIO_CONF2_CSX1;
SW_WRITE_REG(GPIO_CONF2, gpio_conf2); SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN3].flags &= ~GPIO_FLAG_VALID; adm5120_gpio_map[ADM5120_GPIO_PIN3].flags &= ~GPIO_FLAG_VALID;
if (adm5120_package_bga()) if (adm5120_package_bga())
@ -362,7 +362,7 @@ void __init adm5120_gpio_csx1_enable(void)
void __init adm5120_gpio_ew_enable(void) void __init adm5120_gpio_ew_enable(void)
{ {
gpio_conf2 |= GPIO_CONF2_EW; gpio_conf2 |= GPIO_CONF2_EW;
SW_WRITE_REG(GPIO_CONF2, gpio_conf2); SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
adm5120_gpio_map[ADM5120_GPIO_PIN0].flags &= ~GPIO_FLAG_VALID; adm5120_gpio_map[ADM5120_GPIO_PIN0].flags &= ~GPIO_FLAG_VALID;
} }
@ -372,7 +372,7 @@ void __init adm5120_gpio_init(void)
int i; int i;
gpio_conf2 = 0; gpio_conf2 = 0;
SW_WRITE_REG(GPIO_CONF2, gpio_conf2); SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
for (i = 0; i < ADM5120_GPIO_COUNT; i++) for (i = 0; i < ADM5120_GPIO_COUNT; i++)
adm5120_gpio_map[i].flags = GPIO_FLAG_VALID; adm5120_gpio_map[i].flags = GPIO_FLAG_VALID;

4
target/linux/adm5120/files/arch/mips/adm5120/memory.c
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@ -82,7 +82,7 @@ static void __init adm5120_detect_memsize(void)
u32 size, maxsize; u32 size, maxsize;
u8 *p; u8 *p;
memctrl = SW_READ_REG(MEMCTRL); memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL);
switch (memctrl & MEMCTRL_SDRS_MASK) { switch (memctrl & MEMCTRL_SDRS_MASK) {
case MEMCTRL_SDRS_4M: case MEMCTRL_SDRS_4M:
maxsize = 4 << 20; maxsize = 4 << 20;
@ -148,7 +148,7 @@ static void __init adm5120_detect_memsize(void)
memctrl |= MEMCTRL_SDRS_64M; memctrl |= MEMCTRL_SDRS_64M;
break; break;
} }
SW_WRITE_REG(MEMCTRL, memctrl); SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl);
} }
out: out:

2
target/linux/adm5120/files/arch/mips/adm5120/reset.c
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@ -48,7 +48,7 @@ void adm5120_restart(char *command)
if (adm5120_board_reset) if (adm5120_board_reset)
adm5120_board_reset(); adm5120_board_reset();
SW_WRITE_REG(SOFT_RESET, 1); SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1);
} }
void adm5120_halt(void) void adm5120_halt(void)

6
target/linux/adm5120/files/drivers/char/watchdog/adm5120_wdt.c
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@ -47,7 +47,7 @@ MODULE_LICENSE("GPL");
static inline void wdt_set_timeout(void) static inline void wdt_set_timeout(void)
{ {
u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16); u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16);
SW_WRITE_REG(WDOG0, val); SW_WRITE_REG(SWITCH_REG_WDOG0, val);
} }
/* /*
@ -57,12 +57,12 @@ static inline void wdt_set_timeout(void)
static inline void wdt_reset_counter(void) static inline void wdt_reset_counter(void)
{ {
SW_READ_REG(WDOG0); SW_READ_REG(SWITCH_REG_WDOG0);
} }
static inline void wdt_disable(void) static inline void wdt_disable(void)
{ {
SW_WRITE_REG(WDOG0, 0x7FFF0000); SW_WRITE_REG(SWITCH_REG_WDOG0, 0x7FFF0000);
} }

2
target/linux/adm5120/files/drivers/mtd/maps/adm5120-flash.c
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@ -261,7 +261,7 @@ static int adm5120_flash_initinfo(struct adm5120_flash_info *info,
if (info->amap.window_size == 0) { if (info->amap.window_size == 0) {
/* get memory window size */ /* get memory window size */
t = SW_READ_REG(MEMCTRL) >> fdesc->srs_shift; t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift;
t &= MEMCTRL_SRS_MASK; t &= MEMCTRL_SRS_MASK;
info->amap.window_size = flash_sizes[t]; info->amap.window_size = flash_sizes[t];
} }

42
target/linux/adm5120/files/drivers/net/adm5120sw.c
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@ -280,56 +280,56 @@ static void sw_dump_regs(void)
{ {
u32 t; u32 t;
t = SW_READ_REG(PHY_STATUS); t = sw_read_reg(SWITCH_REG_PHY_STATUS);
SW_DBG("phy_status: %08X\n", t); SW_DBG("phy_status: %08X\n", t);
t = SW_READ_REG(CPUP_CONF); t = sw_read_reg(SWITCH_REG_CPUP_CONF);
SW_DBG("cpup_conf: %08X%s%s%s\n", t, SW_DBG("cpup_conf: %08X%s%s%s\n", t,
(t & CPUP_CONF_DCPUP) ? " DCPUP" : "", (t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
(t & CPUP_CONF_CRCP) ? " CRCP" : "", (t & CPUP_CONF_CRCP) ? " CRCP" : "",
(t & CPUP_CONF_BTM) ? " BTM" : ""); (t & CPUP_CONF_BTM) ? " BTM" : "");
t = SW_READ_REG(PORT_CONF0); t = sw_read_reg(SWITCH_REG_PORT_CONF0);
SW_DBG("port_conf0: %08X\n", t); SW_DBG("port_conf0: %08X\n", t);
t = SW_READ_REG(PORT_CONF1); t = sw_read_reg(SWITCH_REG_PORT_CONF1);
SW_DBG("port_conf1: %08X\n", t); SW_DBG("port_conf1: %08X\n", t);
t = SW_READ_REG(PORT_CONF2); t = sw_read_reg(SWITCH_REG_PORT_CONF2);
SW_DBG("port_conf2: %08X\n", t); SW_DBG("port_conf2: %08X\n", t);
t = SW_READ_REG(VLAN_G1); t = sw_read_reg(SWITCH_REG_VLAN_G1);
SW_DBG("vlan g1: %08X\n", t); SW_DBG("vlan g1: %08X\n", t);
t = SW_READ_REG(VLAN_G2); t = sw_read_reg(SWITCH_REG_VLAN_G2);
SW_DBG("vlan g2: %08X\n", t); SW_DBG("vlan g2: %08X\n", t);
t = SW_READ_REG(BW_CNTL0); t = sw_read_reg(SWITCH_REG_BW_CNTL0);
SW_DBG("bw_cntl0: %08X\n", t); SW_DBG("bw_cntl0: %08X\n", t);
t = SW_READ_REG(BW_CNTL1); t = sw_read_reg(SWITCH_REG_BW_CNTL1);
SW_DBG("bw_cntl1: %08X\n", t); SW_DBG("bw_cntl1: %08X\n", t);
t = SW_READ_REG(PHY_CNTL0); t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
SW_DBG("phy_cntl0: %08X\n", t); SW_DBG("phy_cntl0: %08X\n", t);
t = SW_READ_REG(PHY_CNTL1); t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
SW_DBG("phy_cntl1: %08X\n", t); SW_DBG("phy_cntl1: %08X\n", t);
t = SW_READ_REG(PHY_CNTL2); t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
SW_DBG("phy_cntl2: %08X\n", t); SW_DBG("phy_cntl2: %08X\n", t);
t = SW_READ_REG(PHY_CNTL3); t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
SW_DBG("phy_cntl3: %08X\n", t); SW_DBG("phy_cntl3: %08X\n", t);
t = SW_READ_REG(PHY_CNTL4); t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
SW_DBG("phy_cntl4: %08X\n", t); SW_DBG("phy_cntl4: %08X\n", t);
t = SW_READ_REG(INT_STATUS); t = sw_read_reg(SWITCH_REG_INT_STATUS);
sw_dump_intr_mask("int_status: ", t); sw_dump_intr_mask("int_status: ", t);
t = SW_READ_REG(INT_MASK); t = sw_read_reg(SWITCH_REG_INT_MASK);
sw_dump_intr_mask("int_mask: ", t); sw_dump_intr_mask("int_mask: ", t);
t = SW_READ_REG(SHDA); t = sw_read_reg(SWITCH_REG_SHDA);
SW_DBG("shda: %08X\n", t); SW_DBG("shda: %08X\n", t);
t = SW_READ_REG(SLDA); t = sw_read_reg(SWITCH_REG_SLDA);
SW_DBG("slda: %08X\n", t); SW_DBG("slda: %08X\n", t);
t = SW_READ_REG(RHDA); t = sw_read_reg(SWITCH_REG_RHDA);
SW_DBG("rhda: %08X\n", t); SW_DBG("rhda: %08X\n", t);
t = SW_READ_REG(RLDA); t = sw_read_reg(SWITCH_REG_RLDA);
SW_DBG("rlda: %08X\n", t); SW_DBG("rlda: %08X\n", t);
} }
@ -1061,7 +1061,7 @@ static int __init adm5120_switch_probe(struct platform_device *pdev)
(SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) | (SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
(SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) | (SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
PHY_CNTL2_RMAE; PHY_CNTL2_RMAE;
SW_WRITE_REG(PHY_CNTL2, t); sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
t = sw_read_reg(SWITCH_REG_PHY_CNTL3); t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
t |= PHY_CNTL3_RNT; t |= PHY_CNTL3_RNT;

4
target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_nand.h
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@ -65,8 +65,8 @@
static inline void adm5120_nand_enable(void) static inline void adm5120_nand_enable(void)
{ {
SW_WRITE_REG(BW_CNTL1, BW_CNTL1_NAND_ENABLE); SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE);
SW_WRITE_REG(BOOT_DONE, 1); SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1);
} }
static inline void adm5120_nand_set_wpn(unsigned int set) static inline void adm5120_nand_set_wpn(unsigned int set)

4
target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
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@ -32,9 +32,9 @@
#define BITMASK(len) ((1 << (len))-1) #define BITMASK(len) ((1 << (len))-1)
#define SW_READ_REG(r) __raw_readl( \ #define SW_READ_REG(r) __raw_readl( \
(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r) (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
#define SW_WRITE_REG(r, v) __raw_writel((v), \ #define SW_WRITE_REG(r, v) __raw_writel((v), \
(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r) (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
/* Switch register offsets */ /* Switch register offsets */
#define SWITCH_REG_CODE 0x0000 #define SWITCH_REG_CODE 0x0000