mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
fix up eeprom and add ssc driver ... this needs a lot of work
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9761 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
@@ -322,7 +322,6 @@
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#define DANUBE_LED_EDGE_MASK (1 << 26)
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/*------------ GPIO */
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#define DANUBE_GPIO_BASE_ADDR (0xBE100B00)
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@@ -346,4 +345,14 @@
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#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
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#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
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/*------------ SSC */
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#define DANUBE_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)
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#endif
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@@ -32,6 +32,10 @@
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#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
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#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
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#define DANUBE_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
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#define DANUBE_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
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#define DANUBE_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
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#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
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#define MIPS_CPU_TIMER_IRQ 7
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@@ -0,0 +1,119 @@
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//*************************************************************************
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//* Summary of definitions which are used in each peripheral *
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//*************************************************************************
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#ifndef peripheral_definitions_h
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#define peripheral_definitions_h
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////#include "cpu.h"
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//
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///* These files have to be included by each peripheral */
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//#include <sysdefs.h>
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//#include <excep.h>
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//#include <cpusubsys.h>
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//#include <sys_api.h>
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//#include <mips.h>
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//#include "SRAM_address_map.h"
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//
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///* common header files for all CPU's */
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//#include "iiu.h"
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//#include "bcu.h"
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//#include "FPI_address_map.h"
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//#include "direct_interrupts.h"
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/////////////////////////////////////////////////////////////////////////
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//extern int _clz();
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//extern void _nop();
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//extern void _sleep();
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//extern void sys_enable_int();
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typedef unsigned char UINT8;
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typedef signed char INT8;
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typedef unsigned short UINT16;
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typedef signed short INT16;
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typedef unsigned int UINT32;
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typedef signed int INT32;
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typedef unsigned long long UINT64;
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typedef signed long long INT64;
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#define REG8( addr ) (*(volatile UINT8 *) (addr))
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#define REG16( addr ) (*(volatile UINT16 *)(addr))
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#define REG32( addr ) (*(volatile UINT32 *)(addr))
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#define REG64( addr ) (*(volatile UINT64 *)(addr))
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/* define routine to set FPI access in Supervisor Mode */
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#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG)
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/* Supervisor mode ends, following functions will be done in User mode */
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#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm
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/* enable all Interrupts in IIU */
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//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask
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///* get all high priority interrupt bits in IIU */
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//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED)
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///* signal ends of interrupt to IIU */
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//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit
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///* force IIU interrupt register */
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//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data
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///* get all bits of interrupt register */
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//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR)
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/* insert a NOP instruction */
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#define NOP _nop()
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/* CPU goes to power down mode until interrupt occurs */
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#define IFX_CPU_SLEEP _sleep()
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/* enable all interrupts to CPU */
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#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int()
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/* get all low priority interrupt bits in peripheral */
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#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg)
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/* clear low priority interrupt bit in peripheral */
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#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit
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/* write FPI bus */
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#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data
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#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data
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#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data
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/* read FPI bus */
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#define READ_FPI_BYTE(addr) REG8(addr)
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#define READ_FPI_16BIT(addr) REG16(addr)
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#define READ_FPI_32BIT(addr) REG32(addr)
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/* write peripheral register */
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#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
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#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
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#else //not CONFIG_CPU_LITTLE_ENDIAN
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#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
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#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
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#endif //CONFIG_CPU_LITTLE_ENDIAN
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/* read peripheral register */
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#define READ_PERIPHERAL_REGISTER(addr) REG32(addr)
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/* read/modify(or)/write peripheral register */
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#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data
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/* read/modify(and)/write peripheral register */
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#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
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/* CPU-independent mnemonic constants */
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/* CLC register bits */
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#define IFX_CLC_ENABLE 0x00000000
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#define IFX_CLC_DISABLE 0x00000001
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#define IFX_CLC_DISABLE_STATUS 0x00000002
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#define IFX_CLC_SUSPEND_ENABLE 0x00000004
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#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008
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#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010
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#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
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#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00
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#define IFX_CLC_RUN_DIVIDER_OFFSET 8
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#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000
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#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16
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#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
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#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
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/* number of cycles to wait for interrupt service routine to be called */
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#define WAIT_CYCLES 50
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#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */
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258
target/linux/danube/files/include/asm-mips/danube/ifx_ssc.h
Normal file
258
target/linux/danube/files/include/asm-mips/danube/ifx_ssc.h
Normal file
@@ -0,0 +1,258 @@
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/*
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* ifx_ssc.h defines some data sructures used in ifx_ssc.c
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*
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* Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
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*
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*
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*/
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#ifndef __IFX_SSC_H
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#define __IFX_SSC_H
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#ifdef __KERNEL__
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#include <asm/danube/ifx_ssc_defines.h>
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#endif //__KERNEL__
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#define PORT_CNT 1 // assume default value
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/* symbolic constants to be used in SSC routines */
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// ### TO DO: bad performance
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#define IFX_SSC_TXFIFO_ITL 1
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#define IFX_SSC_RXFIFO_ITL 1
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struct ifx_ssc_statistics {
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unsigned int abortErr; /* abort error */
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unsigned int modeErr; /* master/slave mode error */
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unsigned int txOvErr; /* TX Overflow error */
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unsigned int txUnErr; /* TX Underrun error */
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unsigned int rxOvErr; /* RX Overflow error */
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unsigned int rxUnErr; /* RX Underrun error */
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unsigned int rxBytes;
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unsigned int txBytes;
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};
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struct ifx_ssc_hwopts {
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unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */
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unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */
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unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */
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unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */
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unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */
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unsigned int echoMode:1; /* Echo mode */
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unsigned int loopBack:1; /* Loopback mode */
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unsigned int idleValue:1; /* Idle value */
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unsigned int clockPolarity:1; /* Idle clock is high or low */
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unsigned int clockPhase:1; /* Tx on trailing or leading edge */
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unsigned int headingControl:1; /* LSB first or MSB first */
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unsigned int dataWidth:6; /* from 2 up to 32 bits */
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unsigned int masterSelect:1; /* Master or Slave mode */
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unsigned int modeRxTx:2; /* rx/tx mode */
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unsigned int gpoCs:8; /* choose outputs to use for chip select */
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unsigned int gpoInv:8; /* invert GPO outputs */
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};
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struct ifx_ssc_frm_opts {
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bool FrameEnable; // SFCON.SFEN
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unsigned int DataLength; // SFCON.DLEN
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unsigned int PauseLength; // SFCON.PLEN
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unsigned int IdleData; // SFCON.IDAT
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unsigned int IdleClock; // SFCON.ICLK
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bool StopAfterPause; // SFCON.STOP
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};
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struct ifx_ssc_frm_status {
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bool DataBusy; // SFSTAT.DBSY
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bool PauseBusy; // SFSTAT.PBSY
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unsigned int DataCount; // SFSTAT.DCNT
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unsigned int PauseCount; // SFSTAT.PCNT
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bool EnIntAfterData; // SFCON.IBEN
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bool EnIntAfterPause; // SFCON.IAEN
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};
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typedef struct {
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char *buf;
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size_t len;
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} ifx_ssc_buf_item_t;
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// data structures for batch execution
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typedef union {
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struct {
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bool save_options;
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} init;
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ifx_ssc_buf_item_t read;
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ifx_ssc_buf_item_t write;
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ifx_ssc_buf_item_t rd_wr;
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unsigned int set_baudrate;
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struct ifx_ssc_frm_opts set_frm;
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unsigned int set_gpo;
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struct ifx_ssc_hwopts set_hwopts;
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} ifx_ssc_batch_cmd_param;
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struct ifx_ssc_batch_list {
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unsigned int cmd;
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ifx_ssc_batch_cmd_param cmd_param;
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struct ifx_ssc_batch_list *next;
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};
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#ifdef __KERNEL__
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#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
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struct ifx_ssc_port {
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unsigned long mapbase;
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struct ifx_ssc_hwopts opts;
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struct ifx_ssc_statistics stats;
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struct ifx_ssc_frm_status frm_status;
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struct ifx_ssc_frm_opts frm_opts;
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/* wait queue for ifx_ssc_read() */
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wait_queue_head_t rwait, pwait;
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int port_nr;
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char port_is_open; /* exclusive open - boolean */
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// int no_of_bits; /* number of _valid_ bits */
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// int elem_size; /* shift for element (no of bytes)*/
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/* buffer and pointers to the read/write position */
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char *rxbuf; /* buffer for RX */
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char *rxbuf_end; /* buffer end pointer for RX */
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volatile char *rxbuf_ptr; /* buffer write pointer for RX */
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char *txbuf; /* buffer for TX */
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char *txbuf_end; /* buffer end pointer for TX */
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volatile char *txbuf_ptr; /* buffer read pointer for TX */
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unsigned int baud;
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/* each channel has its own interrupts */
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/* (transmit/receive/error/frame) */
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unsigned int txirq, rxirq, errirq, frmirq;
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};
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/* default values for SSC configuration */
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// values of CON
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#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
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#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
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#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
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#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
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#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
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#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
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#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
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#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
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#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
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#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
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// other values
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#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
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#ifdef CONFIG_USE_EMULATOR
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#define IFX_SSC_DEF_BAUDRATE 10000
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#else
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#define IFX_SSC_DEF_BAUDRATE 2000000
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#endif
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#define IFX_SSC_DEF_RMC 0x10
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#define IFX_SSC_DEF_TXFIFO_FL 8
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#define IFX_SSC_DEF_RXFIFO_FL 1
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#if 1 //TODO
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#define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */
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#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
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#else
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#error "what is ur Chip Select???"
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#endif
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#define IFX_SSC_DEF_SFCON 0 /* no serial framing */
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#if 0
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#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
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IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
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#endif
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#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
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IFX_SSC_R_BIT | IFX_SSC_E_BIT
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#endif /* __KERNEL__ */
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// batch execution commands
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#define IFX_SSC_BATCH_CMD_INIT 1
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#define IFX_SSC_BATCH_CMD_READ 2
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#define IFX_SSC_BATCH_CMD_WRITE 3
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#define IFX_SSC_BATCH_CMD_RD_WR 4
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#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
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#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
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#define IFX_SSC_BATCH_CMD_SET_FRM 7
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#define IFX_SSC_BATCH_CMD_SET_GPO 8
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#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
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//#define IFX_SSC_BATCH_CMD_
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//#define IFX_SSC_BATCH_CMD_
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#define IFX_SSC_BATCH_CMD_END_EXEC 0
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/* Macros to configure SSC hardware */
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/* headingControl: */
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#define IFX_SSC_LSB_FIRST 0
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#define IFX_SSC_MSB_FIRST 1
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/* dataWidth: */
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#define IFX_SSC_MIN_DATA_WIDTH 2
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#define IFX_SSC_MAX_DATA_WIDTH 32
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/* master/slave mode select */
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#define IFX_SSC_MASTER_MODE 1
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#define IFX_SSC_SLAVE_MODE 0
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/* rx/tx mode */
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// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
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#define IFX_SSC_MODE_RXTX 0
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#define IFX_SSC_MODE_RX 1
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#define IFX_SSC_MODE_TX 2
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#define IFX_SSC_MODE_OFF 3
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#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
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/* GPO values */
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#define IFX_SSC_MAX_GPO_OUT 7
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#define IFX_SSC_RXREQ_BLOCK_SIZE 32768
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/***********************/
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/* defines for ioctl's */
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/***********************/
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#define IFX_SSC_IOCTL_MAGIC 'S'
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/* read out the statistics */
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#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
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/* clear the statistics */
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#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
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/* set the baudrate */
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#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
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/* get the current baudrate */
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#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
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/* set hardware options */
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#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
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/* get the current hardware options */
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#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
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/* set transmission mode */
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#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
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/* get the current transmission mode */
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#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
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/* abort transmission */
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#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
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#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
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/* set general purpose outputs */
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#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
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/* clear general purpose outputs */
|
||||
#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
|
||||
/* get general purpose outputs */
|
||||
#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
|
||||
|
||||
/*** serial framing ***/
|
||||
/* get status of serial framing */
|
||||
#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
|
||||
/* get counter reload values and control bits */
|
||||
#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
|
||||
/* set counter reload values and control bits */
|
||||
#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
|
||||
|
||||
/*** batch execution ***/
|
||||
/* do batch execution */
|
||||
#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
|
||||
|
||||
#ifdef __KERNEL__
|
||||
// routines from ifx_ssc.c
|
||||
// ### TO DO
|
||||
/* kernel interface for read and write */
|
||||
ssize_t ifx_ssc_kread (int, char *, size_t);
|
||||
ssize_t ifx_ssc_kwrite (int, const char *, size_t);
|
||||
|
||||
#ifdef CONFIG_IFX_VP_KERNEL_TEST
|
||||
void ifx_ssc_tc (void);
|
||||
#endif // CONFIG_IFX_VP_KERNEL_TEST
|
||||
|
||||
#endif //__KERNEL__
|
||||
#endif // __IFX_SSC_H
|
||||
@@ -0,0 +1,547 @@
|
||||
#ifndef IFX_SSC_DEFINES_H
|
||||
#define IFX_SSC_DEFINES_H
|
||||
|
||||
#include "ifx_peripheral_definitions.h"
|
||||
|
||||
/* maximum SSC FIFO size */
|
||||
#define IFX_SSC_MAX_FIFO_SIZE 32
|
||||
|
||||
/* register map of SSC */
|
||||
|
||||
/* address of the Clock Control Register of the SSC */
|
||||
#define IFX_SSC_CLC 0x00000000
|
||||
/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0
|
||||
bit 1 is hardware modified*/
|
||||
#define IFX_SSC_CLC_readmask 0x00FFFFEF
|
||||
#define IFX_SSC_CLC_writemask 0x00FFFF3D
|
||||
#define IFX_SSC_CLC_hwmask 0x00000002
|
||||
#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask)
|
||||
|
||||
/* address of Port Input Select Register of the SSC */
|
||||
#define IFX_SSC_PISEL 0x00000004
|
||||
/* IFX_SSC_PISEL register is significant in lowest three bits only */
|
||||
#define IFX_SSC_PISEL_readmask 0x00000007
|
||||
#define IFX_SSC_PISEL_writemask 0x00000007
|
||||
#define IFX_SSC_PISEL_hwmask 0x00000000
|
||||
#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask)
|
||||
|
||||
/* address of Identification Register of the SSC */
|
||||
#define IFX_SSC_ID 0x00000008
|
||||
/* IFX_SSC_ID register is significant in no bit */
|
||||
#define IFX_SSC_ID_readmask 0x0000FF3F
|
||||
#define IFX_SSC_ID_writemask 0x00000000
|
||||
#define IFX_SSC_ID_hwmask 0x00000000
|
||||
#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask)
|
||||
|
||||
/* address of the Control Register of the SSC */
|
||||
#define IFX_SSC_CON 0x00000010
|
||||
/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */
|
||||
#define IFX_SSC_CON_readmask 0x01DF1FFF
|
||||
#define IFX_SSC_CON_writemask 0x01DF1FFF
|
||||
#define IFX_SSC_CON_hwmask 0x00000000
|
||||
#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask)
|
||||
|
||||
/* address of the Status Register of the SSC */
|
||||
#define IFX_SSC_STATE 0x00000014
|
||||
/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0
|
||||
all bits except 1:0 are hardware modified */
|
||||
#define IFX_SSC_STATE_readmask 0x771F3F87
|
||||
#define IFX_SSC_STATE_writemask 0x00000000
|
||||
#define IFX_SSC_STATE_hwmask 0x771F3F84
|
||||
#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask)
|
||||
|
||||
/* address of the Write Hardware Modified Control Register Bits of the SSC */
|
||||
#define IFX_SSC_WHBSTATE 0x00000018
|
||||
/* IFX_SSC_WHBSTATE register is write only */
|
||||
#define IFX_SSC_WHBSTATE_readmask 0x00000000
|
||||
#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF
|
||||
#define IFX_SSC_WHBSTATE_hwmask 0x00000000
|
||||
#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask)
|
||||
|
||||
/* address of the Baudrate Timer Reload Register of the SSC */
|
||||
#define IFX_SSC_BR 0x00000040
|
||||
/* IFX_SSC_BR register is significant in bit 15 downto 0*/
|
||||
#define IFX_SSC_BR_readmask 0x0000FFFF
|
||||
#define IFX_SSC_BR_writemask 0x0000FFFF
|
||||
#define IFX_SSC_BR_hwmask 0x00000000
|
||||
#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask)
|
||||
|
||||
/* address of the Baudrate Timer Status Register of the SSC */
|
||||
#define IFX_SSC_BRSTAT 0x00000044
|
||||
/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/
|
||||
#define IFX_SSC_BRSTAT_readmask 0x0000FFFF
|
||||
#define IFX_SSC_BRSTAT_writemask 0x00000000
|
||||
#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF
|
||||
#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask)
|
||||
|
||||
/* address of the Transmitter Buffer Register of the SSC */
|
||||
#define IFX_SSC_TB 0x00000020
|
||||
/* IFX_SSC_TB register is significant in bit 31 downto 0*/
|
||||
#define IFX_SSC_TB_readmask 0xFFFFFFFF
|
||||
#define IFX_SSC_TB_writemask 0xFFFFFFFF
|
||||
#define IFX_SSC_TB_hwmask 0x00000000
|
||||
#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask)
|
||||
|
||||
/* address of the Reciver Buffer Register of the SSC */
|
||||
#define IFX_SSC_RB 0x00000024
|
||||
/* IFX_SSC_RB register is significant in no bits*/
|
||||
#define IFX_SSC_RB_readmask 0xFFFFFFFF
|
||||
#define IFX_SSC_RB_writemask 0x00000000
|
||||
#define IFX_SSC_RB_hwmask 0xFFFFFFFF
|
||||
#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask)
|
||||
|
||||
/* address of the Receive FIFO Control Register of the SSC */
|
||||
#define IFX_SSC_RXFCON 0x00000030
|
||||
/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
|
||||
#define IFX_SSC_RXFCON_readmask 0x00003F03
|
||||
#define IFX_SSC_RXFCON_writemask 0x00003F03
|
||||
#define IFX_SSC_RXFCON_hwmask 0x00000000
|
||||
#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask)
|
||||
|
||||
/* address of the Transmit FIFO Control Register of the SSC */
|
||||
#define IFX_SSC_TXFCON 0x00000034
|
||||
/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
|
||||
#define IFX_SSC_TXFCON_readmask 0x00003F03
|
||||
#define IFX_SSC_TXFCON_writemask 0x00003F03
|
||||
#define IFX_SSC_TXFCON_hwmask 0x00000000
|
||||
#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask)
|
||||
|
||||
/* address of the FIFO Status Register of the SSC */
|
||||
#define IFX_SSC_FSTAT 0x00000038
|
||||
/* IFX_SSC_FSTAT register is significant in no bit*/
|
||||
#define IFX_SSC_FSTAT_readmask 0x00003F3F
|
||||
#define IFX_SSC_FSTAT_writemask 0x00000000
|
||||
#define IFX_SSC_FSTAT_hwmask 0x00003F3F
|
||||
#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask)
|
||||
|
||||
/* address of the Data Frame Control register of the SSC */
|
||||
#define IFX_SSC_SFCON 0x00000060
|
||||
#define IFX_SSC_SFCON_readmask 0xFFDFFFFD
|
||||
#define IFX_SSC_SFCON_writemask 0xFFDFFFFD
|
||||
#define IFX_SSC_SFCON_hwmask 0x00000000
|
||||
#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask)
|
||||
|
||||
/* address of the Data Frame Status register of the SSC */
|
||||
#define IFX_SSC_SFSTAT 0x00000064
|
||||
#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3
|
||||
#define IFX_SSC_SFSTAT_writemask 0x00000000
|
||||
#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3
|
||||
#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask)
|
||||
|
||||
/* address of the General Purpose Output Control register of the SSC */
|
||||
#define IFX_SSC_GPOCON 0x00000070
|
||||
#define IFX_SSC_GPOCON_readmask 0x0000FFFF
|
||||
#define IFX_SSC_GPOCON_writemask 0x0000FFFF
|
||||
#define IFX_SSC_GPOCON_hwmask 0x00000000
|
||||
#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask)
|
||||
|
||||
/* address of the General Purpose Output Status register of the SSC */
|
||||
#define IFX_SSC_GPOSTAT 0x00000074
|
||||
#define IFX_SSC_GPOSTAT_readmask 0x000000FF
|
||||
#define IFX_SSC_GPOSTAT_writemask 0x00000000
|
||||
#define IFX_SSC_GPOSTAT_hwmask 0x00000000
|
||||
#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask)
|
||||
|
||||
/* address of the Force GPO Status register of the SSC */
|
||||
#define IFX_SSC_WHBGPOSTAT 0x00000078
|
||||
#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000
|
||||
#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF
|
||||
#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000
|
||||
#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask)
|
||||
|
||||
/* address of the Receive Request Register of the SSC */
|
||||
#define IFX_SSC_RXREQ 0x00000080
|
||||
#define IFX_SSC_RXREQ_readmask 0x0000FFFF
|
||||
#define IFX_SSC_RXREQ_writemask 0x0000FFFF
|
||||
#define IFX_SSC_RXREQ_hwmask 0x00000000
|
||||
#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask)
|
||||
|
||||
/* address of the Receive Count Register of the SSC */
|
||||
#define IFX_SSC_RXCNT 0x00000084
|
||||
#define IFX_SSC_RXCNT_readmask 0x0000FFFF
|
||||
#define IFX_SSC_RXCNT_writemask 0x00000000
|
||||
#define IFX_SSC_RXCNT_hwmask 0x0000FFFF
|
||||
#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask)
|
||||
|
||||
/* address of the DMA Configuration Register of the SSC */
|
||||
#define IFX_SSC_DMACON 0x000000EC
|
||||
#define IFX_SSC_DMACON_readmask 0x0000FFFF
|
||||
#define IFX_SSC_DMACON_writemask 0x00000000
|
||||
#define IFX_SSC_DMACON_hwmask 0x0000FFFF
|
||||
#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask)
|
||||
|
||||
//------------------------------------------------------
|
||||
// interrupt register for enabling interrupts, mask register of irq_reg
|
||||
#define IFX_SSC_IRN_EN 0xF4
|
||||
// read/write
|
||||
#define IFX_SSC_IRN_EN_readmask 0x0000000F
|
||||
#define IFX_SSC_IRN_EN_writemask 0x0000000F
|
||||
#define IFX_SSC_IRN_EN_hwmask 0x00000000
|
||||
#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask)
|
||||
|
||||
// interrupt register for accessing interrupts
|
||||
#define IFX_SSC_IRN_CR 0xF8
|
||||
// read/write
|
||||
#define IFX_SSC_IRN_CR_readmask 0x0000000F
|
||||
#define IFX_SSC_IRN_CR_writemask 0x0000000F
|
||||
#define IFX_SSC_IRN_CR_hwmask 0x0000000F
|
||||
#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask)
|
||||
|
||||
// interrupt register for stimulating interrupts
|
||||
#define IFX_SSC_IRN_ICR 0xFC
|
||||
// read/write
|
||||
#define IFX_SSC_IRN_ICR_readmask 0x0000000F
|
||||
#define IFX_SSC_IRN_ICR_writemask 0x0000000F
|
||||
#define IFX_SSC_IRN_ICR_hwmask 0x00000000
|
||||
#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask)
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Number of IRQs and bitposition of IRQ
|
||||
#define IFX_SSC_NUM_IRQ 4
|
||||
#define IFX_SSC_T_BIT 0x00000001
|
||||
#define IFX_SSC_R_BIT 0x00000002
|
||||
#define IFX_SSC_E_BIT 0x00000004
|
||||
#define IFX_SSC_F_BIT 0x00000008
|
||||
|
||||
/* bit masks for SSC registers */
|
||||
|
||||
/* ID register */
|
||||
#define IFX_SSC_PERID_REV_MASK 0x0000001F
|
||||
#define IFX_SSC_PERID_CFG_MASK 0x00000020
|
||||
#define IFX_SSC_PERID_ID_MASK 0x0000FF00
|
||||
#define IFX_SSC_PERID_REV_OFFSET 0
|
||||
#define IFX_SSC_PERID_CFG_OFFSET 5
|
||||
#define IFX_SSC_PERID_ID_OFFSET 8
|
||||
#define IFX_SSC_PERID_ID 0x45
|
||||
#define IFX_SSC_PERID_DMA_ON 0x00000020
|
||||
#define IFX_SSC_PERID_RXFS_MASK 0x003F0000
|
||||
#define IFX_SSC_PERID_RXFS_OFFSET 16
|
||||
#define IFX_SSC_PERID_TXFS_MASK 0x3F000000
|
||||
#define IFX_SSC_PERID_TXFS_OFFSET 24
|
||||
|
||||
/* PISEL register */
|
||||
#define IFX_SSC_PISEL_MASTER_IN_A 0x0000
|
||||
#define IFX_SSC_PISEL_MASTER_IN_B 0x0001
|
||||
#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000
|
||||
#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002
|
||||
#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000
|
||||
#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004
|
||||
|
||||
/* IFX_SSC_CON register */
|
||||
#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000
|
||||
#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000
|
||||
#define IFX_SSC_CON_IDLE_HIGH 0x00800000
|
||||
#define IFX_SSC_CON_IDLE_LOW 0x00000000
|
||||
#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000
|
||||
#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000
|
||||
#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16
|
||||
#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000
|
||||
#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK)
|
||||
|
||||
#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000
|
||||
#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000
|
||||
|
||||
#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000
|
||||
#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800
|
||||
#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400
|
||||
#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200
|
||||
#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100
|
||||
#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000
|
||||
#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00
|
||||
#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000
|
||||
|
||||
#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080
|
||||
#define IFX_SSC_CON_NO_LOOPBACK 0x00000000
|
||||
#define IFX_SSC_CON_HALF_DUPLEX 0x00000080
|
||||
#define IFX_SSC_CON_FULL_DUPLEX 0x00000000
|
||||
#define IFX_SSC_CON_CLOCK_FALL 0x00000040
|
||||
#define IFX_SSC_CON_CLOCK_RISE 0x00000000
|
||||
#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000
|
||||
#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020
|
||||
#define IFX_SSC_CON_MSB_FIRST 0x00000010
|
||||
#define IFX_SSC_CON_LSB_FIRST 0x00000000
|
||||
#define IFX_SSC_CON_ENABLE_CSB 0x00000008
|
||||
#define IFX_SSC_CON_DISABLE_CSB 0x00000000
|
||||
#define IFX_SSC_CON_INVERT_CSB 0x00000004
|
||||
#define IFX_SSC_CON_TRUE_CSB 0x00000000
|
||||
#define IFX_SSC_CON_RX_OFF 0x00000002
|
||||
#define IFX_SSC_CON_RX_ON 0x00000000
|
||||
#define IFX_SSC_CON_TX_OFF 0x00000001
|
||||
#define IFX_SSC_CON_TX_ON 0x00000000
|
||||
|
||||
/* IFX_SSC_STATE register */
|
||||
#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28
|
||||
#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000
|
||||
#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET)
|
||||
#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24
|
||||
#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000
|
||||
#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET)
|
||||
#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16
|
||||
#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000
|
||||
#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1)
|
||||
#define IFX_SSC_STATE_BUSY 0x00002000
|
||||
#define IFX_SSC_STATE_RX_UFL 0x00001000
|
||||
#define IFX_SSC_STATE_TX_UFL 0x00000800
|
||||
#define IFX_SSC_STATE_ABORT_ERR 0x00000400
|
||||
#define IFX_SSC_STATE_RX_OFL 0x00000200
|
||||
#define IFX_SSC_STATE_TX_OFL 0x00000100
|
||||
#define IFX_SSC_STATE_MODE_ERR 0x00000080
|
||||
#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004
|
||||
#define IFX_SSC_STATE_IS_MASTER 0x00000002
|
||||
#define IFX_SSC_STATE_IS_ENABLED 0x00000001
|
||||
|
||||
/* WHBSTATE register */
|
||||
#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001
|
||||
#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001
|
||||
#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001
|
||||
|
||||
#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002
|
||||
#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002
|
||||
#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002
|
||||
|
||||
#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004
|
||||
#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004
|
||||
|
||||
#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008
|
||||
#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008
|
||||
|
||||
#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010
|
||||
#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020
|
||||
|
||||
#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040
|
||||
#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080
|
||||
|
||||
#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100
|
||||
#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200
|
||||
#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400
|
||||
#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800
|
||||
#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000
|
||||
#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000
|
||||
#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000
|
||||
#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000
|
||||
#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50
|
||||
#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0
|
||||
|
||||
/* BR register */
|
||||
#define IFX_SSC_BR_BAUDRATE_OFFSET 0
|
||||
#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF
|
||||
|
||||
/* BR_STAT register */
|
||||
#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0
|
||||
#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF
|
||||
|
||||
/* TB register */
|
||||
#define IFX_SSC_TB_DATA_OFFSET 0
|
||||
#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF
|
||||
|
||||
/* RB register */
|
||||
#define IFX_SSC_RB_DATA_OFFSET 0
|
||||
#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF
|
||||
|
||||
/* RXFCON and TXFCON registers */
|
||||
#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000
|
||||
#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001
|
||||
#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002
|
||||
#define IFX_SSC_XFCON_ITL_MASK 0x00003F00
|
||||
#define IFX_SSC_XFCON_ITL_OFFSET 8
|
||||
|
||||
/* FSTAT register */
|
||||
#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0
|
||||
#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F
|
||||
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8
|
||||
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00
|
||||
|
||||
/* GPOCON register */
|
||||
#define IFX_SSC_GPOCON_INVOUT0_POS 0
|
||||
#define IFX_SSC_GPOCON_INV_OUT0 0x00000001
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT1_POS 1
|
||||
#define IFX_SSC_GPOCON_INV_OUT1 0x00000002
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT2_POS 2
|
||||
#define IFX_SSC_GPOCON_INV_OUT2 0x00000003
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT3_POS 3
|
||||
#define IFX_SSC_GPOCON_INV_OUT3 0x00000008
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT4_POS 4
|
||||
#define IFX_SSC_GPOCON_INV_OUT4 0x00000010
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT5_POS 5
|
||||
#define IFX_SSC_GPOCON_INV_OUT5 0x00000020
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT6_POS 6
|
||||
#define IFX_SSC_GPOCON_INV_OUT6 0x00000040
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000
|
||||
#define IFX_SSC_GPOCON_INVOUT7_POS 7
|
||||
#define IFX_SSC_GPOCON_INV_OUT7 0x00000080
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000
|
||||
#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF
|
||||
#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000
|
||||
|
||||
#define IFX_SSC_GPOCON_ISCSB0_POS 8
|
||||
#define IFX_SSC_GPOCON_IS_CSB0 0x00000100
|
||||
#define IFX_SSC_GPOCON_IS_GPO0 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB1_POS 9
|
||||
#define IFX_SSC_GPOCON_IS_CSB1 0x00000200
|
||||
#define IFX_SSC_GPOCON_IS_GPO1 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB2_POS 10
|
||||
#define IFX_SSC_GPOCON_IS_CSB2 0x00000400
|
||||
#define IFX_SSC_GPOCON_IS_GPO2 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB3_POS 11
|
||||
#define IFX_SSC_GPOCON_IS_CSB3 0x00000800
|
||||
#define IFX_SSC_GPOCON_IS_GPO3 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB4_POS 12
|
||||
#define IFX_SSC_GPOCON_IS_CSB4 0x00001000
|
||||
#define IFX_SSC_GPOCON_IS_GPO4 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB5_POS 13
|
||||
#define IFX_SSC_GPOCON_IS_CSB5 0x00002000
|
||||
#define IFX_SSC_GPOCON_IS_GPO5 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB6_POS 14
|
||||
#define IFX_SSC_GPOCON_IS_CSB6 0x00004000
|
||||
#define IFX_SSC_GPOCON_IS_GPO6 0x00000000
|
||||
#define IFX_SSC_GPOCON_ISCSB7_POS 15
|
||||
#define IFX_SSC_GPOCON_IS_CSB7 0x00008000
|
||||
#define IFX_SSC_GPOCON_IS_GPO7 0x00000000
|
||||
#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00
|
||||
#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000
|
||||
|
||||
/* GPOSTAT register */
|
||||
#define IFX_SSC_GPOSTAT_OUT0 0x00000001
|
||||
#define IFX_SSC_GPOSTAT_OUT1 0x00000002
|
||||
#define IFX_SSC_GPOSTAT_OUT2 0x00000004
|
||||
#define IFX_SSC_GPOSTAT_OUT3 0x00000008
|
||||
#define IFX_SSC_GPOSTAT_OUT4 0x00000010
|
||||
#define IFX_SSC_GPOSTAT_OUT5 0x00000020
|
||||
#define IFX_SSC_GPOSTAT_OUT6 0x00000040
|
||||
#define IFX_SSC_GPOSTAT_OUT7 0x00000080
|
||||
#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF
|
||||
|
||||
/* WHBGPOSTAT register */
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040
|
||||
#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080
|
||||
#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF
|
||||
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6
|
||||
#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7
|
||||
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000
|
||||
#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000
|
||||
#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00
|
||||
|
||||
/* SFCON register */
|
||||
#define IFX_SSC_SFCON_SF_ENABLE 0x00000001
|
||||
#define IFX_SSC_SFCON_SF_DISABLE 0x00000000
|
||||
#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004
|
||||
#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000
|
||||
#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008
|
||||
#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000
|
||||
#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0
|
||||
#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000
|
||||
#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000
|
||||
#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000
|
||||
#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000
|
||||
#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000
|
||||
#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000
|
||||
#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22
|
||||
#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096
|
||||
#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024
|
||||
|
||||
#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET)
|
||||
#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET)
|
||||
#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK)
|
||||
#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
|
||||
|
||||
/* SFSTAT register */
|
||||
#define IFX_SSC_SFSTAT_IN_DATA 0x00000001
|
||||
#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002
|
||||
#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0
|
||||
#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4
|
||||
#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000
|
||||
#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20
|
||||
|
||||
#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET)
|
||||
#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET)
|
||||
|
||||
/* RXREQ register */
|
||||
#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF
|
||||
#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0
|
||||
|
||||
/* RXCNT register */
|
||||
#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF
|
||||
#define IFX_SSC_RXCNT_TODO_OFFSET 0
|
||||
|
||||
/* DMACON register */
|
||||
#define IFX_SSC_DMACON_RXON 0x00000001
|
||||
#define IFX_SSC_DMACON_RXOFF 0x00000000
|
||||
#define IFX_SSC_DMACON_TXON 0x00000002
|
||||
#define IFX_SSC_DMACON_TXOFF 0x00000000
|
||||
#define IFX_SSC_DMACON_DMAON 0x00000003
|
||||
#define IFX_SSC_DMACON_DMAOFF 0x00000000
|
||||
#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C
|
||||
#define IFX_SSC_DMACON_CLASS_OFFSET 2
|
||||
|
||||
/* register access macros */
|
||||
#define ifx_ssc_fstat_received_words(status) (status & 0x003F)
|
||||
#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8)
|
||||
|
||||
#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE))
|
||||
#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON))
|
||||
#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON))
|
||||
#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE))
|
||||
#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB))
|
||||
#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB))
|
||||
#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT))
|
||||
#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR))
|
||||
|
||||
#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET)
|
||||
#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user