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mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00

[adm5120] cleanup files using checkpatch.pl

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27162 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
2011-06-12 19:17:57 +00:00
parent 9f0d58cb15
commit 27e94101de
42 changed files with 294 additions and 290 deletions

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@@ -89,7 +89,7 @@ enum {
/*
* TODO:remove adm5120_eth* variables when the switch driver will be
* converted into a real platform driver
* converted into a real platform driver
*/
extern unsigned int adm5120_eth_num_ports;
extern unsigned char adm5120_eth_macs[6][6];

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@@ -48,16 +48,16 @@
/*
* INTC register bits
*/
#define INTC_INT_TIMER ( 1 << INTC_IRQ_TIMER )
#define INTC_INT_UART0 ( 1 << INTC_IRQ_UART0 )
#define INTC_INT_UART1 ( 1 << INTC_IRQ_UART1 )
#define INTC_INT_USBC ( 1 << INTC_IRQ_USBC )
#define INTC_INT_INTX0 ( 1 << INTC_IRQ_INTX0 )
#define INTC_INT_INTX1 ( 1 << INTC_IRQ_INTX1 )
#define INTC_INT_PCI0 ( 1 << INTC_IRQ_PCI0 )
#define INTC_INT_PCI1 ( 1 << INTC_IRQ_PCI1 )
#define INTC_INT_PCI2 ( 1 << INTC_IRQ_PCI2 )
#define INTC_INT_SWITCH ( 1 << INTC_IRQ_SWITCH )
#define INTC_INT_ALL (( 1 << INTC_IRQ_COUNT)-1)
#define INTC_INT_TIMER (1 << INTC_IRQ_TIMER)
#define INTC_INT_UART0 (1 << INTC_IRQ_UART0)
#define INTC_INT_UART1 (1 << INTC_IRQ_UART1)
#define INTC_INT_USBC (1 << INTC_IRQ_USBC)
#define INTC_INT_INTX0 (1 << INTC_IRQ_INTX0)
#define INTC_INT_INTX1 (1 << INTC_IRQ_INTX1)
#define INTC_INT_PCI0 (1 << INTC_IRQ_PCI0)
#define INTC_INT_PCI1 (1 << INTC_IRQ_PCI1)
#define INTC_INT_PCI2 (1 << INTC_IRQ_PCI2)
#define INTC_INT_SWITCH (1 << INTC_IRQ_SWITCH)
#define INTC_INT_ALL ((1 << INTC_IRQ_COUNT) - 1)
#endif /* _MACH_ADM5120_INTC_H */

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@@ -44,25 +44,25 @@
#define MPMC_REG_SC3 0x0260
/* Control register bits */
#define MPMC_CTRL_AM ( 1 << 1 ) /* Address Mirror */
#define MPMC_CTRL_LPM ( 1 << 2 ) /* Low Power Mode */
#define MPMC_CTRL_DWB ( 1 << 3 ) /* Drain Write Buffers */
#define MPMC_CTRL_AM (1 << 1) /* Address Mirror */
#define MPMC_CTRL_LPM (1 << 2) /* Low Power Mode */
#define MPMC_CTRL_DWB (1 << 3) /* Drain Write Buffers */
/* Status register bits */
#define MPMC_STATUS_BUSY ( 1 << 0 ) /* Busy */
#define MPMC_STATUS_WBS ( 1 << 1 ) /* Write Buffer Status */
#define MPMC_STATUS_SRA ( 1 << 2 ) /* Self-Refresh Acknowledge*/
#define MPMC_STATUS_BUSY (1 << 0) /* Busy */
#define MPMC_STATUS_WBS (1 << 1) /* Write Buffer Status */
#define MPMC_STATUS_SRA (1 << 2) /* Self-Refresh Acknowledge*/
/* Dynamic Control register bits */
#define MPMC_DC_CE ( 1 << 0 )
#define MPMC_DC_DMC ( 1 << 1 )
#define MPMC_DC_SRR ( 1 << 2 )
#define MPMC_DC_CE (1 << 0)
#define MPMC_DC_DMC (1 << 1)
#define MPMC_DC_SRR (1 << 2)
#define MPMC_DC_SI_SHIFT 7
#define MPMC_DC_SI_MASK ( 3 << 7 )
#define MPMC_DC_SI_NORMAL ( 0 << 7 )
#define MPMC_DC_SI_MODE ( 1 << 7 )
#define MPMC_DC_SI_PALL ( 2 << 7 )
#define MPMC_DC_SI_NOP ( 3 << 7 )
#define MPMC_DC_SI_MASK (3 << 7)
#define MPMC_DC_SI_NORMAL (0 << 7)
#define MPMC_DC_SI_MODE (1 << 7)
#define MPMC_DC_SI_PALL (2 << 7)
#define MPMC_DC_SI_NOP (3 << 7)
#define SRAM_REG_CONF 0x00
#define SRAM_REG_WWE 0x04

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@@ -46,7 +46,7 @@
#define NAND_READ_REG(r) \
readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
#define NAND_WRITE_REG(r, v) \
writeb((v),(void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
writeb((v), (void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
/*-------------------------------------------------------------------------*/

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@@ -45,7 +45,7 @@ struct adm5120_pci_irq {
unsigned irq;
};
#define PCIIRQ(s,f,p,i) {.slot = (s), .func = (f), .pin = (p), .irq = (i)}
#define PCIIRQ(s, f, p, i) {.slot = (s), .func = (f), .pin = (p), .irq = (i)}
#ifdef CONFIG_PCI
extern void adm5120_pci_set_irq_map(unsigned int nr_irqs,
@@ -73,7 +73,7 @@ extern void adm5120_add_device_gpio_buttons(unsigned nbuttons,
#define GPIO_LED_DEF(g, n, t, a) { \
.name = (n), \
.default_trigger = (t), \
.default_trigger = (t), \
.gpio = (g), \
.active_low = (a) \
}

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@@ -27,38 +27,38 @@
#define UART_REG_FLAG 0x18
/* Receive Status Register bits */
#define UART_RSR_FE ( 1 << 0 )
#define UART_RSR_PE ( 1 << 1 )
#define UART_RSR_BE ( 1 << 2 )
#define UART_RSR_OE ( 1 << 3 )
#define UART_RSR_ERR ( UART_RSR_FE | UART_RSR_PE | UART_RSR_BE )
#define UART_RSR_FE (1 << 0)
#define UART_RSR_PE (1 << 1)
#define UART_RSR_BE (1 << 2)
#define UART_RSR_OE (1 << 3)
#define UART_RSR_ERR (UART_RSR_FE | UART_RSR_PE | UART_RSR_BE)
#define UART_ECR_ALL 0xFF
/* Line Control High register bits */
#define UART_LCRH_BRK ( 1 << 0 ) /* send break */
#define UART_LCRH_PEN ( 1 << 1 ) /* parity enable */
#define UART_LCRH_EPS ( 1 << 2 ) /* even parity select */
#define UART_LCRH_STP1 ( 0 << 3 ) /* one stop bits select */
#define UART_LCRH_STP2 ( 1 << 3 ) /* two stop bits select */
#define UART_LCRH_FEN ( 1 << 4 ) /* FIFO enable */
#define UART_LCRH_BRK (1 << 0) /* send break */
#define UART_LCRH_PEN (1 << 1) /* parity enable */
#define UART_LCRH_EPS (1 << 2) /* even parity select */
#define UART_LCRH_STP1 (0 << 3) /* one stop bits select */
#define UART_LCRH_STP2 (1 << 3) /* two stop bits select */
#define UART_LCRH_FEN (1 << 4) /* FIFO enable */
#define UART_LCRH_WLEN5 ( 0 << 5 )
#define UART_LCRH_WLEN6 ( 1 << 5 )
#define UART_LCRH_WLEN7 ( 2 << 5 )
#define UART_LCRH_WLEN8 ( 3 << 5 )
#define UART_LCRH_WLEN5 (0 << 5)
#define UART_LCRH_WLEN6 (1 << 5)
#define UART_LCRH_WLEN7 (2 << 5)
#define UART_LCRH_WLEN8 (3 << 5)
/* Control register bits */
#define UART_CTRL_EN ( 1 << 0 )
#define UART_CTRL_EN (1 << 0)
/* Flag register bits */
#define UART_FLAG_CTS ( 1 << 0 )
#define UART_FLAG_DSR ( 1 << 1 )
#define UART_FLAG_DCD ( 1 << 2 )
#define UART_FLAG_BUSY ( 1 << 3 )
#define UART_FLAG_RXFE ( 1 << 4 )
#define UART_FLAG_TXFF ( 1 << 5 )
#define UART_FLAG_RXFF ( 1 << 6 )
#define UART_FLAG_TXFE ( 1 << 7 )
#define UART_FLAG_CTS (1 << 0)
#define UART_FLAG_DSR (1 << 1)
#define UART_FLAG_DCD (1 << 2)
#define UART_FLAG_BUSY (1 << 3)
#define UART_FLAG_RXFE (1 << 4)
#define UART_FLAG_TXFF (1 << 5)
#define UART_FLAG_RXFF (1 << 6)
#define UART_FLAG_TXFE (1 << 7)
#endif /* _MACH_ADM5120_UART_H */