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[xburst] Add 2.6.36 patches
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23421 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
lars
334
target/linux/xburst/patches-2.6.36/001-xburst-cache-quirks.patch
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334
target/linux/xburst/patches-2.6.36/001-xburst-cache-quirks.patch
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@@ -0,0 +1,334 @@
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From 3679ae9872aef12529b332767e32097aa8233904 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 24 Apr 2010 17:34:29 +0200
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Subject: [PATCH] JZ4740 cache quirks
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---
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arch/mips/include/asm/r4kcache.h | 231 ++++++++++++++++++++++++++++++++++++++
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1 files changed, 231 insertions(+), 0 deletions(-)
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--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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@@ -17,6 +17,58 @@
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#include <asm/cpu-features.h>
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#include <asm/mipsmtregs.h>
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+#ifdef CONFIG_JZRISC
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+
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+#define K0_TO_K1() \
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+do { \
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+ unsigned long __k0_addr; \
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+ \
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+ __asm__ __volatile__( \
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+ "la %0, 1f\n\t" \
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+ "or %0, %0, %1\n\t" \
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+ "jr %0\n\t" \
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+ "nop\n\t" \
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+ "1: nop\n" \
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+ : "=&r"(__k0_addr) \
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+ : "r" (0x20000000) ); \
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+} while(0)
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+
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+#define K1_TO_K0() \
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+do { \
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+ unsigned long __k0_addr; \
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+ __asm__ __volatile__( \
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+ "nop;nop;nop;nop;nop;nop;nop\n\t" \
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+ "la %0, 1f\n\t" \
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+ "jr %0\n\t" \
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+ "nop\n\t" \
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+ "1: nop\n" \
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+ : "=&r" (__k0_addr)); \
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+} while (0)
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+
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+#define INVALIDATE_BTB() \
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+do { \
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+ unsigned long tmp; \
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+ __asm__ __volatile__( \
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+ ".set mips32\n\t" \
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+ "mfc0 %0, $16, 7\n\t" \
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+ "nop\n\t" \
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+ "ori %0, 2\n\t" \
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+ "mtc0 %0, $16, 7\n\t" \
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+ "nop\n\t" \
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+ : "=&r" (tmp)); \
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+} while (0)
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+
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+#define SYNC_WB() __asm__ __volatile__ ("sync")
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+
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+#else /* CONFIG_JZRISC */
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+
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+#define K0_TO_K1() do { } while (0)
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+#define K1_TO_K0() do { } while (0)
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+#define INVALIDATE_BTB() do { } while (0)
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+#define SYNC_WB() do { } while (0)
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+
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+#endif /* CONFIG_JZRISC */
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+
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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@@ -144,6 +196,7 @@ static inline void flush_icache_line_ind
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{
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__iflush_prologue
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cache_op(Index_Invalidate_I, addr);
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+ INVALIDATE_BTB();
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__iflush_epilogue
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}
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@@ -151,6 +204,7 @@ static inline void flush_dcache_line_ind
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{
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__dflush_prologue
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cache_op(Index_Writeback_Inv_D, addr);
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+ SYNC_WB();
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__dflush_epilogue
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}
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@@ -163,6 +217,7 @@ static inline void flush_icache_line(uns
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{
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__iflush_prologue
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cache_op(Hit_Invalidate_I, addr);
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+ INVALIDATE_BTB();
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__iflush_epilogue
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}
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@@ -170,6 +225,7 @@ static inline void flush_dcache_line(uns
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{
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__dflush_prologue
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cache_op(Hit_Writeback_Inv_D, addr);
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+ SYNC_WB();
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__dflush_epilogue
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}
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@@ -177,6 +233,7 @@ static inline void invalidate_dcache_lin
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{
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__dflush_prologue
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cache_op(Hit_Invalidate_D, addr);
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+ SYNC_WB();
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__dflush_epilogue
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}
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@@ -209,6 +266,7 @@ static inline void flush_scache_line(uns
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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protected_cache_op(Hit_Invalidate_I, addr);
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+ INVALIDATE_BTB();
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}
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/*
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@@ -220,6 +278,7 @@ static inline void protected_flush_icach
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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protected_cache_op(Hit_Writeback_Inv_D, addr);
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+ SYNC_WB();
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}
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static inline void protected_writeback_scache_line(unsigned long addr)
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@@ -396,8 +455,10 @@ static inline void blast_##pfx##cache##l
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
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+#ifndef CONFIG_JZRISC
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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+#endif
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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@@ -405,12 +466,122 @@ __BUILD_BLAST_CACHE(s, scache, Index_Wri
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__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
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+#ifndef CONFIG_JZRISC
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
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+#endif
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
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__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
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+#ifdef CONFIG_JZRISC
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+
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+static inline void blast_dcache32(void)
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+{
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+ unsigned long start = INDEX_BASE;
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+ unsigned long end = start + current_cpu_data.dcache.waysize;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc)
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+ for (addr = start; addr < end; addr += 0x400)
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+ cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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+
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+ SYNC_WB();
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+}
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+
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+static inline void blast_dcache32_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = page + PAGE_SIZE;
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+
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+ do {
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+ cache32_unroll32(start,Hit_Writeback_Inv_D);
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+ start += 0x400;
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+ } while (start < end);
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+
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+ SYNC_WB();
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+}
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+
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+static inline void blast_dcache32_page_indexed(unsigned long page)
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+{
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+ unsigned long indexmask = current_cpu_data.dcache.waysize - 1;
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+ unsigned long start = INDEX_BASE + (page & indexmask);
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc)
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+ for (addr = start; addr < end; addr += 0x400)
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+ cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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+
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+ SYNC_WB();
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+}
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+
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+static inline void blast_icache32(void)
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+{
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+ unsigned long start = INDEX_BASE;
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+ unsigned long end = start + current_cpu_data.icache.waysize;
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+ unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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+ unsigned long ws_end = current_cpu_data.icache.ways <<
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+ current_cpu_data.icache.waybit;
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+ unsigned long ws, addr;
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+
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+ K0_TO_K1();
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc)
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+ for (addr = start; addr < end; addr += 0x400)
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+ cache32_unroll32(addr|ws,Index_Invalidate_I);
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+
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+ INVALIDATE_BTB();
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+
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+ K1_TO_K0();
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+}
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+
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+static inline void blast_icache32_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = page + PAGE_SIZE;
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+
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+ K0_TO_K1();
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+
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+ do {
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+ cache32_unroll32(start,Hit_Invalidate_I);
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+ start += 0x400;
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+ } while (start < end);
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+
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+ INVALIDATE_BTB();
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+
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+ K1_TO_K0();
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+}
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+
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+static inline void blast_icache32_page_indexed(unsigned long page)
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+{
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+ unsigned long indexmask = current_cpu_data.icache.waysize - 1;
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+ unsigned long start = INDEX_BASE + (page & indexmask);
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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+ unsigned long ws_end = current_cpu_data.icache.ways <<
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+ current_cpu_data.icache.waybit;
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+ unsigned long ws, addr;
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+
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+ K0_TO_K1();
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc)
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+ for (addr = start; addr < end; addr += 0x400)
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+ cache32_unroll32(addr|ws,Index_Invalidate_I);
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+
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+ INVALIDATE_BTB();
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+
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+ K1_TO_K0();
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+}
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+
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+#endif /* CONFIG_JZRISC */
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+
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/* build blast_xxx_range, protected_blast_xxx_range */
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#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
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static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
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@@ -432,13 +603,73 @@ static inline void prot##blast_##pfx##ca
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__##pfx##flush_epilogue \
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}
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+#ifndef CONFIG_JZRISC
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
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+#endif
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
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+#ifndef CONFIG_JZRISC
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
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+#endif
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
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/* blast_inv_dcache_range */
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__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
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__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
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+#ifdef CONFIG_JZRISC
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+
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+static inline void protected_blast_dcache_range(unsigned long start,
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+ unsigned long end)
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+{
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+ unsigned long lsize = cpu_dcache_line_size();
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+ unsigned long addr = start & ~(lsize - 1);
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+ unsigned long aend = (end - 1) & ~(lsize - 1);
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+
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+ while (1) {
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+ protected_cache_op(Hit_Writeback_Inv_D, addr);
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+ if (addr == aend)
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+ break;
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+ addr += lsize;
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+ }
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+ SYNC_WB();
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+}
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+
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+static inline void protected_blast_icache_range(unsigned long start,
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+ unsigned long end)
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+{
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+ unsigned long lsize = cpu_icache_line_size();
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+ unsigned long addr = start & ~(lsize - 1);
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+ unsigned long aend = (end - 1) & ~(lsize - 1);
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+
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+ K0_TO_K1();
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+
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+ while (1) {
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+ protected_cache_op(Hit_Invalidate_I, addr);
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+ if (addr == aend)
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+ break;
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+ addr += lsize;
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+ }
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+ INVALIDATE_BTB();
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+
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+ K1_TO_K0();
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+}
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+
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+static inline void blast_dcache_range(unsigned long start,
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+ unsigned long end)
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+{
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+ unsigned long lsize = cpu_dcache_line_size();
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+ unsigned long addr = start & ~(lsize - 1);
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+ unsigned long aend = (end - 1) & ~(lsize - 1);
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+
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+ while (1) {
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+ cache_op(Hit_Writeback_Inv_D, addr);
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+ if (addr == aend)
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+ break;
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+ addr += lsize;
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+ }
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+ SYNC_WB();
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+}
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+
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+#endif /* CONFIG_JZRISC */
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+
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#endif /* _ASM_R4KCACHE_H */
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