mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
split patch; start irq cleanup
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@3117 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
mbm
488
target/linux/aruba-2.6/patches/002-irq.patch
Normal file
488
target/linux/aruba-2.6/patches/002-irq.patch
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@@ -0,0 +1,488 @@
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diff -Nur linux-2.6.15/arch/mips/aruba/idtIRQ.S linux-2.6.15-openwrt/arch/mips/aruba/idtIRQ.S
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--- linux-2.6.15/arch/mips/aruba/idtIRQ.S 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.15-openwrt/arch/mips/aruba/idtIRQ.S 2006-01-10 00:32:32.000000000 +0100
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@@ -0,0 +1,87 @@
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+/**************************************************************************
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+ *
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+ * BRIEF MODULE DESCRIPTION
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+ * Intterrupt dispatcher code for IDT boards
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+ *
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+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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||||
+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
||||
+ * option) any later version.
|
||||
+ *
|
||||
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
+ *
|
||||
+ * You should have received a copy of the GNU General Public License along
|
||||
+ * with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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||||
+ *
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||||
+ *
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||||
+ **************************************************************************
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||||
+ * May 2004 rkt, neb
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||||
+ *
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+ * Initial Release
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+ *
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||||
+ *
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||||
+ *
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||||
+ **************************************************************************
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||||
+ */
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+
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+
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+#include <asm/asm.h>
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+#include <asm/mipsregs.h>
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+#include <asm/regdef.h>
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+#include <asm/stackframe.h>
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+
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+ .text
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+ .set noreorder
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+ .set noat
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+ .align 5
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+ NESTED(idtIRQ, PT_SIZE, sp)
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+ .set noat
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+ SAVE_ALL
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+ CLI
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+
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+ .set at
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+ .set noreorder
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+
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+ /* Get the pending interrupts */
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+ mfc0 t0, CP0_CAUSE
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+ nop
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+
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+ /* Isolate the allowed ones by anding the irq mask */
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+ mfc0 t2, CP0_STATUS
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+ move a1, sp /* need a nop here, hence we anticipate */
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+ andi t0, CAUSEF_IP
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+ and t0, t2
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+
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+ /* check for r4k counter/timer IRQ. */
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+
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+ andi t1, t0, CAUSEF_IP7
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+ beqz t1, 1f
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+ nop
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+
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+ jal aruba_timer_interrupt
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+
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+ li a0, 7
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+
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+ j ret_from_irq
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+ nop
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+1:
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+ jal aruba_irqdispatch
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+ move a0, t0
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+ j ret_from_irq
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+ nop
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+
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+ END(idtIRQ)
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+
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+
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diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/aruba/irq.c
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--- linux-2.6.15/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.15-openwrt/arch/mips/aruba/irq.c 2006-01-10 00:32:32.000000000 +0100
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@@ -0,0 +1,393 @@
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+/**************************************************************************
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+ *
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||||
+ * BRIEF MODULE DESCRIPTION
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||||
+ * Interrupt routines for IDT EB434 boards
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+ *
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||||
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
|
||||
+ *
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||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
||||
+ * option) any later version.
|
||||
+ *
|
||||
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
+ *
|
||||
+ * You should have received a copy of the GNU General Public License along
|
||||
+ * with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
+ *
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||||
+ *
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||||
+ **************************************************************************
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||||
+ * May 2004 rkt, neb
|
||||
+ *
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||||
+ * Initial Release
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||||
+ *
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||||
+ *
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||||
+ *
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||||
+ **************************************************************************
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+ */
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+
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+#include <linux/errno.h>
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+#include <linux/init.h>
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+#include <linux/kernel_stat.h>
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+#include <linux/module.h>
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+#include <linux/signal.h>
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+#include <linux/sched.h>
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+#include <linux/types.h>
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+#include <linux/interrupt.h>
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+#include <linux/ioport.h>
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+#include <linux/timex.h>
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+#include <linux/slab.h>
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+#include <linux/random.h>
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+#include <linux/delay.h>
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+
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+#include <asm/bitops.h>
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+#include <asm/bootinfo.h>
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+#include <asm/io.h>
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+#include <asm/mipsregs.h>
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+#include <asm/system.h>
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+#include <asm/idt-boards/rc32434/rc32434.h>
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+#include <asm/idt-boards/rc32434/rc32434_gpio.h>
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+
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+#include <asm/irq.h>
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+
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+#undef DEBUG_IRQ
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+#ifdef DEBUG_IRQ
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+/* note: prints function name for you */
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+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
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+#else
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+#define DPRINTK(fmt, args...)
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+#endif
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+
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+extern asmlinkage void idtIRQ(void);
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+static unsigned int startup_irq(unsigned int irq);
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+static void end_irq(unsigned int irq_nr);
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+static void mask_and_ack_irq(unsigned int irq_nr);
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+static void aruba_enable_irq(unsigned int irq_nr);
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+static void aruba_disable_irq(unsigned int irq_nr);
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+
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+extern void __init init_generic_irq(void);
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+
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+typedef struct {
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+ u32 mask;
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+ volatile u32 *base_addr;
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+} intr_group_t;
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+
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+static const intr_group_t intr_group_merlot[NUM_INTR_GROUPS] = {
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+ {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0)},
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+};
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+
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+#define READ_PEND_MERLOT(base) (*((volatile unsigned long *)(0xbc003010)))
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+#define READ_MASK_MERLOT(base) (*((volatile unsigned long *)(0xbc003010 + 4)))
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+#define WRITE_MASK_MERLOT(base, val) ((*((volatile unsigned long *)((0xbc003010) + 4))) = (val))
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+
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+static const intr_group_t intr_group_muscat[NUM_INTR_GROUPS] = {
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+ {0x0000efff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
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+ {0x00001fff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
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+ {0x00000007, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
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+ {0x0003ffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
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+ {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
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+};
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+
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+#define READ_PEND_MUSCAT(base) (*(base))
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+#define READ_MASK_MUSCAT(base) (*(base + 2))
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+#define WRITE_MASK_MUSCAT(base, val) (*(base + 2) = (val))
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+
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+static inline int irq_to_group(unsigned int irq_nr)
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+{
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ return 0;
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+ }
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+}
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+
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+static inline int group_to_ip(unsigned int group)
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+{
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ return group + 2;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ return 6;
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+ }
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+}
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+
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+static inline void enable_local_irq(unsigned int ip)
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+{
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+ int ipnum = 0x100 << ip;
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+ clear_c0_cause(ipnum);
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+ set_c0_status(ipnum);
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+}
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+
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+static inline void disable_local_irq(unsigned int ip)
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+{
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+ int ipnum = 0x100 << ip;
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+ clear_c0_status(ipnum);
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+}
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+
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+static inline void ack_local_irq(unsigned int ip)
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+{
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+ int ipnum = 0x100 << ip;
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+ clear_c0_cause(ipnum);
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+}
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+
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+static void aruba_enable_irq(unsigned int irq_nr)
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+{
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+ int ip = irq_nr - GROUP0_IRQ_BASE;
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+ unsigned int group, intr_bit;
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+ volatile unsigned int *addr;
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+ if (ip < 0) {
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+ enable_local_irq(irq_nr);
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+ } else {
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+ // calculate group
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ group = ip >> 5;
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ group = 0;
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+ break;
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+ }
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+
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+ // calc interrupt bit within group
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+ ip -= (group << 5);
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+ intr_bit = 1 << ip;
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+
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+ // first enable the IP mapped to this IRQ
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+ enable_local_irq(group_to_ip(group));
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ addr = intr_group_muscat[group].base_addr;
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+ // unmask intr within group
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+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ addr = intr_group_merlot[group].base_addr;
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+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
|
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+ break;
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void aruba_disable_irq(unsigned int irq_nr)
|
||||
+{
|
||||
+ int ip = irq_nr - GROUP0_IRQ_BASE;
|
||||
+ unsigned int group, intr_bit, mask;
|
||||
+ volatile unsigned int *addr;
|
||||
+
|
||||
+ // calculate group
|
||||
+ switch (mips_machtype) {
|
||||
+ case MACH_ARUBA_AP70:
|
||||
+ group = ip >> 5;
|
||||
+ break;
|
||||
+ case MACH_ARUBA_AP65:
|
||||
+ case MACH_ARUBA_AP60:
|
||||
+ default:
|
||||
+ group = 0;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ // calc interrupt bit within group
|
||||
+ ip -= group << 5;
|
||||
+ intr_bit = 1 << ip;
|
||||
+
|
||||
+ switch (mips_machtype) {
|
||||
+ case MACH_ARUBA_AP70:
|
||||
+ addr = intr_group_muscat[group].base_addr;
|
||||
+ // mask intr within group
|
||||
+ mask = READ_MASK_MUSCAT(addr);
|
||||
+ mask |= intr_bit;
|
||||
+ WRITE_MASK_MUSCAT(addr, mask);
|
||||
+
|
||||
+ /*
|
||||
+ if there are no more interrupts enabled in this
|
||||
+ group, disable corresponding IP
|
||||
+ */
|
||||
+ if (mask == intr_group_muscat[group].mask)
|
||||
+ disable_local_irq(group_to_ip(group));
|
||||
+ break;
|
||||
+ case MACH_ARUBA_AP65:
|
||||
+ case MACH_ARUBA_AP60:
|
||||
+ default:
|
||||
+ addr = intr_group_merlot[group].base_addr;
|
||||
+ // mask intr within group
|
||||
+ mask = READ_MASK_MERLOT(addr);
|
||||
+ mask &= ~intr_bit;
|
||||
+ WRITE_MASK_MERLOT(addr, mask);
|
||||
+ if (!mask)
|
||||
+ disable_local_irq(group_to_ip(group));
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static unsigned int startup_irq(unsigned int irq_nr)
|
||||
+{
|
||||
+ aruba_enable_irq(irq_nr);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void shutdown_irq(unsigned int irq_nr)
|
||||
+{
|
||||
+ aruba_disable_irq(irq_nr);
|
||||
+ return;
|
||||
+}
|
||||
+
|
||||
+static void mask_and_ack_irq(unsigned int irq_nr)
|
||||
+{
|
||||
+ aruba_disable_irq(irq_nr);
|
||||
+ ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
|
||||
+}
|
||||
+
|
||||
+static void end_irq(unsigned int irq_nr)
|
||||
+{
|
||||
+
|
||||
+ int ip = irq_nr - GROUP0_IRQ_BASE;
|
||||
+ unsigned int intr_bit, group;
|
||||
+ volatile unsigned int *addr;
|
||||
+
|
||||
+ if (irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)) {
|
||||
+ printk("warning: end_irq %d did not enable (%x)\n",
|
||||
+ irq_nr, irq_desc[irq_nr].status);
|
||||
+ }
|
||||
+
|
||||
+ switch (mips_machtype) {
|
||||
+ case MACH_ARUBA_AP70:
|
||||
+ if (irq_nr == GROUP4_IRQ_BASE + 9) idt_gpio->gpioistat &= 0xfffffdff;
|
||||
+ else if (irq_nr == GROUP4_IRQ_BASE + 10) idt_gpio->gpioistat &= 0xfffffbff;
|
||||
+ else if (irq_nr == GROUP4_IRQ_BASE + 11) idt_gpio->gpioistat &= 0xfffff7ff;
|
||||
+ else if (irq_nr == GROUP4_IRQ_BASE + 12) idt_gpio->gpioistat &= 0xffffefff;
|
||||
+
|
||||
+ group = ip >> 5;
|
||||
+
|
||||
+ // calc interrupt bit within group
|
||||
+ ip -= (group << 5);
|
||||
+ intr_bit = 1 << ip;
|
||||
+
|
||||
+ // first enable the IP mapped to this IRQ
|
||||
+ enable_local_irq(group_to_ip(group));
|
||||
+
|
||||
+ addr = intr_group_muscat[group].base_addr;
|
||||
+ // unmask intr within group
|
||||
+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
|
||||
+ break;
|
||||
+ case MACH_ARUBA_AP65:
|
||||
+ case MACH_ARUBA_AP60:
|
||||
+ group = 0;
|
||||
+
|
||||
+ // calc interrupt bit within group
|
||||
+ intr_bit = 1 << ip;
|
||||
+
|
||||
+ // first enable the IP mapped to this IRQ
|
||||
+ enable_local_irq(group_to_ip(group));
|
||||
+
|
||||
+ addr = intr_group_merlot[group].base_addr;
|
||||
+ // unmask intr within group
|
||||
+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static struct hw_interrupt_type aruba_irq_type = {
|
||||
+ .typename = "IDT434",
|
||||
+ .startup = startup_irq,
|
||||
+ .shutdown = shutdown_irq,
|
||||
+ .enable = aruba_enable_irq,
|
||||
+ .disable = aruba_disable_irq,
|
||||
+ .ack = mask_and_ack_irq,
|
||||
+ .end = end_irq,
|
||||
+};
|
||||
+
|
||||
+void __init arch_init_irq(void)
|
||||
+{
|
||||
+ int i;
|
||||
+ printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
|
||||
+ memset(irq_desc, 0, sizeof(irq_desc));
|
||||
+ set_except_vector(0, idtIRQ);
|
||||
+
|
||||
+ for (i = 0; i < RC32434_NR_IRQS; i++) {
|
||||
+ irq_desc[i].status = IRQ_DISABLED;
|
||||
+ irq_desc[i].action = NULL;
|
||||
+ irq_desc[i].depth = 1;
|
||||
+ irq_desc[i].handler = &aruba_irq_type;
|
||||
+ spin_lock_init(&irq_desc[i].lock);
|
||||
+ }
|
||||
+
|
||||
+ switch (mips_machtype) {
|
||||
+ case MACH_ARUBA_AP70:
|
||||
+ break;
|
||||
+ case MACH_ARUBA_AP65:
|
||||
+ case MACH_ARUBA_AP60:
|
||||
+ default:
|
||||
+ WRITE_MASK_MERLOT(intr_group_merlot[0].base_addr, 0);
|
||||
+ *((volatile unsigned long *)0xbc003014) = 0x10;
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/* Main Interrupt dispatcher */
|
||||
+void aruba_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
|
||||
+{
|
||||
+ unsigned int pend, group, ip;
|
||||
+ volatile unsigned int *addr;
|
||||
+ switch (mips_machtype) {
|
||||
+ case MACH_ARUBA_AP70:
|
||||
+ if ((ip = (cp0_cause & 0x7c00))) {
|
||||
+ group = 21 - rc32434_clz(ip);
|
||||
+
|
||||
+ addr = intr_group_muscat[group].base_addr;
|
||||
+
|
||||
+ pend = READ_PEND_MUSCAT(addr);
|
||||
+ pend &= ~READ_MASK_MUSCAT(addr); // only unmasked interrupts
|
||||
+ pend = 39 - rc32434_clz(pend);
|
||||
+ do_IRQ((group << 5) + pend, regs);
|
||||
+ }
|
||||
+ break;
|
||||
+ case MACH_ARUBA_AP65:
|
||||
+ case MACH_ARUBA_AP60:
|
||||
+ default:
|
||||
+ if (cp0_cause & 0x4000) {
|
||||
+ // Misc Interrupt
|
||||
+ group = 0;
|
||||
+ addr = intr_group_merlot[group].base_addr;
|
||||
+ pend = READ_PEND_MERLOT(addr);
|
||||
+ pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
|
||||
+ /* handle one misc interrupt at a time */
|
||||
+ while (pend) {
|
||||
+ unsigned int intr_bit, irq_nr;
|
||||
+ intr_bit = pend ^ (pend - 1);
|
||||
+ irq_nr = ((31 - rc32434_clz(pend)) + GROUP0_IRQ_BASE);
|
||||
+ do_IRQ(irq_nr, regs);
|
||||
+ pend &= ~intr_bit;
|
||||
+ }
|
||||
+ }
|
||||
+ if (cp0_cause & 0x3c00) {
|
||||
+ while (cp0_cause) {
|
||||
+ unsigned int intr_bit, irq_nr;
|
||||
+ intr_bit = cp0_cause ^ (cp0_cause - 1);
|
||||
+ irq_nr = ((31 - rc32434_clz(cp0_cause)) - GROUP0_IRQ_BASE);
|
||||
+ do_IRQ(irq_nr, regs);
|
||||
+ cp0_cause &= ~intr_bit;
|
||||
+ }
|
||||
+ }
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
Reference in New Issue
Block a user