qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00
Code Activity

Add preliminary RouterBoard RB1xx support

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6839 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
2007-04-02 16:59:59 +00:00
parent fe41a38a95
commit 3260740c92
45 changed files with 6688 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

63
target/linux/rb1xx-2.6/files/arch/mips/pci/ops-adm5120.c Normal file
View File

@@ -0,0 +1,63 @@
/*
* Copyright (C) ADMtek Incorporated.
* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
* Copyright (C) 2007 OpenWrt.org
*/
#include <linux/autoconf.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <adm5120_defs.h>
volatile u32* pci_config_address_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR);
volatile u32* pci_config_data_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA);
#define PCI_ENABLE 0x80000000
static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
int size, uint32_t *val)
{
*pci_config_address_reg = ((bus->number & 0xff) << 0x10) |
((devfn & 0xff) << 0x08) | (where & 0xfc) | PCI_ENABLE;
switch (size) {
case 1:
*val = ((*pci_config_data_reg)>>((where&3)<<3))&0xff;
break;
case 2:
*val = ((*pci_config_data_reg)>>((where&3)<<3))&0xffff;
break;
default:
*val = (*pci_config_data_reg);
}
return PCIBIOS_SUCCESSFUL;
}
static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
int size, uint32_t val)
{
*pci_config_address_reg = ((bus->number & 0xff) << 0x10) |
((devfn & 0xff) << 0x08) | (where & 0xfc) | PCI_ENABLE;
switch (size) {
case 1:
*(volatile u8 *)(((int)pci_config_data_reg) +
(where & 3)) = val;
break;
case 2:
*(volatile u16 *)(((int)pci_config_data_reg) +
(where & 2)) = (val);
break;
default:
*pci_config_data_reg = (val);
}
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops adm5120_pci_ops = {
.read = pci_config_read,
.write = pci_config_write,
};

96
target/linux/rb1xx-2.6/files/arch/mips/pci/pci-adm5120.c Normal file
View File

@@ -0,0 +1,96 @@
/*
* Copyright (C) ADMtek Incorporated.
* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
* Copyright (C) 2007 OpenWrt.org
*/
#include <linux/autoconf.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <adm5120_info.h>
#include <adm5120_defs.h>
extern struct pci_ops adm5120_pci_ops;
#define PCI_CMM_IOACC_EN 0x1
#define PCI_CMM_MEMACC_EN 0x2
#define PCI_CMM_MASTER_EN 0x4
#define PCI_CMM_DEF \
(PCI_CMM_IOACC_EN | PCI_CMM_MEMACC_EN | PCI_CMM_MASTER_EN)
#define PCI_DEF_CACHE_LINE_SZ 4
struct resource pci_io_resource = {
.name = "ADM5120 PCI I/O",
.start = ADM5120_PCIIO_BASE,
.end = ADM5120_PCICFG_ADDR-1,
.flags = IORESOURCE_IO
};
struct resource pci_mem_resource = {
.name = "ADM5120 PCI MEM",
.start = ADM5120_PCIMEM_BASE,
.end = ADM5120_PCIIO_BASE-1,
.flags = IORESOURCE_MEM
};
static struct pci_controller adm5120_controller = {
.pci_ops = &adm5120_pci_ops,
.io_resource = &pci_io_resource,
.mem_resource = &pci_mem_resource,
};
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot < 2 || slot > 4)
return -1;
return slot + 4;
}
static void adm5120_pci_fixup(struct pci_dev *dev)
{
if (dev->devfn == 0) {
pci_write_config_word(dev, PCI_COMMAND, PCI_CMM_DEF);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
PCI_DEF_CACHE_LINE_SZ);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, adm5120_pci_fixup);
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
static int __init adm5120_pci_setup(void)
{
int pci_bios;
pci_bios = adm5120_has_pci();
printk("adm5120: system has %sPCI BIOS\n", pci_bios ? "" : "no ");
if (pci_bios == 0)
return 1;
/* Avoid ISA compat ranges. */
PCIBIOS_MIN_IO = 0x00000000;
PCIBIOS_MIN_MEM = 0x00000000;
/* Set I/O resource limits. */
ioport_resource.end = 0x1fffffff;
iomem_resource.end = 0xffffffff;
register_pci_controller(&adm5120_controller);
return 0;
}
subsys_initcall(adm5120_pci_setup);