mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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Add preliminary RouterBoard RB1xx support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6839 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
@@ -0,0 +1,60 @@
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/*
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* $Id$
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*
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* ADM5120 SoC definitions
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*
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* This file defines some constants specific to the ADM5120 SoC
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*
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* Copyright (C) 2007 OpenWrt.org
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef _ADM5120_DEFS_H
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#define _ADM5120_DEFS_H
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#define ADM5120_SDRAM0_BASE 0x00000000
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#define ADM5120_SDRAM1_BASE 0x01000000
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#define ADM5120_SRAM1_BASE 0x10000000
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#define ADM5120_MPMC_BASE 0x11000000
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#define ADM5120_USBC_BASE 0x11200000
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#define ADM5120_PCIMEM_BASE 0x11400000
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#define ADM5120_PCIIO_BASE 0x11500000
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#define ADM5120_PCICFG_ADDR 0x115FFFF0
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#define ADM5120_PCICFG_DATA 0x115FFFF8
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#define ADM5120_SWITCH_BASE 0x12000000
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#define ADM5120_INTC_BASE 0x12200000
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#define ADM5120_UART0_BASE 0x12600000
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#define ADM5120_UART1_BASE 0x12800000
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#define ADM5120_SRAM0_BASE 0x1FC00000
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#define ADM5120_MPMC_SIZE 0x1000
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#define ADM5120_USBC_SIZE 0x84
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#define ADM5120_PCIMEM_SIZE (ADM5120_PCIIO_BASE - ADM5120_PCIMEM_BASE)
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#define ADM5120_PCIIO_SIZE (ADM5120_PCICFG_ADDR - ADM5120_PCIIO_BASE)
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#define ADM5120_PCICFG_SIZE 0x10
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#define ADM5120_SWITCH_SIZE 0x114
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#define ADM5120_INTC_SIZE 0x28
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#define ADM5120_UART_SIZE 0x20
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#define ADM5120_CLK_175 175000000
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#define ADM5120_CLK_200 200000000
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#define ADM5120_CLK_225 225000000
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#define ADM5120_CLK_250 250000000
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#define ADM5120_UART_CLOCK 62500000
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#endif /* _ADM5120_DEFS_H */
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@@ -0,0 +1,70 @@
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/*
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* $Id$
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*
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* Copyright (C) 2007 OpenWrt.org
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* Copyright (C) Gabor Juhos <juhosg@freemail.hu>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ADM5120_INFO_H
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#define _ADM5120_INFO_H
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#include <linux/types.h>
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struct adm5120_info {
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unsigned int product_code;
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unsigned int revision;
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unsigned int cpu_package;
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unsigned int nand_boot;
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unsigned long cpu_speed;
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unsigned int boot_loader;
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unsigned int board_type;
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unsigned int num_iface;
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};
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#define CPU_SPEED_175 175000000
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#define CPU_SPEED_200 200000000
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#define CPU_SPEED_225 225000000
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#define CPU_SPEED_250 250000000
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#define CPU_PACKAGE_PQFP 0
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#define CPU_PACKAGE_BGA 1
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#define BOOT_LOADER_UNKNOWN 0
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#define BOOT_LOADER_CFE 1
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#define BOOT_LOADER_UBOOT 2
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#define BOOT_LOADER_MYLOADER 3
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#define BOOT_LOADER_ROUTERBOOT 4
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#define BOOT_LOADER_LAST 4
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#define BOARD_TYPE_UNKNOWN 0
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#define BOARD_TYPE_WP54G_WRT 1
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#define BOARD_TYPE_WP54G 2
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#define BOARD_TYPE_WP54AG 3
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#define BOARD_TYPE_WPP54G 4
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#define BOARD_TYPE_WPP54AG 5
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#define BOARD_TYPE_NP28G 6
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#define BOARD_TYPE_NP28GHS 7
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#define BOARD_TYPE_NP27G 8
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#define BOARD_TYPE_WP54Gv1C 9
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#define BOARD_TYPE_RB_111 10
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#define BOARD_TYPE_RB_112 11
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#define BOARD_TYPE_RB_133 12
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#define BOARD_TYPE_RB_133C 13
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#define BOARD_TYPE_RB_150 14
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#define BOARD_TYPE_RB_153 15
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#define BOART_TYPE_LAST 15
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extern struct adm5120_info adm5120_info;
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extern void adm5120_info_init(void);
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static inline int adm5120_has_pci(void)
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{
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return (adm5120_info.cpu_package == CPU_PACKAGE_BGA);
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}
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#endif /* _ADM5120_INFO_H */
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@@ -0,0 +1,89 @@
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/*
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* ADM5120 ethernet switch definitions
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*
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* This header file defines the hardware registers of the ADM5120 SoC
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* built-in Ethernet switch.
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*
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* Copyright (C) 2007 OpenWrt.org
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef _ADM5120_SWITCH_H
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#define _ADM5120_SWITCH_H
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#define BITMASK(len) ((1 << (len))-1)
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#define ONEBIT(at) (1 << (at))
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/* Switch register offsets */
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#define SWITCH_REG_CODE 0x0000
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#define SWITCH_REG_SOFT_RESET 0x0004
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#define SWITCH_REG_MEMCTRL 0x001C
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#define SWITCH_REG_CPUP_CONF 0x0024
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#define SWITCH_REG_PORT_CONF0 0x0028
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#define SWITCH_REG_PORT_CONF1 0x002C
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#define SWITCH_REG_PORT_CONF2 0x0030
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#define SWITCH_REG_VLAN_G1 0x0040
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#define SWITCH_REG_VLAN_G2 0x0044
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#define SWITCH_REG_SEND_TRIG 0x0048
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#define SWITCH_REG_MAC_WT0 0x0058
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#define SWITCH_REG_MAC_WT1 0x005C
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#define SWITCH_REG_PHY_CNTL0 0x0068
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#define SWITCH_REG_PHY_CNTL1 0x006C
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#define SWITCH_REG_PHY_CNTL2 0x007C
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#define SWITCH_REG_PHY_CNTL3 0x0080
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#define SWITCH_REG_PRI_CNTL 0x0084
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#define SWITCH_REG_INT_STATUS 0x00B0
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#define SWITCH_REG_INT_MASK 0x00B4
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#define SWITCH_REG_GPIO_CONF0 0x00B8
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#define SWITCH_REG_GPIO_CONF2 0x00BC
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#define SWITCH_REG_WDOG0 0x00C0
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#define SWITCH_REG_WDOG1 0x00C4
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#define SWITCH_REG_PHY_CNTL4 0x00A0
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#define SWITCH_REG_SEND_HBADDR 0x00D0
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#define SWITCH_REG_SEND_LBADDR 0x00D4
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#define SWITCH_REG_RECV_HBADDR 0x00D8
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#define SWITCH_REG_RECV_LBADDR 0x00DC
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#define SWITCH_REG_TIMER_INT 0x00F0
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#define SWITCH_REG_TIMER 0x00F4
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#define SWITCH_REG_PORT0_LED 0x0100
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#define SWITCH_REG_PORT1_LED 0x0104
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#define SWITCH_REG_PORT2_LED 0x0108
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#define SWITCH_REG_PORT3_LED 0x010C
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#define SWITCH_REG_PORT4_LED 0x0110
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/* CODE register bits */
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#define CODE_PC_MASK BITMASK(16) /* Product Code */
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#define CODE_REV_SHIFT 16
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#define CODE_REV_MASK BITMASK(4) /* Product Revision */
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#define CODE_CLKS_SHIFT 20
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#define CODE_CLKS_MASK BITMASK(2) /* Clock Speed */
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#define CODE_CLKS_175 0 /* 175 MHz */
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#define CODE_CLKS_200 1 /* 200 MHz */
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#define CODE_CLKS_225 2 /* 225 MHz */
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#define CODE_CLKS_250 3 /* 250 MHz */
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#define CODE_NAB ONEBIT(24) /* NAND boot */
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#define CODE_PK_MASK BITMASK(1) /* Package type */
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#define CODE_PK_SHIFT 29
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#define CODE_PK_BGA 0 /* BGA package */
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#define CODE_PK_PQFP 1 /* PQFP package */
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#endif /* _ADM5120_SWITCH_H */
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@@ -0,0 +1,167 @@
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/*
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* Copyright (C) 2006,2007 Gabor Juhos
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef _MYLOADER_H_
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#define _MYLOADER_H_
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/*
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* Firmware file format:
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*
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* <header>
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* [<block descriptor 0>]
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* ...
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* [<block descriptor n>]
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* <null block descriptor>
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* [<block data 0>]
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* ...
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* [<block data n>]
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*
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*
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*/
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/* Myloader specific magic numbers */
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#define MYLO_MAGIC_FIRMWARE 0x4C594D00
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#define MYLO_MAGIC_20021103 0x20021103
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#define MYLO_MAGIC_20021107 0x20021107
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#define MYLO_MAGIC_SYS_PARAMS MYLO_MAGIC_20021107
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#define MYLO_MAGIC_PARTITIONS MYLO_MAGIC_20021103
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#define MYLO_MAGIC_BOARD_PARAMS MYLO_MAGIC_20021103
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/*
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* Addresses of the data structures provided by MyLoader
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*/
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#define MYLO_MIPS_SYS_PARAMS 0x80000800 /* System Parameters */
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#define MYLO_MIPS_BOARD_PARAMS 0x80000A00 /* Board Parameters */
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#define MYLO_MIPS_PARTITIONS 0x80000C00 /* Partition Table */
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#define MYLO_MIPS_BOOT_PARAMS 0x80000E00 /* Boot Parameters */
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/* Vendor ID's (seems to be same as the PCI vendor ID's) */
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#define VENID_COMPEX 0x11F6
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/* Devices based on the ADM5120 */
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#define DEVID_COMPEX_NP27G 0x0078
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#define DEVID_COMPEX_NP28G 0x044C
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#define DEVID_COMPEX_NP28GHS 0x044E
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#define DEVID_COMPEX_WP54Gv1C 0x0514
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#define DEVID_COMPEX_WP54G 0x0515
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#define DEVID_COMPEX_WP54AG 0x0546
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#define DEVID_COMPEX_WPP54AG 0x0550
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#define DEVID_COMPEX_WPP54G 0x0555
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/* Devices based on the IXP422 */
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#define DEVID_COMPEX_WP18 0x047E
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#define DEVID_COMPEX_NP18A 0x0489
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/* Other devices */
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#define DEVID_COMPEX_NP26G8M 0x03E8
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#define DEVID_COMPEX_NP26G16M 0x03E9
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struct mylo_fw_header {
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uint32_t magic; /* must be MYLO_MAGIC_FIRMWARE */
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uint32_t crc; /* CRC of the whole firmware */
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uint32_t res0; /* unknown/unused */
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uint32_t res1; /* unknown/unused */
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uint16_t vid; /* vendor ID */
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uint16_t did; /* device ID */
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uint16_t svid; /* sub vendor ID */
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uint16_t sdid; /* sub device ID */
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uint32_t rev; /* device revision */
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uint32_t fwhi; /* FIXME: firmware version high? */
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uint32_t fwlo; /* FIXME: firmware version low? */
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uint32_t flags; /* firmware flags */
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};
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#define FW_FLAG_BOARD_PARAMS_WP 0x01 /* board parameters are write protected */
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#define FW_FLAG_BOOT_SECTOR_WE 0x02 /* enable of write boot sectors (below 64K) */
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struct mylo_fw_blockdesc {
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uint32_t type; /* block type */
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uint32_t addr; /* relative address to flash start */
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uint32_t dlen; /* size of block data in bytes */
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uint32_t blen; /* total size of block in bytes */
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};
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#define FW_DESC_TYPE_UNUSED 0
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#define FW_DESC_TYPE_USED 1
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struct mylo_partition {
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uint16_t flags; /* partition flags */
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uint16_t type; /* type of the partition */
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uint32_t addr; /* relative address of the partition from the
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flash start */
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uint32_t size; /* size of the partition in bytes */
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uint32_t param; /* if this is the active partition, the
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MyLoader load code to this address */
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};
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#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition,
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* MyLoader loads firmware from here */
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#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */
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#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */
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#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM
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* before decompression */
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#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */
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#define PARTITION_TYPE_FREE 0
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#define PARTITION_TYPE_USED 1
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#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the
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partition table */
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struct mylo_partition_table {
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uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */
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uint32_t res0; /* unknown/unused */
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uint32_t res1; /* unknown/unused */
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uint32_t res2; /* unknown/unused */
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struct mylo_partition partitions[MYLO_MAX_PARTITIONS];
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};
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struct mylo_partition_header {
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uint32_t len; /* length of the partition data */
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uint32_t crc; /* CRC value of the partition data */
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};
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struct mylo_system_params {
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uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */
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uint32_t res0;
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uint32_t res1;
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uint32_t mylo_ver;
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uint16_t vid; /* Vendor ID */
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uint16_t did; /* Device ID */
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uint16_t svid; /* Sub Vendor ID */
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uint16_t sdid; /* Sub Device ID */
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uint32_t rev; /* device revision */
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uint32_t fwhi;
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uint32_t fwlo;
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uint32_t tftp_addr;
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uint32_t prog_start;
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uint32_t flash_size; /* Size of boot FLASH in bytes */
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uint32_t dram_size; /* Size of onboard RAM in bytes */
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};
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struct mylo_eth_addr {
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uint8_t mac[6];
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uint8_t csum[2];
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};
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#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address
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in the board parameters */
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struct mylo_board_params {
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uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */
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uint32_t res0;
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uint32_t res1;
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uint32_t res2;
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struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT];
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};
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#endif /* _MYLOADER_H_*/
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