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ar71xx: add preliminary support for 3.3
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30410 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
220
target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch
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220
target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch
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@@ -0,0 +1,220 @@
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--- a/arch/mips/ath79/mach-db120.c
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+++ b/arch/mips/ath79/mach-db120.c
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@@ -37,17 +37,26 @@
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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#include <linux/pci.h>
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+#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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-#include "machtypes.h"
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+
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+#include "common.h"
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+#include "dev-ap9x-pci.h"
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+#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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+#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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-#include "pci.h"
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+#include "machtypes.h"
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+#define DB120_GPIO_LED_USB 11
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#define DB120_GPIO_LED_WLAN_5G 12
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#define DB120_GPIO_LED_WLAN_2G 13
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#define DB120_GPIO_LED_STATUS 14
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@@ -58,8 +67,50 @@
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#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
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#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
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-#define DB120_WMAC_CALDATA_OFFSET 0x1000
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-#define DB120_PCIE_CALDATA_OFFSET 0x5000
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+#define DB120_MAC0_OFFSET 0
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+#define DB120_MAC1_OFFSET 6
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+#define DB120_WMAC_CALDATA_OFFSET 0x1000
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+#define DB120_PCIE_CALDATA_OFFSET 0x5000
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+
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+static struct mtd_partition db120_partitions[] = {
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+ {
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+ .name = "u-boot",
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+ .offset = 0,
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+ .size = 0x040000,
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+ .mask_flags = MTD_WRITEABLE,
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+ },
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+ {
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+ .name = "u-boot-env",
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+ .offset = 0x040000,
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+ .size = 0x010000,
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+ },
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+ {
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+ .name = "rootfs",
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+ .offset = 0x050000,
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+ .size = 0x630000,
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+ },
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+ {
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+ .name = "uImage",
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+ .offset = 0x680000,
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+ .size = 0x160000,
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+ },
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+ {
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+ .name = "NVRAM",
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+ .offset = 0x7E0000,
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+ .size = 0x010000,
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+ },
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+ {
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+ .name = "ART",
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+ .offset = 0x7F0000,
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+ .size = 0x010000,
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+ .mask_flags = MTD_WRITEABLE,
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+ }
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+};
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+
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+static struct flash_platform_data db120_flash_data = {
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+ .parts = db120_partitions,
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+ .nr_parts = ARRAY_SIZE(db120_partitions),
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+};
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static struct gpio_led db120_leds_gpio[] __initdata = {
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{
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@@ -82,6 +133,11 @@ static struct gpio_led db120_leds_gpio[]
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.gpio = DB120_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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+ {
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+ .name = "db120:green:usb",
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+ .gpio = DB120_GPIO_LED_USB,
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+ .active_low = 1,
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+ }
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};
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static struct gpio_keys_button db120_gpio_keys[] __initdata = {
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@@ -95,66 +151,65 @@ static struct gpio_keys_button db120_gpi
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},
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};
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-static struct ath79_spi_controller_data db120_spi0_data = {
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- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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- .cs_line = 0,
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-};
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-
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-static struct spi_board_info db120_spi_info[] = {
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- {
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- .bus_num = 0,
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- .chip_select = 0,
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- .max_speed_hz = 25000000,
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- .modalias = "s25sl064a",
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- .controller_data = &db120_spi0_data,
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- }
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-};
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-
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-static struct ath79_spi_platform_data db120_spi_data = {
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- .bus_num = 0,
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- .num_chipselect = 1,
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-};
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-
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-#ifdef CONFIG_PCI
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-static struct ath9k_platform_data db120_ath9k_data;
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-
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-static int db120_pci_plat_dev_init(struct pci_dev *dev)
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+static void __init db120_gmac_setup(void)
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{
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- switch (PCI_SLOT(dev->devfn)) {
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- case 0:
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- dev->dev.platform_data = &db120_ath9k_data;
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- break;
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- }
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+ void __iomem *base;
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+ u32 t;
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- return 0;
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-}
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+ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
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-static void __init db120_pci_init(u8 *eeprom)
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-{
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- memcpy(db120_ath9k_data.eeprom_data, eeprom,
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- sizeof(db120_ath9k_data.eeprom_data));
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+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
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+ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
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+ AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
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+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
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- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
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- ath79_register_pci();
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+ iounmap(base);
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}
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-#else
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-static inline void db120_pci_init(void) {}
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-#endif /* CONFIG_PCI */
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static void __init db120_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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+ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
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+ ath79_register_m25p80(&db120_flash_data);
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+
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ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
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db120_leds_gpio);
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ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(db120_gpio_keys),
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db120_gpio_keys);
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- ath79_register_spi(&db120_spi_data, db120_spi_info,
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- ARRAY_SIZE(db120_spi_info));
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ath79_register_usb();
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ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
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- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
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+ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
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+
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+ db120_gmac_setup();
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+
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+ ath79_register_mdio(0, 0x0);
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+ ath79_register_mdio(1, 0x0);
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+
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+ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
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+#if 0
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+ /* GMAC0 is connected to an AR8327 switch */
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.speed = SPEED_1000;
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+ ath79_eth0_data.duplex = DUPLEX_FULL;
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+#else
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+ /* GMAC0 is connected to PHY4 of the internal switch */
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+ ath79_switch_data.phy4_mii_en = 1;
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+
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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+ ath79_eth0_data.phy_mask = BIT(4);
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+ ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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+#endif
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+ ath79_register_eth(0);
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+
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+ /* GMAC1 is connected to the internal switch */
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+ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
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+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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+ ath79_eth1_data.speed = SPEED_1000;
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+ ath79_eth1_data.duplex = DUPLEX_FULL;
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+
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+ ath79_register_eth(1);
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}
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MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -31,9 +31,11 @@ config ATH79_MACH_AP81
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config ATH79_MACH_DB120
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bool "Atheros DB120 reference board"
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select SOC_AR934X
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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- select ATH79_DEV_SPI
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+ select ATH79_DEV_M25P80
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select ATH79_DEV_USB
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select ATH79_DEV_WMAC
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help
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