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mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00

[ar71xx] preliminary 2.6.28 support

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13559 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2008-12-09 08:11:49 +00:00
parent 303c9d4114
commit 33ffee7816
29 changed files with 1595 additions and 0 deletions

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@@ -0,0 +1,50 @@
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -586,6 +586,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/
core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
+#
+# Atheros AR71xx
+#
+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/
+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx
+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000
+
# temporary until string.h is fixed
cflags-y += -ffreestanding
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -22,6 +22,23 @@ choice
config MACH_ALCHEMY
bool "Alchemy processor based machines"
+config ATHEROS_AR71XX
+ bool "Atheros AR71xx based boards"
+ select CEVT_R4K
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+ select IRQ_CPU
+ select ARCH_REQUIRE_GPIOLIB
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_HAS_EARLY_PRINTK
+ select MIPS_MACHINE
+ help
+ Support for Atheros AR71xx based boards.
+
config BASLER_EXCITE
bool "Basler eXcite smart camera"
select CEVT_R4K
@@ -598,6 +615,7 @@ config WR_PPMC
endchoice
source "arch/mips/alchemy/Kconfig"
+source "arch/mips/ar71xx/Kconfig"
source "arch/mips/basler/excite/Kconfig"
source "arch/mips/emma/Kconfig"
source "arch/mips/jazz/Kconfig"

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@@ -0,0 +1,10 @@
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o
obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o
#
# These are still pretty much in the old state, watch, go blind.

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@@ -0,0 +1,56 @@
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -81,6 +81,12 @@ config USB_EHCI_BIG_ENDIAN_DESC
depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
default y
+config USB_EHCI_AR71XX
+ bool "USB EHCI support for AR71xx"
+ depends on USB_EHCI_HCD && ATHEROS_AR71XX
+ help
+ Support for Atheros AR71xx built-in EHCI controller
+
config USB_EHCI_FSL
bool "Support for Freescale on-chip EHCI USB controller"
depends on USB_EHCI_HCD && FSL_SOC
@@ -140,6 +146,12 @@ config USB_OHCI_HCD
To compile this driver as a module, choose M here: the
module will be called ohci-hcd.
+config USB_OHCI_AR71XX
+ bool "USB OHCI support for Atheros AR71xx"
+ depends on USB_OHCI_HCD && ATHEROS_AR71XX
+ help
+ Support for Atheros AR71xx built-in OHCI controller
+
config USB_OHCI_HCD_PPC_SOC
bool "OHCI support for on-chip PPC USB controller"
depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx)
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1034,6 +1034,11 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ixp4xx_ehci_driver
#endif
+#ifdef CONFIG_USB_EHCI_AR71XX
+#include "ehci-ar71xx.c"
+#define PLATFORM_DRIVER ehci_ar71xx_driver
+#endif
+
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
#error "missing bus glue for ehci-hcd"
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1080,6 +1080,11 @@ MODULE_LICENSE ("GPL");
#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
#endif
+#ifdef CONFIG_USB_OHCI_AR71XX
+#include "ohci-ar71xx.c"
+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver
+#endif
+
#if !defined(PCI_DRIVER) && \
!defined(PLATFORM_DRIVER) && \
!defined(OF_PLATFORM_DRIVER) && \

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@@ -0,0 +1,26 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -53,6 +53,13 @@ if SPI_MASTER
comment "SPI Master Controller Drivers"
+config SPI_AR71XX
+ tristate "Atheros AR71xx SPI Controller"
+ depends on SPI_MASTER && ATHEROS_AR71XX
+ select SPI_BITBANG
+ help
+ This is the SPI contoller driver for Atheros AR71xx.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on (ARCH_AT91 || AVR32)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ endif
obj-$(CONFIG_SPI_MASTER) += spi.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o
obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o

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@@ -0,0 +1,21 @@
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2039,6 +2039,8 @@ config ACENIC_OMIT_TIGON_I
The safe and default value for this is N.
+source drivers/net/ag71xx/Kconfig
+
config DL2K
tristate "DL2000/TC902x-based Gigabit Ethernet support"
depends on PCI
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Linux network (ethercard) device drivers.
#
+obj-$(CONFIG_AG71XX) += ag71xx/
obj-$(CONFIG_E1000) += e1000/
obj-$(CONFIG_E1000E) += e1000e/
obj-$(CONFIG_IBM_NEW_EMAC) += ibm_newemac/

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@@ -0,0 +1,26 @@
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -747,6 +747,13 @@ config TXX9_WDT
help
Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
+config AR71XX_WDT
+ tristate "Atheros AR71xx Watchdog Timer"
+ depends on ATHEROS_AR71XX
+ help
+ Hardware driver for the built-in watchdog timer on the Atheros
+ AR71xx SoCs.
+
# PARISC Architecture
# POWERPC Architecture
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o
# PARISC Architecture

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@@ -0,0 +1,13 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -500,6 +500,10 @@ static struct flash_info __devinitdata m
{ "at26df161a", 0x1f4601, 0, 64 * 1024, 32, SECT_4K, },
{ "at26df321", 0x1f4701, 0, 64 * 1024, 64, SECT_4K, },
+ /* PMC -- pm25x "blocks" are 32K, sectors are 4K */
+ { "pm25lv512", 0, 32 * 1024, 2, SECT_4K },
+ { "pm25lv010", 0, 32 * 1024, 4, SECT_4K },
+
/* Spansion -- single (large) sector size only, at least
* for the chips listed here (without boot sectors).
*/

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@@ -0,0 +1,24 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -83,6 +83,11 @@ config MVSWITCH_PHY
---help---
Currently supports the Marvell 88E6060 switch.
+config MICREL_PHY
+ tristate "Drivers for Micrel/Kendin PHYs"
+ ---help---
+ Currently has a driver for the KSZ8041
+
config FIXED_PHY
bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
depends on PHYLIB=y
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_ADM6996_PHY) += adm6996.o
obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
+obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_OF_GPIO) += mdio-ofgpio.o

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@@ -0,0 +1,22 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -707,12 +707,17 @@ static int __devinit m25p_probe(struct s
struct mtd_partition *parts = NULL;
int nr_parts = 0;
+ static const char *part_probes[] = {
#ifdef CONFIG_MTD_CMDLINE_PARTS
- static const char *part_probes[] = { "cmdlinepart", NULL, };
+ "cmdlinepart",
+#endif
+#ifdef CONFIG_MTD_MYLOADER_PARTS
+ "MyLoader",
+#endif
+ NULL, };
nr_parts = parse_mtd_partitions(&flash->mtd,
part_probes, &parts, 0);
-#endif
if (nr_parts <= 0 && data && data->parts) {
parts = data->parts;

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@@ -0,0 +1,12 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -500,6 +500,9 @@ static struct flash_info __devinitdata m
{ "at26df161a", 0x1f4601, 0, 64 * 1024, 32, SECT_4K, },
{ "at26df321", 0x1f4701, 0, 64 * 1024, 64, SECT_4K, },
+ /* EON -- en25px */
+ { "en25p32", 0x1c2016, 64 * 1024, 64, },
+
/* PMC -- pm25x "blocks" are 32K, sectors are 4K */
{ "pm25lv512", 0, 32 * 1024, 2, SECT_4K },
{ "pm25lv010", 0, 32 * 1024, 4, SECT_4K },

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@@ -0,0 +1,12 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -717,6 +717,9 @@ static int __devinit m25p_probe(struct s
#ifdef CONFIG_MTD_MYLOADER_PARTS
"MyLoader",
#endif
+#ifdef CONFIG_MTD_REDBOOT_PARTS
+ "RedBoot",
+#endif
NULL, };
nr_parts = parse_mtd_partitions(&flash->mtd,

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@@ -0,0 +1,54 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -60,31 +60,32 @@ static int parse_redboot_partitions(stru
static char nullstring[] = "unallocated";
#endif
+ buf = vmalloc(master->erasesize);
+ if (!buf)
+ return -ENOMEM;
+
+ restart:
if ( directory < 0 ) {
offset = master->size + directory * master->erasesize;
- while (master->block_isbad &&
+ while (master->block_isbad &&
master->block_isbad(master, offset)) {
if (!offset) {
nogood:
printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
+ vfree(buf);
return -EIO;
}
offset -= master->erasesize;
}
} else {
offset = directory * master->erasesize;
- while (master->block_isbad &&
+ while (master->block_isbad &&
master->block_isbad(master, offset)) {
offset += master->erasesize;
if (offset == master->size)
goto nogood;
}
}
- buf = vmalloc(master->erasesize);
-
- if (!buf)
- return -ENOMEM;
-
printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
master->name, offset);
@@ -156,6 +157,11 @@ static int parse_redboot_partitions(stru
}
if (i == numslots) {
/* Didn't find it */
+ if (offset + master->erasesize < master->size) {
+ /* not at the end of the flash yet, maybe next block :) */
+ directory++;
+ goto restart;
+ }
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
master->name);
ret = 0;

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@@ -0,0 +1,21 @@
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -420,4 +420,8 @@ config MTD_NAND_SH_FLCTL
Several Renesas SuperH CPU has FLCTL. This option enables support
for NAND Flash using FLCTL. This driver support SH7723.
+config MTD_NAND_RB4XX
+ tristate "NAND flash driver for RouterBoard 4xx series"
+ depends on MTD_NAND && ATHEROS_AR71XX
+
endif # MTD_NAND
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) +=
obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o

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@@ -0,0 +1,22 @@
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -160,6 +160,7 @@ endif
#
libs-$(CONFIG_ARC) += arch/mips/fw/arc/
libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
libs-y += arch/mips/fw/lib/
libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -778,6 +778,9 @@ config MIPS_NILE4
config MIPS_DISABLE_OBSOLETE_IDE
bool
+config MYLOADER
+ bool
+
config SYNC_R4K
bool

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@@ -0,0 +1,16 @@
--- a/drivers/net/ag71xx/ag71xx_phy.c
+++ b/drivers/net/ag71xx/ag71xx_phy.c
@@ -138,12 +138,8 @@ static void ag71xx_phy_link_adjust(struc
}
}
- if (phydev->link != ag->link) {
- if (phydev->link)
- netif_schedule(dev);
-
+ if (phydev->link != ag->link)
status_change = 1;
- }
ag->link = phydev->link;
ag->duplex = phydev->duplex;

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@@ -0,0 +1,11 @@
--- a/drivers/net/ag71xx/ag71xx_mdio.c
+++ b/drivers/net/ag71xx/ag71xx_mdio.c
@@ -160,7 +160,7 @@ static int __init ag71xx_mdio_probe(stru
am->mii_bus.reset = ag71xx_mdio_reset;
am->mii_bus.irq = am->mii_irq;
am->mii_bus.priv = am;
- am->mii_bus.dev = &pdev->dev;
+ am->mii_bus.parent = &pdev->dev;
snprintf(am->mii_bus.id, MII_BUS_ID_SIZE, "%x", 0);
pdata = pdev->dev.platform_data;

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@@ -0,0 +1,90 @@
--- a/drivers/net/ag71xx/ag71xx_mdio.c
+++ b/drivers/net/ag71xx/ag71xx_mdio.c
@@ -57,7 +57,7 @@ static int ag71xx_mdio_mii_read(struct a
while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
if (i-- == 0) {
printk(KERN_ERR "%s: mii_read timed out\n",
- am->mii_bus.name);
+ am->mii_bus->name);
ret = 0xffff;
goto out;
}
@@ -88,7 +88,7 @@ static void ag71xx_mdio_mii_write(struct
while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
if (i-- == 0) {
printk(KERN_ERR "%s: mii_write timed out\n",
- am->mii_bus.name);
+ am->mii_bus->name);
break;
}
udelay(AG71XX_MDIO_DELAY);
@@ -154,23 +154,27 @@ static int __init ag71xx_mdio_probe(stru
goto err_free_mdio;
}
- am->mii_bus.name = "ag71xx_mdio";
- am->mii_bus.read = ag71xx_mdio_read;
- am->mii_bus.write = ag71xx_mdio_write;
- am->mii_bus.reset = ag71xx_mdio_reset;
- am->mii_bus.irq = am->mii_irq;
- am->mii_bus.priv = am;
- am->mii_bus.parent = &pdev->dev;
- snprintf(am->mii_bus.id, MII_BUS_ID_SIZE, "%x", 0);
+ am->mii_bus = mdiobus_alloc();
+ if (am->mii_bus == NULL)
+ goto err_iounmap;
+
+ am->mii_bus->name = "ag71xx_mdio";
+ am->mii_bus->read = ag71xx_mdio_read;
+ am->mii_bus->write = ag71xx_mdio_write;
+ am->mii_bus->reset = ag71xx_mdio_reset;
+ am->mii_bus->irq = am->mii_irq;
+ am->mii_bus->priv = am;
+ am->mii_bus->parent = &pdev->dev;
+ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
pdata = pdev->dev.platform_data;
if (pdata)
- am->mii_bus.phy_mask = pdata->phy_mask;
+ am->mii_bus->phy_mask = pdata->phy_mask;
for (i = 0; i < PHY_MAX_ADDR; i++)
am->mii_irq[i] = PHY_POLL;
- err = mdiobus_register(&am->mii_bus);
+ err = mdiobus_register(am->mii_bus);
if (err)
goto err_iounmap;
@@ -194,7 +198,8 @@ static int __exit ag71xx_mdio_remove(str
if (am) {
ag71xx_mdio_bus = NULL;
- mdiobus_unregister(&am->mii_bus);
+ mdiobus_unregister(am->mii_bus);
+ mdiobus_free(am->mii_bus);
iounmap(am->mdio_base);
kfree(am);
platform_set_drvdata(pdev, NULL);
--- a/drivers/net/ag71xx/ag71xx.h
+++ b/drivers/net/ag71xx/ag71xx.h
@@ -101,7 +101,7 @@ struct ag71xx_ring {
};
struct ag71xx_mdio {
- struct mii_bus mii_bus;
+ struct mii_bus *mii_bus;
int mii_irq[PHY_MAX_ADDR];
void __iomem *mdio_base;
};
--- a/drivers/net/ag71xx/ag71xx_main.c
+++ b/drivers/net/ag71xx/ag71xx_main.c
@@ -807,7 +807,7 @@ static int __init ag71xx_probe(struct pl
ag = netdev_priv(dev);
ag->pdev = pdev;
ag->dev = dev;
- ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
+ ag->mii_bus = ag71xx_mdio_bus->mii_bus;
ag->msg_enable = netif_msg_init(ag71xx_debug,
AG71XX_DEFAULT_MSG_ENABLE);
spin_lock_init(&ag->lock);

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@@ -0,0 +1,29 @@
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -47,6 +47,7 @@
#include <asm/mmu_context.h>
#include <asm/types.h>
#include <asm/stacktrace.h>
+#include <asm/time.h>
extern void check_wait(void);
extern asmlinkage void r4k_wait(void);
@@ -1514,6 +1515,8 @@ void __cpuinit per_cpu_trap_init(void)
*/
if (cpu_has_mips_r2) {
cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
+ if (get_c0_compare_irq)
+ cp0_compare_irq = get_c0_compare_irq();
cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -53,6 +53,7 @@ extern int (*perf_irq)(void);
#ifdef CONFIG_CEVT_R4K
extern int mips_clockevent_init(void);
extern unsigned int __weak get_c0_compare_int(void);
+extern unsigned int __weak get_c0_compare_irq(void);
#else
static inline int mips_clockevent_init(void)
{

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@@ -0,0 +1,56 @@
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -15,6 +15,22 @@
#include <asm/cevt-r4k.h>
/*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register. 4 time the
+ * pipeline depth seems reasonably conservative, and empirically
+ * works better in configurations with high CPU/bus clock ratios.
+ */
+
+#define compare_change_hazard() \
+ do { \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ } while (0)
+
+/*
* The SMTC Kernel for the 34K, 1004K, et. al. replaces several
* of these routines with SMTC-specific variants.
*/
@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
+ compare_change_hazard();
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
return res;
}
@@ -99,22 +116,6 @@ static int c0_compare_int_pending(void)
return (read_c0_cause() >> cp0_compare_irq) & 0x100;
}
-/*
- * Compare interrupt can be routed and latched outside the core,
- * so a single execution hazard barrier may not be enough to give
- * it time to clear as seen in the Cause register. 4 time the
- * pipeline depth seems reasonably conservative, and empirically
- * works better in configurations with high CPU/bus clock ratios.
- */
-
-#define compare_change_hazard() \
- do { \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- } while (0)
-
int c0_compare_int_usable(void)
{
unsigned int delta;