bcm63xx: add preliminary support for bcm6328

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31878 3c298f89-4303-0410-b956-a3cf2f4a3e73
2025-04-21 12:27:27 +03:00 · 2012-05-27 13:22:29 +00:00
parent c9204063aa
commit 35f8e31243
21 changed files with 1364 additions and 18 deletions
--- a/target/linux/brcm63xx/patches-3.3/311-MIPS-BCM63XX-add-MISC-register-set-definition.patch
+++ b/target/linux/brcm63xx/patches-3.3/311-MIPS-BCM63XX-add-MISC-register-set-definition.patch
@@ -0,0 +1,107 @@
+From 48d3ed67982d2d1cecb5b33bf396d21f6fd7b088 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 14 Jun 2011 21:14:39 +0200
+Subject: [PATCH 39/79] MIPS: BCM63XX: add MISC register set definition
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |   10 +++++++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |    2 ++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   10 ++++++++++
+ 3 files changed, 21 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -129,7 +129,8 @@ enum bcm63xx_regs_set {
+ 	RSET_PCMDMA,
+ 	RSET_PCMDMAC,
+ 	RSET_PCMDMAS,
+-	RSET_TRNG
+	RSET_TRNG,
+	RSET_MISC
+ };
+ 
+ #define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
+@@ -198,6 +199,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6338_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6338_PCMDMAS_BASE		(0xdeadbeef)
+ #define BCM_6338_TRNG_BASE		(0xdeadbeef)
+#define BCM_6338_MISC_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6345 register sets base address
+@@ -242,6 +244,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6345_PCMDMAS_BASE		(0xdeadbeef)
+ #define BCM_6345_TRNG_BASE		(0xdeadbeef)
+#define BCM_6345_MISC_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6348 register sets base address
+@@ -283,6 +286,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6348_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6348_PCMDMAS_BASE		(0xdeadbeef)
+ #define BCM_6348_TRNG_BASE		(0xdeadbeef)
+#define BCM_6348_MISC_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6358 register sets base address
+@@ -324,6 +328,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_PCMDMAC_BASE		(0xfffe1900)
+ #define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
+ #define BCM_6358_TRNG_BASE		(0xdeadbeef)
+#define BCM_6358_MISC_BASE		(0xdeadbeef)
+ 
+ 
+ /*
+@@ -366,6 +371,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_PCMDMAC_BASE		(0xb0005a00)
+ #define BCM_6368_PCMDMAS_BASE		(0xb0005c00)
+ #define BCM_6368_TRNG_BASE		(0xb0004180)
+#define BCM_6368_MISC_BASE		(0xdeadbeef)
+ 
+ 
+ extern const unsigned long *bcm63xx_regs_base;
+@@ -412,6 +418,7 @@ extern const unsigned long *bcm63xx_regs
+ 	__GEN_RSET_BASE(__cpu, PCMDMAC)					\
+ 	__GEN_RSET_BASE(__cpu, PCMDMAS)					\
+ 	__GEN_RSET_BASE(__cpu, TRNG)					\
+	__GEN_RSET_BASE(__cpu, MISC)					\
+ 	}
+ 
+ #define __GEN_CPU_REGS_TABLE(__cpu)					\
+@@ -451,6 +458,7 @@ extern const unsigned long *bcm63xx_regs
+ 	[RSET_PCMDMAC]		= BCM_## __cpu ##_PCMDMAC_BASE,		\
+ 	[RSET_PCMDMAS]		= BCM_## __cpu ##_PCMDMAS_BASE,		\
+ 	[RSET_TRNG]		= BCM_## __cpu ##_TRNG_BASE,		\
+	[RSET_MISC]		= BCM_## __cpu ##_MISC_BASE,		\
+ 
+ 
+ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -91,5 +91,7 @@
+ #define bcm_memc_writel(v, o)	bcm_rset_writel(RSET_MEMC, (v), (o))
+ #define bcm_ddr_readl(o)	bcm_rset_readl(RSET_DDR, (o))
+ #define bcm_ddr_writel(v, o)	bcm_rset_writel(RSET_DDR, (v), (o))
+#define bcm_misc_readl(o)	bcm_rset_readl(RSET_MISC, (o))
+#define bcm_misc_writel(v, o)	bcm_rset_writel(RSET_MISC, (v), (o))
+ 
+ #endif /* ! BCM63XX_IO_H_ */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1116,4 +1116,14 @@
+ #define TRNG_THRES			0x0c
+ #define TRNG_MASK			0x10
+ 
+/*************************************************************************
+ * _REG relative to RSET_MISC
+ *************************************************************************/
+
+#define MISC_STRAPBUS_6328_REG		0x240
+#define STRAPBUS_6328_FCVO_SHIFT	7
+#define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
+#define STRAPBUS_6328_BOOT_SEL_SERIAL	(1 << 28)
+#define STRAPBUS_6328_BOOT_SEL_NAND	(0 << 28)
+
+ #endif /* BCM63XX_REGS_H_ */