From 3843e5f1aff5fcdef48bb675ed995cda6070998a Mon Sep 17 00:00:00 2001 From: Xiangfu Liu Date: Mon, 12 Oct 2009 12:06:23 +0800 Subject: [PATCH] upgrade u-boot to 2009.08 --- target/linux/xburst/image/u-boot/Makefile | 9 +- ...h => 0001-add-xburst-platform-files.patch} | 3820 +---------------- .../patches/0002-add-xburst-support.patch | 1595 +++++++ .../image/u-boot/patches/0002-fix-mmc.patch | 89 - .../patches/0003-add-2GB-nand-support.patch | 176 - 5 files changed, 1742 insertions(+), 3947 deletions(-) rename target/linux/xburst/image/u-boot/patches/{0001-add-qi_lb60-support.patch => 0001-add-xburst-platform-files.patch} (80%) create mode 100644 target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch delete mode 100644 target/linux/xburst/image/u-boot/patches/0002-fix-mmc.patch delete mode 100644 target/linux/xburst/image/u-boot/patches/0003-add-2GB-nand-support.patch diff --git a/target/linux/xburst/image/u-boot/Makefile b/target/linux/xburst/image/u-boot/Makefile index d83cdd38f..dfb20eff9 100644 --- a/target/linux/xburst/image/u-boot/Makefile +++ b/target/linux/xburst/image/u-boot/Makefile @@ -10,15 +10,12 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=u-boot -PKG_VERSION:=20090707 -PKG_REV:=59869ca72df8bc4e4ffa9dd17cb6673bbe010272 -PKG_RELEASE:=1 +PKG_VERSION:=2009.08 PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 -PKG_SOURCE_URL:=git://git.denx.de/u-boot.git -PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION) -PKG_SOURCE_VERSION:=$(PKG_REV) +PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot +PKG_CAT:=bzcat include $(INCLUDE_DIR)/package.mk diff --git a/target/linux/xburst/image/u-boot/patches/0001-add-qi_lb60-support.patch b/target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch similarity index 80% rename from target/linux/xburst/image/u-boot/patches/0001-add-qi_lb60-support.patch rename to target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch index 933d6f297..ab2eade4e 100644 --- a/target/linux/xburst/image/u-boot/patches/0001-add-qi_lb60-support.patch +++ b/target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch @@ -1,33 +1,67 @@ -diff --git a/Makefile b/Makefile -index 2a06440..91c5b30 100644 ---- a/Makefile -+++ b/Makefile -@@ -165,7 +165,7 @@ ifeq ($(ARCH),i386) - CROSS_COMPILE = i386-linux- - endif - ifeq ($(ARCH),mips) --CROSS_COMPILE = mips_4KC- -+CROSS_COMPILE = mipsel-openwrt-linux- - endif - ifeq ($(ARCH),nios) - CROSS_COMPILE = nios-elf- -@@ -3310,6 +3310,16 @@ qemu_mips_config : unconfig - @$(MKCONFIG) -a qemu-mips mips mips qemu-mips - - ######################################################################### -+## MIPS32 Jz47XX -+######################################################################### -+qi_lb60_config : unconfig -+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h -+ @echo "Compile NAND boot image for Qi_LB60" -+ @$(MKCONFIG) -a qi_lb60 mips mips qi_lb60 -+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/qi_lb60/config.tmp -+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk -+ -+######################################################################### - ## MIPS64 5Kc - ######################################################################### - +From 5c38420f8091019aac00b5c0c2846f0c35b297c4 Mon Sep 17 00:00:00 2001 +From: Xiangfu Liu +Date: Mon, 12 Oct 2009 11:22:48 +0800 +Subject: [PATCH] add xburst platform files + +--- + board/qi_lb60/Makefile | 38 + + board/qi_lb60/config.mk | 33 + + board/qi_lb60/config.tmp | 1 + + board/qi_lb60/flash.c | 50 + + board/qi_lb60/qi_lb60.c | 103 + + board/qi_lb60/u-boot-nand.lds | 63 + + board/qi_lb60/u-boot.lds | 63 + + cpu/mips/jz4740.c | 574 +++++ + cpu/mips/jz4740_cpm_test.c | 98 + + cpu/mips/jz4740_nand.c | 198 ++ + cpu/mips/jz_cs8900.c | 397 +++ + cpu/mips/jz_cs8900.h | 258 ++ + cpu/mips/jz_eth.c | 376 +++ + cpu/mips/jz_eth.h | 267 ++ + cpu/mips/jz_i2c.c | 234 ++ + cpu/mips/jz_lcd.c | 643 +++++ + cpu/mips/jz_lcd.h | 1020 ++++++++ + cpu/mips/jz_mmc.c | 1404 +++++++++++ + cpu/mips/jz_mmc.h | 113 + + cpu/mips/jz_serial.c | 167 ++ + cpu/mips/mmc_protocol.h | 273 +++ + cpu/mips/usb_boot.S | 821 +++++++ + include/asm-mips/jz4740.h | 4880 +++++++++++++++++++++++++++++++++++++ + include/configs/qi_lb60.h | 210 ++ + nand_spl/board/qi_lb60/Makefile | 104 + + nand_spl/board/qi_lb60/config.mk | 34 + + nand_spl/board/qi_lb60/u-boot.lds | 63 + + nand_spl/nand_boot_jz4740.c | 456 ++++ + 28 files changed, 12941 insertions(+), 0 deletions(-) + create mode 100644 board/qi_lb60/Makefile + create mode 100644 board/qi_lb60/config.mk + create mode 100644 board/qi_lb60/config.tmp + create mode 100644 board/qi_lb60/flash.c + create mode 100644 board/qi_lb60/qi_lb60.c + create mode 100644 board/qi_lb60/u-boot-nand.lds + create mode 100644 board/qi_lb60/u-boot.lds + create mode 100644 cpu/mips/jz4740.c + create mode 100644 cpu/mips/jz4740_cpm_test.c + create mode 100644 cpu/mips/jz4740_nand.c + create mode 100644 cpu/mips/jz_cs8900.c + create mode 100644 cpu/mips/jz_cs8900.h + create mode 100644 cpu/mips/jz_eth.c + create mode 100644 cpu/mips/jz_eth.h + create mode 100644 cpu/mips/jz_i2c.c + create mode 100644 cpu/mips/jz_lcd.c + create mode 100644 cpu/mips/jz_lcd.h + create mode 100644 cpu/mips/jz_mmc.c + create mode 100644 cpu/mips/jz_mmc.h + create mode 100644 cpu/mips/jz_serial.c + create mode 100644 cpu/mips/mmc_protocol.h + create mode 100644 cpu/mips/usb_boot.S + create mode 100644 include/asm-mips/jz4740.h + create mode 100644 include/configs/qi_lb60.h + create mode 100644 nand_spl/board/qi_lb60/Makefile + create mode 100644 nand_spl/board/qi_lb60/config.mk + create mode 100644 nand_spl/board/qi_lb60/u-boot.lds + create mode 100644 nand_spl/nand_boot_jz4740.c + diff --git a/board/qi_lb60/Makefile b/board/qi_lb60/Makefile new file mode 100644 index 0000000..470447d @@ -111,6 +145,13 @@ index 0000000..56b77d3 +# RAM version +#TEXT_BASE = 0x80100000 +endif +diff --git a/board/qi_lb60/config.tmp b/board/qi_lb60/config.tmp +new file mode 100644 +index 0000000..3ea6c8c +--- /dev/null ++++ b/board/qi_lb60/config.tmp +@@ -0,0 +1 @@ ++TEXT_BASE = 0x80100000 diff --git a/board/qi_lb60/flash.c b/board/qi_lb60/flash.c new file mode 100644 index 0000000..891c604 @@ -169,10 +210,10 @@ index 0000000..891c604 +} diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c new file mode 100644 -index 0000000..c23534d +index 0000000..572d22b --- /dev/null +++ b/board/qi_lb60/qi_lb60.c -@@ -0,0 +1,106 @@ +@@ -0,0 +1,103 @@ +/* + * Authors: Xiangfu Liu + * @@ -220,47 +261,44 @@ index 0000000..c23534d + __gpio_as_i2c(); + + /* -+ * Initialize Other pins -+ */ -+/* unsigned int i; -+ __gpio_as_output( GPIO_AUDIO_POP ); -+ __gpio_set_pin( GPIO_AUDIO_POP ); -+ -+ -+ for (i = 0; i < 8; i++){ -+ __gpio_as_output( GPIO_KEYOUT_BASE + i ); -+ __gpio_set_pin( GPIO_KEYOUT_BASE + i ); -+ } -+ -+ for (i = 0; i < 7; i++){ -+ __gpio_as_input( GPIO_KEYIN_BASE + i ); -+ __gpio_enable_pull( GPIO_KEYIN_BASE + i ); -+ } -+ -+ __gpio_as_input( GPIO_KEYIN_8 ); -+ __gpio_enable_pull( GPIO_KEYIN_8 ); -+ -+*/ -+ __gpio_as_output( GPIO_LCD_CS ); -+ __gpio_clear_pin( GPIO_LCD_CS ); -+ -+ __gpio_as_output( GPIO_AMP_EN ); -+ __gpio_clear_pin( GPIO_AMP_EN ); -+ -+ __gpio_as_output( GPIO_SDPW_EN ); -+ __gpio_set_pin( GPIO_SDPW_EN ); -+ -+ __gpio_as_input( GPIO_SD_DETECT ); -+ __gpio_enable_pull( GPIO_SD_DETECT ); -+ -+ __gpio_as_input( GPIO_USB_DETECT ); -+ __gpio_enable_pull( GPIO_USB_DETECT ); -+ -+ /* + * Initialize MSC pins + */ + __gpio_as_msc(); -+ __gpio_set_pin(2 + 3 * 32); ++ ++ /* ++ * Initialize Other pins ++ */ ++ unsigned int i; ++ for (i = 0; i < 8; i++) { ++ __gpio_as_output(GPIO_KEYOUT_BASE + i); ++ __gpio_set_pin(GPIO_KEYOUT_BASE + i); ++ } ++ ++ for (i = 0; i < 7; i++){ ++ __gpio_as_input(GPIO_KEYIN_BASE + i); ++ __gpio_enable_pull(GPIO_KEYIN_BASE + i); ++ } ++ /* __gpio_as_input( GPIO_KEYIN_8 ); */ ++ /* __gpio_enable_pull( GPIO_KEYIN_8 ); */ ++ ++ __gpio_as_output(GPIO_AUDIO_POP); ++ __gpio_set_pin(GPIO_AUDIO_POP); ++ ++ __gpio_as_output(GPIO_LCD_CS); ++ __gpio_clear_pin(GPIO_LCD_CS); ++ ++ __gpio_as_output(GPIO_AMP_EN); ++ __gpio_clear_pin(GPIO_AMP_EN); ++ ++ __gpio_as_output(GPIO_SDPW_EN); ++ __gpio_disable_pull(GPIO_SDPW_EN); ++ __gpio_clear_pin(GPIO_SDPW_EN); ++ ++ __gpio_as_input(GPIO_SD_DETECT); ++ __gpio_disable_pull(GPIO_SD_DETECT); ++ ++ __gpio_as_input(GPIO_USB_DETECT); ++ __gpio_enable_pull(GPIO_USB_DETECT); +} + +void board_early_init(void) @@ -417,629 +455,6 @@ index 0000000..a15a96e + .bss : { *(.bss) } + uboot_end = .; +} -diff --git a/common/lcd.c b/common/lcd.c -index 74a5c77..aff35ff 100644 ---- a/common/lcd.c -+++ b/common/lcd.c -@@ -64,7 +64,9 @@ - #ifdef CONFIG_LCD_LOGO - # include /* Get logo data, width and height */ - # if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) --# error Default Color Map overlaps with Logo Color Map -+# ifndef CONFIG_JzRISC /* JzRISC core */ -+# error Default Color Map overlaps with Logo Color Map -+# endif - # endif - #endif - -@@ -83,6 +85,9 @@ extern void lcd_ctrl_init (void *lcdbase); - extern void lcd_enable (void); - static void *lcd_logo (void); - -+#ifdef CONFIG_JzRISC /* JzRISC core */ -+extern int flush_cache_all(void); -+#endif - - #if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) - extern void lcd_setcolreg (ushort regno, -@@ -282,12 +287,24 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) - lcd_color_fg : lcd_color_bg; - bits <<= 1; - } -+#elif LCD_BPP == LCD_COLOR32 -+ uint *m = (uint *)d; -+ for (c=0; c<8; ++c) { -+ *m++ = (bits & 0x80) ? -+ lcd_color_fg : lcd_color_bg; -+ d+=4; -+ bits <<= 1; -+ } - #endif - } - #if LCD_BPP == LCD_MONOCHROME - *d = rest | (*d & ((1 << (8-off)) - 1)); - #endif - } -+ -+#ifdef CONFIG_JzRISC /* JzRISC core */ -+ flush_cache_all(); -+#endif - } - - /*----------------------------------------------------------------------*/ -@@ -410,10 +427,18 @@ static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) - test_pattern(); - #else - /* set framebuffer to background color */ -+#if LCD_BPP == LCD_COLOR32 -+ long long i; -+ int *lcdbase_p = (int *)lcd_base; -+ for(i=0;i - * -@@ -22,33 +22,21 @@ - * MA 02111-1307 USA - */ - -+ - #include --#include -+#include - #include - #include - #include - #include - --#define RA t8 -- --/* -- * 16kB is the maximum size of instruction and data caches on MIPS 4K, -- * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. -- * -- * Note that the above size is the maximum size of primary cache. U-Boot -- * doesn't have L2 cache support for now. -- */ --#define MIPS_MAX_CACHE_SIZE 0x10000 -+#ifndef CONFIG_JzRISC - --#define INDEX_BASE CKSEG0 -+ /* 16KB is the maximum size of instruction and data caches on -+ * MIPS 4K. -+ */ -+#define MIPS_MAX_CACHE_SIZE 0x4000 - -- .macro cache_op op addr -- .set push -- .set noreorder -- .set mips3 -- cache \op, 0(\addr) -- .set pop -- .endm - - /* - * cacheop macro to automate cache operations -@@ -119,79 +107,7 @@ - #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ - icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) - -- .macro f_fill64 dst, offset, val -- LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) --#if LONGSIZE == 4 -- LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) -- LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) --#endif -- .endm -- --/* -- * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) -- */ --LEAF(mips_init_icache) -- blez a1, 9f -- mtc0 zero, CP0_TAGLO -- /* clear tag to invalidate */ -- PTR_LI t0, INDEX_BASE -- PTR_ADDU t1, t0, a1 --1: cache_op Index_Store_Tag_I t0 -- PTR_ADDU t0, a2 -- bne t0, t1, 1b -- /* fill once, so data field parity is correct */ -- PTR_LI t0, INDEX_BASE --2: cache_op Fill t0 -- PTR_ADDU t0, a2 -- bne t0, t1, 2b -- /* invalidate again - prudent but not strictly neccessary */ -- PTR_LI t0, INDEX_BASE --1: cache_op Index_Store_Tag_I t0 -- PTR_ADDU t0, a2 -- bne t0, t1, 1b --9: jr ra -- END(mips_init_icache) -- - /* -- * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) -- */ --LEAF(mips_init_dcache) -- blez a1, 9f -- mtc0 zero, CP0_TAGLO -- /* clear all tags */ -- PTR_LI t0, INDEX_BASE -- PTR_ADDU t1, t0, a1 --1: cache_op Index_Store_Tag_D t0 -- PTR_ADDU t0, a2 -- bne t0, t1, 1b -- /* load from each line (in cached space) */ -- PTR_LI t0, INDEX_BASE --2: LONG_L zero, 0(t0) -- PTR_ADDU t0, a2 -- bne t0, t1, 2b -- /* clear all tags */ -- PTR_LI t0, INDEX_BASE --1: cache_op Index_Store_Tag_D t0 -- PTR_ADDU t0, a2 -- bne t0, t1, 1b --9: jr ra -- END(mips_init_dcache) -- --/******************************************************************************* --* - * mips_cache_reset - low level initialisation of the primary caches - * - * This routine initialises the primary caches to ensure that they -@@ -204,112 +120,129 @@ LEAF(mips_init_dcache) - * a source of parity. - * - * RETURNS: N/A --* - */ --NESTED(mips_cache_reset, 0, ra) -- move RA, ra -+ .globl mips_cache_reset -+ .ent mips_cache_reset -+mips_cache_reset: -+ - li t2, CONFIG_SYS_ICACHE_SIZE - li t3, CONFIG_SYS_DCACHE_SIZE - li t4, CONFIG_SYS_CACHELINE_SIZE - move t5, t4 - -+ - li v0, MIPS_MAX_CACHE_SIZE - -- /* -- * Now clear that much memory starting from zero. -+ /* Now clear that much memory starting from zero. - */ -- PTR_LI a0, CKSEG1 -- PTR_ADDU a1, a0, v0 --2: PTR_ADDIU a0, 64 -- f_fill64 a0, -64, zero -- bne a0, a1, 2b -- -- /* -- * The caches are probably in an indeterminate state, -- * so we force good parity into them by doing an -- * invalidate, load/fill, invalidate for each line. -+ -+ li a0, KSEG1 -+ addu a1, a0, v0 -+ -+2: sw zero, 0(a0) -+ sw zero, 4(a0) -+ sw zero, 8(a0) -+ sw zero, 12(a0) -+ sw zero, 16(a0) -+ sw zero, 20(a0) -+ sw zero, 24(a0) -+ sw zero, 28(a0) -+ addu a0, 32 -+ bltu a0, a1, 2b -+ -+ /* Set invalid tag. - */ - -- /* -- * Assume bottom of RAM will generate good parity for the cache. -+ mtc0 zero, CP0_TAGLO -+ -+ /* -+ * The caches are probably in an indeterminate state, -+ * so we force good parity into them by doing an -+ * invalidate, load/fill, invalidate for each line. -+ */ -+ -+ /* Assume bottom of RAM will generate good parity for the cache. - */ - -- /* -- * Initialize the I-cache first, -+ li a0, K0BASE -+ move a2, t2 # icacheSize -+ move a3, t4 # icacheLineSize -+ move a1, a2 -+ icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) -+ -+ /* To support Orion/R4600, we initialise the data cache in 3 passes. - */ -- move a1, t2 -- move a2, t4 -- PTR_LA t7, mips_init_icache -- jalr t7 - -- /* -- * then initialize D-cache. -+ /* 1: initialise dcache tags. - */ -- move a1, t3 -- move a2, t5 -- PTR_LA t7, mips_init_dcache -- jalr t7 - -- jr RA -- END(mips_cache_reset) -+ li a0, K0BASE -+ move a2, t3 # dcacheSize -+ move a3, t5 # dcacheLineSize -+ move a1, a2 -+ icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - --/******************************************************************************* --* --* dcache_status - get cache status --* --* RETURNS: 0 - cache disabled; 1 - cache enabled --* --*/ --LEAF(dcache_status) -- mfc0 t0, CP0_CONFIG -- li t1, CONF_CM_UNCACHED -- andi t0, t0, CONF_CM_CMASK -- move v0, zero -- beq t0, t1, 2f -- li v0, 1 --2: jr ra -- END(dcache_status) -- --/******************************************************************************* --* -+ /* 2: fill dcache. -+ */ -+ -+ li a0, K0BASE -+ move a2, t3 # dcacheSize -+ move a3, t5 # dcacheLineSize -+ move a1, a2 -+ icacheopn(a0,a1,a2,a3,1lw,(dummy)) -+ -+ /* 3: clear dcache tags. -+ */ -+ -+ li a0, K0BASE -+ move a2, t3 # dcacheSize -+ move a3, t5 # dcacheLineSize -+ move a1, a2 -+ icacheop(a0,a1,a2,a3,Index_Store_Tag_D) -+ -+ j ra -+ .end mips_cache_reset -+ -+ -+/* -+ * dcache_status - get cache status -+ * -+ * RETURNS: 0 - cache disabled; 1 - cache enabled -+ */ -+ .globl dcache_status -+ .ent dcache_status -+dcache_status: -+ -+ mfc0 v0, CP0_CONFIG -+ andi v0, v0, 1 -+ j ra -+ -+ .end dcache_status -+ -+/* - * dcache_disable - disable cache - * - * RETURNS: N/A --* - */ --LEAF(dcache_disable) -+ .globl dcache_disable -+ .ent dcache_disable -+dcache_disable: -+ - mfc0 t0, CP0_CONFIG - li t1, -8 - and t0, t0, t1 - ori t0, t0, CONF_CM_UNCACHED -- mtc0 t0, CP0_CONFIG -- jr ra -- END(dcache_disable) -+ mtc0 t0, CP0_CONFIG -+ j ra - --/******************************************************************************* --* --* dcache_enable - enable cache --* --* RETURNS: N/A --* --*/ --LEAF(dcache_enable) -- mfc0 t0, CP0_CONFIG -- ori t0, CONF_CM_CMASK -- xori t0, CONF_CM_CMASK -- ori t0, CONF_CM_CACHABLE_NONCOHERENT -- mtc0 t0, CP0_CONFIG -- jr ra -- END(dcache_enable) -- --#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS --/******************************************************************************* --* --* mips_cache_lock - lock RAM area pointed to by a0 in cache. --* --* RETURNS: N/A --* --*/ -+ .end dcache_disable -+ -+ -+/* -+ * mips_cache_lock - lock RAM area pointed to by a0 in cache. -+ * -+ * RETURNS: N/A -+ */ - #if defined(CONFIG_PURPLE) - # define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2) - #else -@@ -318,14 +251,14 @@ LEAF(dcache_enable) - .globl mips_cache_lock - .ent mips_cache_lock - mips_cache_lock: -- li a1, CKSEG0 - CACHE_LOCK_SIZE -+ li a1, K0BASE - CACHE_LOCK_SIZE - addu a0, a1 - li a2, CACHE_LOCK_SIZE - li a3, CONFIG_SYS_CACHELINE_SIZE - move a1, a2 - icacheop(a0,a1,a2,a3,0x1d) - -- jr ra -- -+ j ra - .end mips_cache_lock --#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */ -+ -+#endif /* CONFIG_JzRISC */ -diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk -index a173c54..8d27e52 100644 ---- a/cpu/mips/config.mk -+++ b/cpu/mips/config.mk -@@ -25,15 +25,15 @@ MIPSFLAGS:=$(shell \ - if [ "$v" -lt "14" ]; then \ - echo "-mcpu=4kc"; \ - else \ -- echo "-march=4kc -mtune=4kc"; \ -+ echo "-march=4kc -mtune=r4600"; \ - fi) - - ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) - ENDIANNESS = -EL - else --ENDIANNESS = -EB -+#ENDIANNESS = -EB - endif - --MIPSFLAGS += $(ENDIANNESS) -+MIPSFLAGS += $(ENDIANNESS) -mabicalls -mips32 -O2 - - PLATFORM_CPPFLAGS += $(MIPSFLAGS) -diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c -index d5a1604..48e1cea 100644 ---- a/cpu/mips/cpu.c -+++ b/cpu/mips/cpu.c -@@ -28,6 +28,12 @@ - #include - #include - -+#ifdef CONFIG_JZ4740 -+#include -+#endif -+ -+#if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL) -+ - #define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ -@@ -40,6 +46,19 @@ - - void __attribute__((weak)) _machine_restart(void) - { -+#ifdef CONFIG_JZ4740 -+ __wdt_select_extalclk(); -+ __wdt_select_clk_div64(); -+ __wdt_set_data(100); -+ __wdt_set_count(0); -+ __tcu_start_wdt_clock(); -+ __wdt_start(); -+ while(1); -+#endif -+#if defined(CONFIG_JzRISC) -+ void (*f)(void) = (void *) 0xbfc00000; -+ f(); -+#endif - } - - int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -@@ -110,3 +129,59 @@ int cpu_eth_init(bd_t *bis) - #endif - return 0; - } -+ -+#endif /* !CONFIG_NAND_SPL !CONFIG_MSC_SPL */ -+ -+#ifdef CONFIG_JzRISC -+void flush_icache_all(void) -+{ -+ u32 addr, t = 0; -+ -+ asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ -+ asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ -+ -+ for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; -+ addr += CONFIG_SYS_CACHELINE_SIZE) { -+ asm volatile ( -+ ".set mips3\n\t" -+ " cache %0, 0(%1)\n\t" -+ ".set mips2\n\t" -+ : -+ : "I" (Index_Store_Tag_I), "r"(addr)); -+ } -+ -+ /* invalicate btb */ -+ asm volatile ( -+ ".set mips32\n\t" -+ "mfc0 %0, $16, 7\n\t" -+ "nop\n\t" -+ "ori %0,2\n\t" -+ "mtc0 %0, $16, 7\n\t" -+ ".set mips2\n\t" -+ : -+ : "r" (t)); -+} -+ -+void flush_dcache_all(void) -+{ -+ u32 addr; -+ -+ for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; -+ addr += CONFIG_SYS_CACHELINE_SIZE) { -+ asm volatile ( -+ ".set mips3\n\t" -+ " cache %0, 0(%1)\n\t" -+ ".set mips2\n\t" -+ : -+ : "I" (Index_Writeback_Inv_D), "r"(addr)); -+ } -+ -+ asm volatile ("sync"); -+} -+ -+void flush_cache_all(void) -+{ -+ flush_dcache_all(); -+ flush_icache_all(); -+} -+#endif /* CONFIG_JzRISC */ diff --git a/cpu/mips/jz4740.c b/cpu/mips/jz4740.c new file mode 100644 index 0000000..87e0ccf @@ -3492,10 +2907,10 @@ index 0000000..9f3faee + diff --git a/cpu/mips/jz_lcd.c b/cpu/mips/jz_lcd.c new file mode 100644 -index 0000000..17098b3 +index 0000000..36361ba --- /dev/null +++ b/cpu/mips/jz_lcd.c -@@ -0,0 +1,645 @@ +@@ -0,0 +1,643 @@ +/* + * JzRISC lcd controller + * @@ -3521,13 +2936,11 @@ index 0000000..17098b3 + * Fallowing macro may be used: + * CONFIG_LCD : LCD support + * LCD_BPP : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 -+ * CFG_WHITE_ON_BLACK + * CONFIG_LCD_LOGO : show logo + */ + +#include +#include -+#include +#include + +#include /* virt_to_phys() */ @@ -5169,7 +4582,7 @@ index 0000000..d2e7cc4 +#endif /* __JZLCD_H__ */ diff --git a/cpu/mips/jz_mmc.c b/cpu/mips/jz_mmc.c new file mode 100644 -index 0000000..8a7c310 +index 0000000..ec0a518 --- /dev/null +++ b/cpu/mips/jz_mmc.c @@ -0,0 +1,1404 @@ @@ -5236,7 +4649,7 @@ index 0000000..8a7c310 +({ \ + int detected = 1; \ + __gpio_as_input(GPIO_SD_CD_N); \ -+ if (__gpio_get_pin(GPIO_SD_CD_N)) \ ++ if (!__gpio_get_pin(GPIO_SD_CD_N)) \ + detected = 0; \ + detected; \ +}) @@ -7148,589 +6561,6 @@ index 0000000..9028cdf +#endif /* MMC_DEBUG_EN */ + +#endif /* __MMC_PROTOCOL__ */ -diff --git a/cpu/mips/start.S b/cpu/mips/start.S -index 57db589..fa6e352 100644 ---- a/cpu/mips/start.S -+++ b/cpu/mips/start.S -@@ -23,32 +23,33 @@ - */ - - #include -+#include - #include - #include -+#include -+#include - -- /* -- * For the moment disable interrupts, mark the kernel mode and -- * set ST0_KX so that the CPU does not spit fire when using -- * 64-bit addresses. -- */ -- .macro setup_c0_status set clr -- .set push -- mfc0 t0, CP0_STATUS -- or t0, ST0_CU0 | \set | 0x1f | \clr -- xor t0, 0x1f | \clr -- mtc0 t0, CP0_STATUS -- .set noreorder -- sll zero, 3 # ehb -- .set pop -- .endm -- -- .macro setup_c0_status_reset --#ifdef CONFIG_64BIT -- setup_c0_status ST0_KX 0 --#else -- setup_c0_status 0 0 -+#ifdef CONFIG_JZ4730 -+#include -+#endif -+ -+#ifdef CONFIG_JZ4740 -+#include -+#endif -+ -+#ifdef CONFIG_JZ4750 -+#include -+#endif -+ -+#ifdef CONFIG_JZ4750D -+#include -+#endif -+ -+#if defined(CONFIG_JZ4750) || defined(CONFIG_JZ4750D) -+#define JZ4750_NANDBOOT_CFG0 (0x55555500 | (CFG_NAND_BW8*0xff)) -+#define JZ4750_NANDBOOT_CFG1 0x55555555 -+#define JZ4750_NANDBOOT_CFG2 ((CFG_NAND_PAGE_SIZE==2048)&0xff0000) | ((CFG_NAND_PAGE_SIZE!=512)&0xff00) | ((CFG_NAND_ROW_CYCLE==3)&0xff) - #endif -- .endm - - #define RVECENT(f,n) \ - b f; nop -@@ -61,6 +62,28 @@ - .globl _start - .text - _start: -+#if defined(CONFIG_JZ4740) -+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) -+ .word JZ4740_NORBOOT_CFG /* fetched during NOR Boot */ -+#else -+#if defined(CONFIG_NAND_SPL) -+ .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */ -+#endif -+#endif -+#endif /* CONFIG_JZ4740 */ -+#if defined(CONFIG_JZ4750) || defined(CONFIG_JZ4750D) -+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) -+ .word JZ4750_NORBOOT_CFG /* fetched during NOR Boot */ -+#else -+#if defined(CONFIG_NAND_SPL) && !defined(CONFIG_MSC_SPL) -+ /* First three words fetched by CPU during NAND Boot */ -+ .word JZ4750_NANDBOOT_CFG0 -+ .word JZ4750_NANDBOOT_CFG1 -+ .word JZ4750_NANDBOOT_CFG2 -+#endif -+#endif -+#endif /* CONFIG_JZ4750 || CONFIG_JZ4750D */ -+#if !defined(CONFIG_JzRISC) - RVECENT(reset,0) /* U-boot entry point */ - RVECENT(reset,1) /* software reboot */ - #if defined(CONFIG_INCA_IP) -@@ -213,7 +236,7 @@ _start: - .word 0x00000000 - .word 0x03e00008 - .word 0x00000000 -- .word 0x00000000 -+ .word 0x00000000 - /* 0xbfc00428 */ - .word 0xdc870000 - .word 0xfca70000 -@@ -224,74 +247,192 @@ _start: - .word 0x00000000 - .word 0x03e00008 - .word 0x00000000 -- .word 0x00000000 -+ .word 0x00000000 - #endif /* CONFIG_PURPLE */ - .align 4 -+#endif /* CONFIG_JzRISC */ -+ - reset: - -+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -+ -+#ifdef CONFIG_JZ4730 -+ -+ /* Disable interrupts */ -+ la t0, INTC_IMR -+ li t1, 0xffffffff -+ sw t1, 0(t0) -+ -+ /* -+ * Clear SCR.HGP -+ */ -+ la t0, CPM_SCR -+ lw t1, 0(t0) -+ ori t1, 0x8 -+ xori t1, 0x8 -+ sw t1, 0(t0) -+ -+ /* -+ * Set usb port0 as host -+ */ -+ la t0, HARB_HAPOR -+ lw t1, 0(t0) -+ ori t1, HARB_HAPOR_UCHSEL -+ sw t1, 0(t0) -+ -+ /* -+ * Check reset status -+ */ -+ la t0, CPM_RSTR -+ lw t1, 0(t0) -+ andi t1, 0x4 -+ bnez t1, resume_from_hibernate -+ nop -+#endif /* CONFIG_JZ4730 */ -+ -+#ifndef CONFIG_NAND_SPL - /* Clear watch registers. - */ - mtc0 zero, CP0_WATCHLO - mtc0 zero, CP0_WATCHHI -+#endif - -- /* WP(Watch Pending), SW0/1 should be cleared. */ -- mtc0 zero, CP0_CAUSE -+ /* STATUS register */ -+#ifdef CONFIG_JzRISC -+ /* -+ * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1 -+ */ -+ li t0, 0x0040FC04 -+ mtc0 t0, CP0_STATUS -+#else -+#ifdef CONFIG_TB0229 -+ li k0, ST0_CU0 -+#else -+ mfc0 k0, CP0_STATUS -+#endif -+ li k1, ~ST0_IE -+ and k0, k1 -+ mtc0 k0, CP0_STATUS -+#endif - -- setup_c0_status_reset -+ /* CAUSE register */ -+#ifdef CONFIG_JzRISC -+ /* IV=1, use the specical interrupt vector (0x200) */ -+ li t1, 0x00800000 -+ mtc0 t1, CP0_CAUSE -+#else -+ mtc0 zero, CP0_CAUSE -+#endif - -+#ifndef CONFIG_JzRISC - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE -+#endif - --#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) -+#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ -+ -+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) - /* CONFIG0 register */ - li t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG --#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ -+#endif - -- /* Initialize $gp. -+ /* Initialize GOT pointer. -+ */ -+ bal 1f -+ nop -+ .word _GLOBAL_OFFSET_TABLE_ -+ 1: -+ move gp, ra -+ lw t1, 0(ra) -+ move gp, t1 -+ -+#ifdef CONFIG_INCA_IP -+ /* Disable INCA-IP Watchdog. - */ -- bal 1f -+ la t9, disable_incaip_wdt -+ jalr t9 - nop -- .word _gp --1: -- lw gp, 0(ra) -+#endif - --#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) -+/* JzRISC will init external memory in board_init_f, -+ which uses cache as stack and calls into C code. */ -+#ifndef CONFIG_JzRISC - /* Initialize any external memory. - */ -- la t9, lowlevel_init -- jalr t9 -+ la t9, lowlevel_init -+ jalr t9 - nop -+#endif - -+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) - /* Initialize caches... - */ -- la t9, mips_cache_reset -- jalr t9 -+#ifdef CONFIG_JzRISC -+ .set mips32 -+ mtc0 zero, CP0_TAGLO -+ mtc0 zero, CP0_TAGHI -+ -+ li t0, K0BASE -+ ori t1, t0, CONFIG_SYS_DCACHE_SIZE -+1: -+ cache Index_Store_Tag_D, 0(t0) -+ bne t0, t1, 1b -+ addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE -+ -+ li t0, K0BASE -+ ori t1, t0, CONFIG_SYS_ICACHE_SIZE -+2: -+ cache Index_Store_Tag_I, 0(t0) -+ bne t0, t1, 2b -+ addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE -+ -+ /* Invalidate BTB */ -+ mfc0 t0, CP0_CONFIG, 7 -+ nop -+ ori t0, 2 -+ mtc0 t0, CP0_CONFIG, 7 - nop - -+ .set mips2 -+#else -+ la t9, mips_cache_reset -+ jalr t9 -+ nop -+#endif -+ - /* ... and enable them. - */ - li t0, CONF_CM_CACHABLE_NONCOHERENT - mtc0 t0, CP0_CONFIG --#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ -+ nop -+ -+#endif /* !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) */ - - /* Set up temporary stack. - */ --#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS -+#ifndef CONFIG_JzRISC - li a0, CONFIG_SYS_INIT_SP_OFFSET -- la t9, mips_cache_lock -- jalr t9 -+ la t9, mips_cache_lock -+ jalr t9 - nop - #endif - -+#ifdef CONFIG_NAND_SPL -+ la sp, 0x80004000 -+ la t9, nand_boot -+ j t9 -+ nop -+#else - li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - la sp, 0(t0) - - la t9, board_init_f -- jr t9 -+ j t9 - nop - -+ - /* - * void relocate_code (addr_sp, gd, addr_moni) - * -@@ -305,37 +446,28 @@ reset: - .globl relocate_code - .ent relocate_code - relocate_code: -- move sp, a0 /* Set new stack pointer */ -+ move sp, a0 /* Set new stack pointer */ - -- li t0, CONFIG_SYS_MONITOR_BASE -+ li t0, TEXT_BASE - la t3, in_ram - lw t2, -12(t3) /* t2 <-- uboot_end_data */ - move t1, a2 -- move s2, a2 /* s2 <-- destination address */ - - /* -- * Fix $gp: -+ * Fix GOT pointer: - * -- * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address -+ * New GOT-PTR = (old GOT-PTR - TEXT_BASE) + Destination Address - */ - move t6, gp -- sub gp, CONFIG_SYS_MONITOR_BASE -- add gp, a2 /* gp now adjusted */ -- sub s1, gp, t6 /* s1 <-- relocation offset */ -+ sub gp, TEXT_BASE -+ add gp, a2 /* gp now adjusted */ -+ sub t6, gp, t6 /* t6 <-- relocation offset */ - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -- -- /* -- * Save destination address and size for later usage in flush_cache() -- */ -- move s0, a1 /* save gd in s0 */ -- move a0, t1 /* a0 <-- destination addr */ -- sub a1, t2, t0 /* a1 <-- size */ -- - /* On the purple board we copy the code earlier in a special way - * in order to solve flash problems - */ -@@ -345,47 +477,61 @@ relocate_code: - sw t3, 0(t1) - addu t0, 4 - ble t0, t2, 1b -- addu t1, 4 /* delay slot */ -+ addu t1, 4 /* delay slot */ - #endif - - /* If caches were enabled, we would have to flush them here. - */ -- -- /* a0 & a1 are already set up for flush_cache(start, size) */ -- la t9, flush_cache -- jalr t9 -+#ifdef CONFIG_JzRISC -+ /* flush d-cache */ -+ .set mips32 -+ li t0, KSEG0 -+ addi t1, t0, CONFIG_SYS_DCACHE_SIZE -+2: -+ cache Index_Writeback_Inv_D, 0(t0) -+ bne t0, t1, 2b -+ addi t0, CONFIG_SYS_CACHELINE_SIZE -+ -+ sync -+ -+ /* flush i-cache */ -+ li t0, KSEG0 -+ addi t1, t0, CONFIG_SYS_ICACHE_SIZE -+3: -+ cache Index_Invalidate_I, 0(t0) -+ bne t0, t1, 3b -+ addi t0, CONFIG_SYS_CACHELINE_SIZE -+ -+ /* Invalidate BTB */ -+ mfc0 t0, CP0_CONFIG, 7 -+ nop -+ ori t0, 2 -+ mtc0 t0, CP0_CONFIG, 7 - nop - -+ .set mips0 -+#endif -+ - /* Jump to where we've relocated ourselves. - */ -- addi t0, s2, in_ram - _start -- jr t0 -+ addi t0, a2, in_ram - _start -+ j t0 - nop - -- .word _gp -- .word _GLOBAL_OFFSET_TABLE_ - .word uboot_end_data - .word uboot_end - .word num_got_entries - - in_ram: -- /* -- * Now we want to update GOT. -- * -- * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object -- * generated by GNU ld. Skip these reserved entries from relocation. -+ /* Now we want to update GOT. - */ - lw t3, -4(t0) /* t3 <-- num_got_entries */ -- lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */ -- lw t5, -20(t0) /* t5 <-- _gp */ -- sub t4, t5 /* compute offset*/ -- add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */ -- addi t4, t4, 8 /* Skipping first two entries. */ -+ addi t4, gp, 8 /* Skipping first two entries. */ - li t2, 2 - 1: - lw t1, 0(t4) - beqz t1, 2f -- add t1, s1 -+ add t1, t6 - sw t1, 0(t4) - 2: - addi t2, 1 -@@ -396,26 +542,134 @@ in_ram: - */ - lw t1, -12(t0) /* t1 <-- uboot_end_data */ - lw t2, -8(t0) /* t2 <-- uboot_end */ -- add t1, s1 /* adjust pointers */ -- add t2, s1 -+ add t1, t6 /* adjust pointers */ -+ add t2, t6 - - sub t1, 4 --1: -- addi t1, 4 -+1: addi t1, 4 - bltl t1, t2, 1b - sw zero, 0(t1) /* delay slot */ - -- move a0, s0 /* a0 <-- gd */ -+ move a0, a1 - la t9, board_init_r -- jr t9 -- move a1, s2 /* delay slot */ -+ j t9 -+ move a1, a2 /* delay slot */ - - .end relocate_code - -+#endif /* CONFIG_NAND_SPL */ -+ -+#if !defined(CONFIG_JzRISC) - /* Exception handlers. - */ - romReserved: -- b romReserved -+ b romReserved - - romExcHandle: -- b romExcHandle -+ b romExcHandle -+#endif -+ -+#ifdef CONFIG_JZ4730 -+ -+/* These are the runtime values, modify them according to your platform. */ -+#define PLCR1_VAL 0x1b000520 -+#define CFCR_VAL 0x0c526220 -+ -+#define DMCR_VAL0 0x042a3211 -+#define DMCR_VAL1 0x05aa3211 /*(DMCR_VAL0|EMC_DMCR_RFSH|EMC_DMCR_MRSET)*/ -+ -+#define RTCOR_VAL 0x10 -+#define RTCSR_VAL 0x83 -+ -+ /* -+ * cpu was reset from hibernate mode -+ */ -+resume_from_hibernate: -+ /* -+ * Init PLL -+ */ -+ la t0, 0xB0000000 /* CFCR */ -+ li t1, CFCR_VAL -+ sw t1, 0(t0) -+ -+ la t0, 0xB0000010 /* PLCR1 */ -+ li t1, PLCR1_VAL -+ sw t1, 0(t0) -+ nop;nop;nop;nop -+ -+ /* Init caches */ -+ .set mips32 -+ mtc0 zero, CP0_TAGLO -+ mtc0 zero, CP0_TAGHI -+ -+ li t0, K0BASE -+ ori t1, t0, CONFIG_SYS_DCACHE_SIZE -+1: -+ cache Index_Store_Tag_D, 0(t0) -+ cache Index_Store_Tag_I, 0(t0) -+ bne t0, t1, 1b -+ addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE -+ -+ /* -+ * Init SDRAM -+ */ -+ la t0, 0xB0010070 /* GPALR2 */ -+ lw t1, 0(t0) -+ li t2, 0x3FFFFFFF -+ and t1, t2 -+ li t2, 0x40000000 -+ or t1, t2 -+ sw t1, 0(t0) -+ -+ la t0, 0xB0010074 /* GPAUR2 */ -+ lw t1, 0(t0) -+ li t2, 0xFFFF0000 -+ and t1, t2 -+ li t2, 0x00005555 -+ or t1, t2 -+ sw t1, 0(t0) -+ -+ la t0, 0xB3010000 /* EMC base address */ -+ -+ li t1, DMCR_VAL0 /* DMCR */ -+ sw t1, 0x80(t0) -+ -+ li t1, RTCOR_VAL -+ sh t1, 0x8c(t0) /* RTCOR */ -+ -+ li t1, RTCSR_VAL -+ sh t1, 0x84(t0) /* RTCSR */ -+ -+ /* precharge all chip-selects */ -+ ori t1, t0, 0xa088 -+ sb $0, 0(t1) -+ ori t1, t0, 0xb088 -+ sb $0, 0(t1) -+ -+ /* delay about 200us */ -+ li t1, 0x20000 -+1: -+ bnez t1, 1b -+ sub t1, 1 -+ -+ la t1, DMCR_VAL1 /* DMCR */ -+ sw t1, 0x80(t0) -+ -+ /* write sdram mode register for each chip-select */ -+ ori t1, t0, 0xa088 -+ sb $0, 0(t1) -+ ori t1, t0, 0xb088 -+ sb $0, 0(t1) -+ -+ /* -+ * jump to resume entry point -+ */ -+ la t0, CPM_SPR -+ lw t1, 0(t0) -+ li t0, 0x80000000 -+ or t0, t1 -+ -+ j t0 -+ nop -+ -+#endif /* CONFIG_JZ4730 */ diff --git a/cpu/mips/usb_boot.S b/cpu/mips/usb_boot.S new file mode 100644 index 0000000..6c3788f @@ -8558,182 +7388,6 @@ index 0000000..6c3788f + .byte 0x31 + + .set reorder -diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c -index 360b070..88717e9 100644 ---- a/drivers/mtd/nand/nand_base.c -+++ b/drivers/mtd/nand/nand_base.c -@@ -109,6 +109,22 @@ static struct nand_ecclayout nand_oob_16 = { - . length = 8}} - }; - -+#if defined(CONFIG_JZ4740) -+static struct nand_ecclayout nand_oob_64 = { -+ .eccbytes = 36, -+ .eccpos = { -+ 6, 7, 8, 9, 10, 11, 12, 13, -+ 14, 15, 16, 17, 18, 19, 20, 21, -+ 22, 23, 24, 25, 26, 27, 28, 29, -+ 30, 31, 32, 33, 34, 35, 36, 37, -+ 38, 39, 40, 41}, -+ .oobfree ={ -+ {.offset = 2, -+ .length = 4}, -+ {.offset = 42, -+ .length = 22}} -+}; -+#else - static struct nand_ecclayout nand_oob_64 = { - .eccbytes = 24, - .eccpos = { -@@ -119,6 +135,7 @@ static struct nand_ecclayout nand_oob_64 = { - {.offset = 2, - .length = 38}} - }; -+#endif - - static struct nand_ecclayout nand_oob_128 = { - .eccbytes = 48, -@@ -1068,6 +1085,60 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - } - - /** -+ * nand_read_page_hwecc_rs - [REPLACABLE] hardware rs ecc based page read function -+ * @mtd: mtd info structure -+ * @chip: nand chip info structure -+ * @buf: buffer to store read data -+ * -+ * Not for syndrome calculating ecc controllers which need a special oob layout -+ */ -+static int nand_read_page_hwecc_rs(struct mtd_info *mtd, struct nand_chip *chip, -+ uint8_t *buf) -+{ -+ int i, eccsize = chip->ecc.size; -+ int eccbytes = chip->ecc.bytes; -+ int eccsteps = chip->ecc.steps; -+ uint8_t *p = buf; -+ uint8_t *ecc_calc = chip->buffers->ecccalc; -+ uint8_t *ecc_code = chip->buffers->ecccode; -+ uint32_t *eccpos = chip->ecc.layout->eccpos; -+ uint32_t page; -+ uint8_t flag = 0; -+ -+ page = (buf[3]<<24) + (buf[2]<<16) + (buf[1]<<8) + buf[0]; -+ -+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); -+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); -+ -+ for (i = 0; i < chip->ecc.total; i++) { -+ ecc_code[i] = chip->oob_poi[eccpos[i]]; -+ if (ecc_code[i] != 0xff) -+ flag = 1; -+ } -+ -+ eccsteps = chip->ecc.steps; -+ p = buf; -+ -+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0x00, -1); -+ for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { -+ int stat; -+ if (flag) { -+ chip->ecc.hwctl(mtd, NAND_ECC_READ); -+ chip->read_buf(mtd, p, eccsize); -+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); -+ if (stat < 0) -+ mtd->ecc_stats.failed++; -+ else -+ mtd->ecc_stats.corrected += stat; -+ } -+ else { -+ chip->ecc.hwctl(mtd, NAND_ECC_READ); -+ chip->read_buf(mtd, p, eccsize); -+ } -+ } -+ return 0; -+} -+/** - * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read - * @mtd: mtd info structure - * @chip: nand chip info structure -@@ -1222,8 +1293,15 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, - ret = chip->ecc.read_page_raw(mtd, chip, bufpoi); - else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) - ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); -- else -+ else { -+#if defined(CONFIG_JZ4740) -+ bufpoi[0] = (uint8_t)page; -+ bufpoi[1] = (uint8_t)(page >> 8); -+ bufpoi[2] = (uint8_t)(page >> 16); -+ bufpoi[3] = (uint8_t)(page >> 24); -+#endif - ret = chip->ecc.read_page(mtd, chip, bufpoi); -+ } - if (ret < 0) - break; - -@@ -2730,8 +2808,13 @@ int nand_scan_tail(struct mtd_info *mtd) - switch (chip->ecc.mode) { - case NAND_ECC_HW: - /* Use standard hwecc read page function ? */ -- if (!chip->ecc.read_page) -+ if (!chip->ecc.read_page) { -+#if defined(CONFIG_JZ4740) -+ chip->ecc.read_page = nand_read_page_hwecc_rs; -+#else - chip->ecc.read_page = nand_read_page_hwecc; -+#endif -+ } - if (!chip->ecc.write_page) - chip->ecc.write_page = nand_write_page_hwecc; - if (!chip->ecc.read_oob) -diff --git a/examples/mips.lds b/examples/mips.lds -index 717b201..22478c6 100644 ---- a/examples/mips.lds -+++ b/examples/mips.lds -@@ -23,8 +23,9 @@ - - /* - OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") --*/ - OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -+*/ -+ - OUTPUT_ARCH(mips) - SECTIONS - { -diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h -index 3a1e6d6..2ee6920 100644 ---- a/include/asm-mips/addrspace.h -+++ b/include/asm-mips/addrspace.h -@@ -131,7 +131,7 @@ - * Returns the uncached address of a sdram address - */ - #ifndef __ASSEMBLY__ --#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) -+#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) || defined(CONFIG_JzRISC) - /* We use a 36 bit physical address map here and - cannot access physical memory directly from core */ - #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h -index b2c4891..db88704 100644 ---- a/include/asm-mips/global_data.h -+++ b/include/asm-mips/global_data.h -@@ -39,6 +39,15 @@ - typedef struct global_data { - bd_t *bd; - unsigned long flags; -+#if defined(CONFIG_JZSOC) -+ /* There are other clocks in the Jz47xx or Jz5730*/ -+ unsigned long cpu_clk; /* CPU core clock */ -+ unsigned long sys_clk; /* System bus clock */ -+ unsigned long per_clk; /* Peripheral bus clock */ -+ unsigned long mem_clk; /* Memory bus clock */ -+ unsigned long dev_clk; /* Device clock */ -+ unsigned long fb_base; /* base address of framebuffer */ -+#endif - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ diff --git a/include/asm-mips/jz4740.h b/include/asm-mips/jz4740.h new file mode 100644 index 0000000..2840bc0 @@ -13622,10 +12276,10 @@ index 0000000..2840bc0 +#endif /* __JZ4740_H__ */ diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h new file mode 100644 -index 0000000..68a2e87 +index 0000000..28b10aa --- /dev/null +++ b/include/configs/qi_lb60.h -@@ -0,0 +1,225 @@ +@@ -0,0 +1,210 @@ +/* + * Authors: Xiangfu Liu + * @@ -13641,7 +12295,6 @@ index 0000000..68a2e87 +#ifndef __CONFIG_H +#define __CONFIG_H + -+#define DEBUG +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_JzRISC 1 /* JzRISC core */ +#define CONFIG_JZSOC 1 /* Jz SoC */ @@ -13649,18 +12302,17 @@ index 0000000..68a2e87 +#define CONFIG_QI_LB60 1 /* Qi_LB60 board */ + +#define CONFIG_DOS_PARTITION 1 -+#define CONFIG_PCMCIA_SLOT_A 1 + -+#define CONFIG_LCD 1 /* LCD support */ ++#define CONFIG_LCD 1 /* LCD support */ +#define LCD_BPP LCD_COLOR32/*5:18,24,32 bits per pixel */ +#define CONFIG_JZLCD_FOXCONN_PT035TN01 + +/* NAND Boot config code */ +#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 + -+#define CONFIG_CPU_SPEED 252000000 /* CPU clock: 252 MHz */ ++#define CONFIG_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ +#define CONFIG_EXTAL 12000000 /* EXTAL freq: 12 MHz */ -+#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */ ++#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */ +#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_CPU_SPEED + +#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */ @@ -13674,16 +12326,15 @@ index 0000000..68a2e87 +#define CONFIG_SYS_NO_FLASH 1 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL) -+#define CONFIG_BOOTDELAY 5 -+#define CONFIG_BOOTFILE "uImage" /* file to load */ -+#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw" -+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" -+#define CONFIG_AUTOLOAD "n" /* No autoload */ ++#define CONFIG_BOOTDELAY 0 ++#define CONFIG_BOOTFILE "uImage" /* file to load */ ++#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 rootfstype=jffs2 root=/dev/mtdblock2 rw rootwait" ++#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x300000;bootm" + -+#define CONFIG_DRIVER_CS8900 1 -+#define CS8900_BASE (0xa8000000) ++#define CONFIG_DRIVER_CS8900 1 ++#define CS8900_BASE (0xa8000000) +#define CS8900_BUS16 -+#define CONFIG_ETHADDR 00:2a:cc:2a:af:fe /* Ethernet address */ ++#define CONFIG_ETHADDR 00:2a:cc:2a:af:fe /* Ethernet address */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE @@ -13720,10 +12371,10 @@ index 0000000..68a2e87 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + -+#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */ ++#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START 0x80100000 -+#define CONFIG_SYS_MEMTEST_END 0x80800000 ++#define CONFIG_SYS_MEMTEST_END 0x80800000 + +#define CONFIG_RX_ETH_BUFFER 16 /* use 16 rx buffers on jz47xx eth */ + @@ -13735,17 +12386,23 @@ index 0000000..68a2e87 +/* + * NAND FLASH configuration + */ -+#define CONFIG_NAND_PAGE_SIZE 2048 -+#define CONFIG_NAND_BLOCK_SIZE (256 << 10) /* NAND chip block size */ -+#define CONFIG_NAND_BADBLOCK_PAGE 127 -+/* NAND bad block was marked at this page in a block, starting from 0 */ -+#define CONFIG_NAND_ECC_POS 6 -+/* Ecc offset position in oob area, default value is 6 if it isn't defined. */ ++#define QI_LB60_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1 ++ * if board nand flash is 2GB, set to 2 ++ * for change the PAGE_SIZE and BLOCK_SIZE ++ * will delete when there is no 1GB flash ++ */ + ++#define CONFIG_NAND_PAGE_SIZE (2048 * QI_LB60_NAND_SIZE) ++/* nand chip block size */ ++#define CONFIG_NAND_BLOCK_SIZE (256 * QI_LB60_NAND_SIZE << 10) ++/* nand bad block was marked at this page in a block, start from 0 */ ++#define CONFIG_NAND_BADBLOCK_PAGE 127 ++/* ECC offset position in oob area, default value is 6 if it isn't defined */ ++#define CONFIG_NAND_ECC_POS (6 * QI_LB60_NAND_SIZE) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xB8000000 -+#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips*/ ++#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/ +#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE + +/* @@ -13778,25 +12435,8 @@ index 0000000..68a2e87 +/* environment starts here */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) + -+/* -+ * NOR FLASH and environment organization -+ */ -+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -+#define CONFIG_SYS_MAX_FLASH_SECT (128)/* max number of sectors on one chip */ -+ -+#define PHYS_FLASH_1 0xa8000000 /* Flash Bank #1 */ -+ -+/* The following #defines are needed to get flash environment right */ -+/* in pi/config.mk TEXT_BAS=0x88000000 */ ++/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -+/* Reserve 256 kB for Monitor*/ -+#define CONFIG_MONITOR_LEN (256*1024) -+ -+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -+ -+/* timeout values are in ticks */ -+#define CONFIG_FLASH_ERASE_TOUT (2 * CONFIG_HZ) /* Timeout for Flash Erase */ -+#define CONFIG_FLASH_WRITE_TOUT (2 * CONFIG_HZ) /* Timeout for Flash Write */ + +/* + * SDRAM Info. @@ -13829,7 +12469,7 @@ index 0000000..68a2e87 + */ +#define GPIO_LCD_CS (2 * 32 + 21) +#define GPIO_DISP_OFF_N (3 * 32 + 21) -+#define GPIO_PWM 123 ++#define GPIO_PWM (3 * 32 + 27) + +#define GPIO_AMP_EN (3 * 32 + 4) + @@ -13848,1781 +12488,8 @@ index 0000000..68a2e87 + +#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ +#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ -+/*#define GPIO_SD_WP 112 SD Card wirte protect */ + +#endif /* __CONFIG_H */ -diff --git a/include/lcd.h b/include/lcd.h -index f054cac..cc5d620 100644 ---- a/include/lcd.h -+++ b/include/lcd.h -@@ -175,8 +175,44 @@ typedef struct vidinfo { - - extern vidinfo_t panel_info; - --#else -+#elif defined(CONFIG_JZSOC) -+/* -+ * LCD controller stucture for JZSOC: JZ4730 JZ4740 -+ */ -+struct jz_fb_dma_descriptor { -+ u_long fdadr; /* Frame descriptor address register */ -+ u_long fsadr; /* Frame source address register */ -+ u_long fidr; /* Frame ID register */ -+ u_long ldcmd; /* Command register */ -+}; -+ -+/* -+ * Jz LCD info -+ */ -+struct jz_fb_info { -+ -+ u_long fdadr0; /* physical address of frame/palette descriptor */ -+ u_long fdadr1; /* physical address of frame descriptor */ -+ -+ /* DMA descriptors */ -+ struct jz_fb_dma_descriptor * dmadesc_fblow; -+ struct jz_fb_dma_descriptor * dmadesc_fbhigh; -+ struct jz_fb_dma_descriptor * dmadesc_palette; -+ u_long screen; /* address of frame buffer */ -+ u_long palette; /* address of palette memory */ -+ u_int palette_size; -+}; -+typedef struct vidinfo { -+ ushort vl_col; /* Number of columns (i.e. 640) */ -+ ushort vl_row; /* Number of rows (i.e. 480) */ -+ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ -+ -+ struct jz_fb_info jz_fb; -+} vidinfo_t; -+ -+extern vidinfo_t panel_info; - -+#else - typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 160) */ - ushort vl_row; /* Number of rows (i.e. 100) */ -@@ -188,7 +224,7 @@ typedef struct vidinfo { - void *priv; /* Pointer to driver-specific data */ - } vidinfo_t; - --#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */ -+#endif /* CONFIG_MPC823, CONFIG_PXA250, CONFIG_MCC200 or CONFIG_JZ4740 */ - - /* Video functions */ - -@@ -226,6 +262,7 @@ void lcd_show_board_info(void); - #define LCD_COLOR4 2 - #define LCD_COLOR8 3 - #define LCD_COLOR16 4 -+#define LCD_COLOR32 5 - - /*----------------------------------------------------------------------*/ - #if defined(CONFIG_LCD_INFO_BELOW_LOGO) -@@ -277,13 +314,22 @@ void lcd_show_board_info(void); - # define CONSOLE_COLOR_GREY 14 - # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ - --#else -+#elif LCD_BPP == LCD_COLOR16 - - /* - * 16bpp color definitions - */ - # define CONSOLE_COLOR_BLACK 0x0000 --# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ -+# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ -+ -+#elif LCD_BPP == LCD_COLOR32 -+/* -+ * 18,24,32 bpp color definitions -+ */ -+# define CONSOLE_COLOR_BLACK 0x00000000 -+# define CONSOLE_COLOR_WHITE 0xffffffff /* Must remain last / highest */ -+ -+#else - - #endif /* color definitions */ - -@@ -315,11 +361,16 @@ void lcd_show_board_info(void); - # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ - (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) - #elif LCD_BPP == LCD_COLOR8 --# define COLOR_MASK(c) (c) -+# define COLOR_MASK(c) (c) -+#elif LCD_BPP == LCD_COLOR16 -+# define COLOR_MASK(c) (c) -+#elif LCD_BPP == LCD_COLOR32 -+# define COLOR_MASK(c) (c) - #else - # error Unsupported LCD BPP. - #endif - -+ - /************************************************************************/ - - #endif /* _LCD_H_ */ -diff --git a/lib_mips/board.c b/lib_mips/board.c -index f8ac234..539f78f 100644 ---- a/lib_mips/board.c -+++ b/lib_mips/board.c -@@ -45,6 +45,10 @@ DECLARE_GLOBAL_DATA_PTR; - - #undef DEBUG - -+#if defined(CONFIG_JZSOC) -+extern int jz_board_init(void); -+#endif -+ - extern int timer_init(void); - - extern int incaip_set_cpuclk(void); -@@ -109,7 +113,6 @@ void *sbrk (ptrdiff_t increment) - return ((void *) old); - } - -- - static int init_func_ram (void) - { - #ifdef CONFIG_BOARD_TYPES -@@ -129,7 +132,6 @@ static int init_func_ram (void) - - static int display_banner(void) - { -- - printf ("\n\n%s\n\n", version_string); - return (0); - } -@@ -178,6 +180,9 @@ static int init_baudrate (void) - typedef int (init_fnc_t) (void); - - init_fnc_t *init_sequence[] = { -+#if defined(CONFIG_JZSOC) -+ jz_board_init, /* init gpio/clocks/dram etc. */ -+#endif - board_early_init_f, - timer_init, - env_init, /* initialize environment */ -@@ -193,7 +198,6 @@ init_fnc_t *init_sequence[] = { - NULL, - }; - -- - void board_init_f(ulong bootflag) - { - gd_t gd_data, *id; -@@ -233,6 +237,12 @@ void board_init_f(ulong bootflag) - addr &= ~(4096 - 1); - debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); - -+#ifdef CONFIG_LCD -+ /* reserve memory for LCD display (always full pages) */ -+ addr = lcd_setmem (addr); -+ gd->fb_base = addr; -+#endif /* CONFIG_LCD */ -+ - /* Reserve memory for U-Boot code, data & bss - * round down to next 16 kB limit - */ -diff --git a/lib_mips/time.c b/lib_mips/time.c -index 07e356d..4654bf4 100644 ---- a/lib_mips/time.c -+++ b/lib_mips/time.c -@@ -24,6 +24,8 @@ - #include - #include - -+#ifndef CONFIG_JzRISC -+ - static unsigned long timestamp; - - /* how many counter cycles in a jiffy */ -@@ -96,3 +98,5 @@ ulong get_tbclk(void) - { - return CONFIG_SYS_HZ; - } -+ -+#endif /* !CONFIG_JzRISC */ -diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile -deleted file mode 100644 -index 931f04b..0000000 ---- a/nand_spl/board/amcc/acadia/Makefile -+++ /dev/null -@@ -1,118 +0,0 @@ --# --# (C) Copyright 2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# -- --include $(TOPDIR)/config.mk --include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk -- --LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds --LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --AFLAGS += -DCONFIG_NAND_SPL --CFLAGS += -DCONFIG_NAND_SPL -- --SOBJS = start.o resetvec.o cache.o --COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o -- --SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) --OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) --__OBJS := $(SOBJS) $(COBJS) --LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) -- --nandobj := $(OBJTREE)/nand_spl/ -- --ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ -- $(nandobj)System.map -- --all: $(obj).depend $(ALL) -- --$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ -- --$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- --$(nandobj)u-boot-spl: $(OBJS) -- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -- -Map $(nandobj)u-boot-spl.map \ -- -o $(nandobj)u-boot-spl -- --$(nandobj)System.map: $(nandobj)u-boot-spl -- @$(NM) $< | \ -- grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ -- sort > $(nandobj)System.map -- --# create symbolic links for common files -- --# from cpu directory --$(obj)cache.S: -- @rm -f $(obj)cache.S -- ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S -- --$(obj)gpio.c: -- @rm -f $(obj)gpio.c -- ln -s $(SRCTREE)/cpu/ppc4xx/gpio.c $(obj)gpio.c -- --$(obj)ndfc.c: -- @rm -f $(obj)ndfc.c -- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c -- --$(obj)resetvec.S: -- @rm -f $(obj)resetvec.S -- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S -- --$(obj)start.S: -- @rm -f $(obj)start.S -- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S -- --# from board directory --$(obj)memory.c: -- @rm -f $(obj)memory.c -- ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c -- --$(obj)pll.c: -- @rm -f $(obj)pll.c -- ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c -- --# from nand_spl directory --$(obj)nand_boot.c: -- @rm -f $(obj)nand_boot.c -- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c -- --# from drivers/mtd/nand directory --$(obj)nand_ecc.c: -- @rm -f $(obj)nand_ecc.c -- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c -- --######################################################################### -- --$(obj)%.o: $(obj)%.S -- $(CC) $(AFLAGS) -c -o $@ $< -- --$(obj)%.o: $(obj)%.c -- $(CC) $(CFLAGS) -c -o $@ $< -- --# defines $(obj).depend target --include $(SRCTREE)/rules.mk -- --sinclude $(obj).depend -- --######################################################################### -diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk -deleted file mode 100644 -index fcc838a..0000000 ---- a/nand_spl/board/amcc/acadia/config.mk -+++ /dev/null -@@ -1,47 +0,0 @@ --# --# (C) Copyright 2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# --# --# AMCC 405EZ Reference Platform (Acadia) board --# -- --# --# TEXT_BASE for SPL: --# --# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, --# in the last 4kBytes of memory space in cache. --# We will copy this SPL into internal SRAM in start.S. So we set --# TEXT_BASE to starting address in internal SRAM here. --# --TEXT_BASE = 0xf8004000 -- --# PAD_TO used to generate a 16kByte binary needed for the combined image --# -> PAD_TO = TEXT_BASE + 0x4000 --PAD_TO = 0xf8008000 -- --ifeq ($(debug),1) --PLATFORM_CPPFLAGS += -DDEBUG --endif -- --ifeq ($(dbcr),1) --PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 --endif -diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds -deleted file mode 100644 -index b89cd80..0000000 ---- a/nand_spl/board/amcc/acadia/u-boot.lds -+++ /dev/null -@@ -1,64 +0,0 @@ --/* -- * (C) Copyright 2007 -- * Stefan Roese, DENX Software Engineering, sr@denx.de. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --OUTPUT_ARCH(powerpc:common) --SECTIONS --{ -- .resetvec 0xf8004ffc : -- { -- *(.resetvec) -- } = 0xffff -- -- .text : -- { -- start.o (.text) -- nand_boot.o (.text) -- ndfc.o (.text) -- -- *(.text) -- *(.fixup) -- } -- _etext = .; -- -- .data : -- { -- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -- *(.data*) -- *(.sdata*) -- __got2_start = .; -- *(.got2) -- __got2_end = .; -- } -- -- _edata = .; -- -- __bss_start = .; -- .bss (NOLOAD) : -- { -- *(.sbss) -- *(.bss) -- . = ALIGN(4); -- } -- -- _end = . ; --} -diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile -deleted file mode 100644 -index e1c1467..0000000 ---- a/nand_spl/board/amcc/bamboo/Makefile -+++ /dev/null -@@ -1,106 +0,0 @@ --# --# (C) Copyright 2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# -- --include $(TOPDIR)/config.mk --include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk -- --LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds --LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --AFLAGS += -DCONFIG_NAND_SPL --CFLAGS += -DCONFIG_NAND_SPL -- --SOBJS = start.o init.o resetvec.o --COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o -- --SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) --OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) --__OBJS := $(SOBJS) $(COBJS) --LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) -- --nandobj := $(OBJTREE)/nand_spl/ -- --ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin -- --all: $(obj).depend $(ALL) -- --$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ -- --$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- --$(nandobj)u-boot-spl: $(OBJS) -- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -- -Map $(nandobj)u-boot-spl.map \ -- -o $(nandobj)u-boot-spl -- --# create symbolic links for common files -- --# from cpu directory --$(obj)ndfc.c: -- @rm -f $(obj)ndfc.c -- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c -- --$(obj)resetvec.S: -- @rm -f $(obj)resetvec.S -- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S -- --$(obj)start.S: -- @rm -f $(obj)start.S -- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S -- --# from board directory --$(obj)init.S: -- @rm -f $(obj)init.S -- ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S -- --# from nand_spl directory --$(obj)nand_boot.c: -- @rm -f $(obj)nand_boot.c -- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c -- --# from drivers/mtd/nand directory --$(obj)nand_ecc.c: -- @rm -f $(obj)nand_ecc.c -- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c -- --ifneq ($(OBJTREE), $(SRCTREE)) --$(obj)sdram.c: -- @rm -f $(obj)sdram.c -- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c --endif -- --######################################################################### -- --$(obj)%.o: $(obj)%.S -- $(CC) $(AFLAGS) -c -o $@ $< -- --$(obj)%.o: $(obj)%.c -- $(CC) $(CFLAGS) -c -o $@ $< -- --# defines $(obj).depend target --include $(SRCTREE)/rules.mk -- --sinclude $(obj).depend -- --######################################################################### -diff --git a/nand_spl/board/amcc/bamboo/config.mk b/nand_spl/board/amcc/bamboo/config.mk -deleted file mode 100644 -index 6377b52..0000000 ---- a/nand_spl/board/amcc/bamboo/config.mk -+++ /dev/null -@@ -1,49 +0,0 @@ --# --# (C) Copyright 2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# --# --# AMCC 440EP Reference Platform (Bamboo) board --# -- --# --# TEXT_BASE for SPL: --# --# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, --# in the last 4kBytes of memory space in cache. --# We will copy this SPL into instruction-cache in start.S. So we set --# TEXT_BASE to starting address in i-cache here. --# --TEXT_BASE = 0x00800000 -- --# PAD_TO used to generate a 16kByte binary needed for the combined image --# -> PAD_TO = TEXT_BASE + 0x4000 --PAD_TO = 0x00804000 -- --PLATFORM_CPPFLAGS += -DCONFIG_440=1 -- --ifeq ($(debug),1) --PLATFORM_CPPFLAGS += -DDEBUG --endif -- --ifeq ($(dbcr),1) --PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 --endif -diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c -deleted file mode 100644 -index 54be256..0000000 ---- a/nand_spl/board/amcc/bamboo/sdram.c -+++ /dev/null -@@ -1,92 +0,0 @@ --/* -- * (C) Copyright 2007 -- * Stefan Roese, DENX Software Engineering, sr@denx.de. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --#include --#include --#include --#include -- --static void wait_init_complete(void) --{ -- u32 val; -- -- do { -- mfsdram(mem_mcsts, val); -- } while (!(val & 0x80000000)); --} -- --/* -- * phys_size_t initdram(int board_type) -- * -- * As the name already indicates, this function is called very early -- * from start.S and configures the SDRAM with fixed values. This is needed, -- * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has -- * not enough free space to implement the complete I2C SPD DDR autodetection -- * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM -- * when booting from NAND flash. -- * -- * Note: -- * As found out by Eugene O'Brien , the fixed -- * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM -- * modules are still plugged in. So it is recommended to remove the DIMM -- * modules while using the NAND booting code with the fixed SDRAM setup! -- */ --phys_size_t initdram(int board_type) --{ -- /* -- * Soft-reset SDRAM controller. -- */ -- mtsdr(sdr_srst, SDR0_SRST_DMC); -- mtsdr(sdr_srst, 0x00000000); -- -- /* -- * Disable memory controller. -- */ -- mtsdram(mem_cfg0, 0x00000000); -- -- /* -- * Setup some default -- */ -- mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ -- mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ -- mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ -- mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ -- mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ -- -- /* -- * Following for CAS Latency = 2.5 @ 133 MHz PLB -- */ -- mtsdram(mem_b0cr, 0x00082001); -- mtsdram(mem_tr0, 0x41094012); -- mtsdram(mem_tr1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ -- mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ -- mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ -- -- /* -- * Enable the controller, then wait for DCEN to complete -- */ -- mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/ -- wait_init_complete(); -- -- return CONFIG_SYS_MBYTES_SDRAM << 20; --} -diff --git a/nand_spl/board/amcc/bamboo/u-boot.lds b/nand_spl/board/amcc/bamboo/u-boot.lds -deleted file mode 100644 -index d171269..0000000 ---- a/nand_spl/board/amcc/bamboo/u-boot.lds -+++ /dev/null -@@ -1,66 +0,0 @@ --/* -- * (C) Copyright 2007 -- * Stefan Roese, DENX Software Engineering, sr@denx.de. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --OUTPUT_ARCH(powerpc:common) --SECTIONS --{ -- .resetvec 0x00800FFC : -- { -- *(.resetvec) -- } = 0xffff -- -- .text : -- { -- start.o (.text) -- init.o (.text) -- nand_boot.o (.text) -- sdram.o (.text) -- ndfc.o (.text) -- -- *(.text) -- *(.fixup) -- } -- _etext = .; -- -- .data : -- { -- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -- *(.data*) -- *(.sdata*) -- __got2_start = .; -- *(.got2) -- __got2_end = .; -- } -- -- _edata = .; -- -- __bss_start = .; -- .bss (NOLOAD) : -- { -- *(.sbss) -- *(.bss) -- . = ALIGN(4); -- } -- -- _end = . ; --} -diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile -deleted file mode 100644 -index fb86752..0000000 ---- a/nand_spl/board/amcc/canyonlands/Makefile -+++ /dev/null -@@ -1,111 +0,0 @@ --# --# (C) Copyright 2008 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# -- --include $(TOPDIR)/config.mk --include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk -- --LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds --LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --AFLAGS += -DCONFIG_NAND_SPL --CFLAGS += -DCONFIG_NAND_SPL -- --SOBJS := start.o --SOBJS += init.o --SOBJS += resetvec.o --COBJS := ddr2_fixed.o --COBJS += nand_boot.o --COBJS += nand_ecc.o --COBJS += ndfc.o -- --SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) --OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) --__OBJS := $(SOBJS) $(COBJS) --LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) -- --nandobj := $(OBJTREE)/nand_spl/ -- --ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin -- --all: $(obj).depend $(ALL) -- --$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ -- --$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- --$(nandobj)u-boot-spl: $(OBJS) -- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -- -Map $(nandobj)u-boot-spl.map \ -- -o $(nandobj)u-boot-spl -- --# create symbolic links for common files -- --# from cpu directory --$(obj)ndfc.c: -- @rm -f $(obj)ndfc.c -- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c -- --$(obj)resetvec.S: -- @rm -f $(obj)resetvec.S -- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S -- --$(obj)start.S: -- @rm -f $(obj)start.S -- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S -- --# from board directory --$(obj)init.S: -- @rm -f $(obj)init.S -- ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $(obj)init.S -- --# from nand_spl directory --$(obj)nand_boot.c: -- @rm -f $(obj)nand_boot.c -- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c -- --# from drivers/mtd/nand directory --$(obj)nand_ecc.c: -- @rm -f $(obj)nand_ecc.c -- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c -- --ifneq ($(OBJTREE), $(SRCTREE)) --$(obj)ddr2_fixed.c: -- @rm -f $(obj)ddr2_fixed.c -- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $(obj)ddr2_fixed.c --endif -- --######################################################################### -- --$(obj)%.o: $(obj)%.S -- $(CC) $(AFLAGS) -c -o $@ $< -- --$(obj)%.o: $(obj)%.c -- $(CC) $(CFLAGS) -c -o $@ $< -- --# defines $(obj).depend target --include $(SRCTREE)/rules.mk -- --sinclude $(obj).depend -- --######################################################################### -diff --git a/nand_spl/board/amcc/canyonlands/config.mk b/nand_spl/board/amcc/canyonlands/config.mk -deleted file mode 100644 -index 688c92b..0000000 ---- a/nand_spl/board/amcc/canyonlands/config.mk -+++ /dev/null -@@ -1,49 +0,0 @@ --# --# (C) Copyright 2008 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# --# --# AMCC 460EX Reference Platform (Canyonlands) board --# -- --# --# TEXT_BASE for SPL: --# --# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff, --# in the last 4kBytes of memory space in cache. --# We will copy this SPL into internal SRAM in start.S. So we set --# TEXT_BASE to starting address in internal SRAM here. --# --TEXT_BASE = 0xE3003000 -- --# PAD_TO used to generate a 128kByte binary needed for the combined image --# -> PAD_TO = TEXT_BASE + 0x20000 --PAD_TO = 0xE3023000 -- --PLATFORM_CPPFLAGS += -DCONFIG_440=1 -- --ifeq ($(debug),1) --PLATFORM_CPPFLAGS += -DDEBUG --endif -- --ifeq ($(dbcr),1) --PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 --endif -diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c -deleted file mode 100644 -index 371bbb3..0000000 ---- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c -+++ /dev/null -@@ -1,98 +0,0 @@ --/* -- * (C) Copyright 2008 -- * Stefan Roese, DENX Software Engineering, sr@denx.de. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --#include --#include --#include --#include -- --static void wait_init_complete(void) --{ -- u32 val; -- -- do { -- mfsdram(SDRAM_MCSTAT, val); -- } while (!(val & 0x80000000)); --} -- --phys_size_t initdram(int board_type) --{ -- /* -- * Reset the DDR-SDRAM controller. -- */ -- mtsdr(SDR0_SRST, (0x80000000 >> 10)); -- mtsdr(SDR0_SRST, 0x00000000); -- -- /* -- * These values are cloned from a running NOR booting -- * Canyonlands with SPD-DDR2 detection and calibration -- * enabled. This will only work for the same memory -- * configuration as used here: -- * -- * Crucial CT6464AC667.8FB - 512MB SO-DIMM -- * -- */ -- mtsdram(SDRAM_MCOPT2, 0x00000000); -- mtsdram(SDRAM_MCOPT1, 0x05122000); -- mtsdram(SDRAM_MODT0, 0x01000000); -- mtsdram(SDRAM_CODT, 0x02800021); -- mtsdram(SDRAM_WRDTR, 0x82000823); -- mtsdram(SDRAM_CLKTR, 0x40000000); -- mtsdram(SDRAM_MB0CF, 0x00000201); -- mtsdram(SDRAM_MB1CF, 0x00000201); -- mtsdram(SDRAM_RTR, 0x06180000); -- mtsdram(SDRAM_SDTR1, 0x80201000); -- mtsdram(SDRAM_SDTR2, 0x42103243); -- mtsdram(SDRAM_SDTR3, 0x0A0D0D16); -- mtsdram(SDRAM_MMODE, 0x00000632); -- mtsdram(SDRAM_MEMODE, 0x00000040); -- mtsdram(SDRAM_INITPLR0, 0xB5380000); -- mtsdram(SDRAM_INITPLR1, 0x82100400); -- mtsdram(SDRAM_INITPLR2, 0x80820000); -- mtsdram(SDRAM_INITPLR3, 0x80830000); -- mtsdram(SDRAM_INITPLR4, 0x80810040); -- mtsdram(SDRAM_INITPLR5, 0x80800532); -- mtsdram(SDRAM_INITPLR6, 0x82100400); -- mtsdram(SDRAM_INITPLR7, 0x8A080000); -- mtsdram(SDRAM_INITPLR8, 0x8A080000); -- mtsdram(SDRAM_INITPLR9, 0x8A080000); -- mtsdram(SDRAM_INITPLR10, 0x8A080000); -- mtsdram(SDRAM_INITPLR11, 0x80000432); -- mtsdram(SDRAM_INITPLR12, 0x808103C0); -- mtsdram(SDRAM_INITPLR13, 0x80810040); -- mtsdram(SDRAM_INITPLR14, 0x00000000); -- mtsdram(SDRAM_INITPLR15, 0x00000000); -- -- mtsdram(SDRAM_MCOPT2, 0x28000000); -- -- wait_init_complete(); -- -- mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ -- mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */ -- -- mtsdram(SDRAM_RDCC, 0x40000000); -- mtsdram(SDRAM_RQDC, 0x80000038); -- mtsdram(SDRAM_RFDC, 0x00000257); -- -- return CONFIG_SYS_MBYTES_SDRAM << 20; --} -diff --git a/nand_spl/board/amcc/canyonlands/u-boot.lds b/nand_spl/board/amcc/canyonlands/u-boot.lds -deleted file mode 100644 -index e676e0c..0000000 ---- a/nand_spl/board/amcc/canyonlands/u-boot.lds -+++ /dev/null -@@ -1,66 +0,0 @@ --/* -- * (C) Copyright 2008 -- * Stefan Roese, DENX Software Engineering, sr@denx.de. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --OUTPUT_ARCH(powerpc:common) --SECTIONS --{ -- .resetvec 0xE3003FFC : -- { -- *(.resetvec) -- } = 0xffff -- -- .text : -- { -- start.o (.text) -- init.o (.text) -- nand_boot.o (.text) -- ddr2_fixed.o (.text) -- ndfc.o (.text) -- -- *(.text) -- *(.fixup) -- } -- _etext = .; -- -- .data : -- { -- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -- *(.data*) -- *(.sdata*) -- __got2_start = .; -- *(.got2) -- __got2_end = .; -- } -- -- _edata = .; -- -- __bss_start = .; -- .bss (NOLOAD) : -- { -- *(.sbss) -- *(.bss) -- . = ALIGN(4); -- } -- -- _end = . ; --} -diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile -deleted file mode 100644 -index cedc8e0..0000000 ---- a/nand_spl/board/amcc/kilauea/Makefile -+++ /dev/null -@@ -1,107 +0,0 @@ --# --# (C) Copyright 2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# -- --include $(TOPDIR)/config.mk --include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk -- --LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds --LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --AFLAGS += -DCONFIG_NAND_SPL --CFLAGS += -DCONFIG_NAND_SPL -- --SOBJS = start.o resetvec.o cache.o --COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o -- --SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) --OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) --__OBJS := $(SOBJS) $(COBJS) --LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) -- --nandobj := $(OBJTREE)/nand_spl/ -- --ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin -- --all: $(obj).depend $(ALL) -- --$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ -- --$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- --$(nandobj)u-boot-spl: $(OBJS) -- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -- -Map $(nandobj)u-boot-spl.map \ -- -o $(nandobj)u-boot-spl -- --# create symbolic links for common files -- --# from cpu directory --$(obj)44x_spd_ddr2.c: $(obj)ecc.h -- @rm -f $(obj)44x_spd_ddr2.c -- ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c -- --$(obj)cache.S: -- @rm -f $(obj)cache.S -- ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S -- --$(obj)ecc.h: -- @rm -f $(obj)ecc.h -- ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h -- --$(obj)ndfc.c: -- @rm -f $(obj)ndfc.c -- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c -- --$(obj)resetvec.S: -- @rm -f $(obj)resetvec.S -- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S -- --$(obj)start.S: -- @rm -f $(obj)start.S -- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S -- --# from nand_spl directory --$(obj)nand_boot.c: -- @rm -f $(obj)nand_boot.c -- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c -- --# from drivers/nand directory --$(obj)nand_ecc.c: -- @rm -f $(obj)nand_ecc.c -- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c -- --######################################################################### -- --$(obj)%.o: $(obj)%.S -- $(CC) $(AFLAGS) -c -o $@ $< -- --$(obj)%.o: $(obj)%.c -- $(CC) $(CFLAGS) -c -o $@ $< -- --# defines $(obj).depend target --include $(SRCTREE)/rules.mk -- --sinclude $(obj).depend -- --######################################################################### -diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk -deleted file mode 100644 -index f6bcd21..0000000 ---- a/nand_spl/board/amcc/kilauea/config.mk -+++ /dev/null -@@ -1,48 +0,0 @@ --# --# (C) Copyright 2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# --# --# AMCC 405EX Reference Platform (Kilauea) board --# -- --# --# TEXT_BASE for SPL: --# --# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, --# in the last 4kBytes of memory space in cache. --# We will copy this SPL into SDRAM since we can't access the NAND --# controller at CS0 while running from this location. So we set --# TEXT_BASE to starting address in SDRAM here. --# --TEXT_BASE = 0x00800000 -- --# PAD_TO used to generate a 16kByte binary needed for the combined image --# -> PAD_TO = TEXT_BASE + 0x4000 --PAD_TO = 0x00804000 -- --ifeq ($(debug),1) --PLATFORM_CPPFLAGS += -DDEBUG --endif -- --ifeq ($(dbcr),1) --PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 --endif -diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds -deleted file mode 100644 -index 5a586fc..0000000 ---- a/nand_spl/board/amcc/kilauea/u-boot.lds -+++ /dev/null -@@ -1,64 +0,0 @@ --/* -- * (C) Copyright 2007 -- * Stefan Roese, DENX Software Engineering, sr@denx.de. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --OUTPUT_ARCH(powerpc:common) --SECTIONS --{ -- .resetvec 0x00800FFC : -- { -- *(.resetvec) -- } = 0xffff -- -- .text : -- { -- start.o (.text) -- nand_boot.o (.text) -- ndfc.o (.text) -- -- *(.text) -- *(.fixup) -- } -- _etext = .; -- -- .data : -- { -- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -- *(.data*) -- *(.sdata*) -- __got2_start = .; -- *(.got2) -- __got2_end = .; -- } -- -- _edata = .; -- -- __bss_start = .; -- .bss (NOLOAD) : -- { -- *(.sbss) -- *(.bss) -- . = ALIGN(4); -- } -- -- _end = . ; --} -diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile -deleted file mode 100644 -index fba0322..0000000 ---- a/nand_spl/board/amcc/sequoia/Makefile -+++ /dev/null -@@ -1,110 +0,0 @@ --# --# (C) Copyright 2006-2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# -- --include $(TOPDIR)/config.mk --include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk -- --LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds --LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --AFLAGS += -DCONFIG_NAND_SPL --CFLAGS += -DCONFIG_NAND_SPL -- --SOBJS = start.o init.o resetvec.o --COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o -- --SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) --OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) --__OBJS := $(SOBJS) $(COBJS) --LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) -- --nandobj := $(OBJTREE)/nand_spl/ -- --ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin -- --all: $(obj).depend $(ALL) -- --$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ -- --$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- --$(nandobj)u-boot-spl: $(OBJS) -- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -- -Map $(nandobj)u-boot-spl.map \ -- -o $(nandobj)u-boot-spl -- --# create symbolic links for common files -- --# from cpu directory --$(obj)denali_data_eye.c: -- @rm -f $(obj)denali_data_eye.c -- ln -s $(SRCTREE)/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c -- --$(obj)ndfc.c: -- @rm -f $(obj)ndfc.c -- ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c -- --$(obj)resetvec.S: -- @rm -f $(obj)resetvec.S -- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S -- --$(obj)start.S: -- @rm -f $(obj)start.S -- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S -- --# from board directory --$(obj)init.S: -- @rm -f $(obj)init.S -- ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S -- --$(obj)sdram.c: -- @rm -f $(obj)sdram.c -- @rm -f $(obj)sdram.h -- ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c -- ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h -- --# from nand_spl directory --$(obj)nand_boot.c: -- @rm -f $(obj)nand_boot.c -- ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c -- --# from drivers/mtd/nand directory --$(obj)nand_ecc.c: -- @rm -f $(obj)nand_ecc.c -- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c -- --######################################################################### -- --$(obj)%.o: $(obj)%.S -- $(CC) $(AFLAGS) -c -o $@ $< -- --$(obj)%.o: $(obj)%.c -- $(CC) $(CFLAGS) -c -o $@ $< -- --# defines $(obj).depend target --include $(SRCTREE)/rules.mk -- --sinclude $(obj).depend -- --######################################################################### -diff --git a/nand_spl/board/amcc/sequoia/config.mk b/nand_spl/board/amcc/sequoia/config.mk -deleted file mode 100644 -index e8c6333..0000000 ---- a/nand_spl/board/amcc/sequoia/config.mk -+++ /dev/null -@@ -1,49 +0,0 @@ --# --# (C) Copyright 2006 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# --# --# AMCC 440EPx Reference Platform (Sequoia) board --# -- --# --# TEXT_BASE for SPL: --# --# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, --# in the last 4kBytes of memory space in cache. --# We will copy this SPL into internal SRAM in start.S. So we set --# TEXT_BASE to starting address in internal SRAM here. --# --TEXT_BASE = 0xE0013000 -- --# PAD_TO used to generate a 16kByte binary needed for the combined image --# -> PAD_TO = TEXT_BASE + 0x4000 --PAD_TO = 0xE0017000 -- --PLATFORM_CPPFLAGS += -DCONFIG_440=1 -- --ifeq ($(debug),1) --PLATFORM_CPPFLAGS += -DDEBUG --endif -- --ifeq ($(dbcr),1) --PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 --endif -diff --git a/nand_spl/board/amcc/sequoia/u-boot.lds b/nand_spl/board/amcc/sequoia/u-boot.lds -deleted file mode 100644 -index 1601c36..0000000 ---- a/nand_spl/board/amcc/sequoia/u-boot.lds -+++ /dev/null -@@ -1,66 +0,0 @@ --/* -- * (C) Copyright 2006 -- * Stefan Roese, DENX Software Engineering, sr@denx.de. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --OUTPUT_ARCH(powerpc:common) --SECTIONS --{ -- .resetvec 0xE0013FFC : -- { -- *(.resetvec) -- } = 0xffff -- -- .text : -- { -- start.o (.text) -- init.o (.text) -- nand_boot.o (.text) -- sdram.o (.text) -- ndfc.o (.text) -- -- *(.text) -- *(.fixup) -- } -- _etext = .; -- -- .data : -- { -- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -- *(.data*) -- *(.sdata*) -- __got2_start = .; -- *(.got2) -- __got2_end = .; -- } -- -- _edata = .; -- -- __bss_start = .; -- .bss (NOLOAD) : -- { -- *(.sbss) -- *(.bss) -- . = ALIGN(4); -- } -- -- _end = . ; --} -diff --git a/nand_spl/board/freescale/mpc8313erdb/Makefile b/nand_spl/board/freescale/mpc8313erdb/Makefile -deleted file mode 100644 -index 1a8f6ff..0000000 ---- a/nand_spl/board/freescale/mpc8313erdb/Makefile -+++ /dev/null -@@ -1,105 +0,0 @@ --# --# (C) Copyright 2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# (C) Copyright 2008 Freescale Semiconductor --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# -- --NAND_SPL := y --TEXT_BASE := 0xfff00000 --PAD_TO := 0xfff04000 -- --include $(TOPDIR)/config.mk -- --LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds --LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --AFLAGS += -DCONFIG_NAND_SPL --CFLAGS += -DCONFIG_NAND_SPL -- --SOBJS = start.o ticks.o --COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ -- time.o cache.o -- --SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) --OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) --__OBJS := $(SOBJS) $(COBJS) --LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) -- --nandobj := $(OBJTREE)/nand_spl/ -- --ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin -- --all: $(obj).depend $(ALL) -- --$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ -- --$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- --$(nandobj)u-boot-spl: $(OBJS) -- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -- -Map $(nandobj)u-boot-spl.map \ -- -o $(nandobj)u-boot-spl -- --# create symbolic links for common files -- --$(obj)start.S: -- ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S -- --$(obj)nand_boot_fsl_elbc.c: -- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ -- $(obj)nand_boot_fsl_elbc.c -- --$(obj)sdram.c: -- ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $(obj)sdram.c -- --$(obj)$(BOARD).c: -- ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $(obj)$(BOARD).c -- --$(obj)ns16550.c: -- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c -- --$(obj)nand_init.c: -- ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c -- --$(obj)cache.c: -- ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c -- --$(obj)time.c: -- ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c -- --$(obj)ticks.S: -- ln -sf $(SRCTREE)/lib_ppc/ticks.S $(obj)ticks.S -- --######################################################################### -- --$(obj)%.o: $(obj)%.S -- $(CC) $(AFLAGS) -c -o $@ $< -- --$(obj)%.o: $(obj)%.c -- $(CC) $(CFLAGS) -c -o $@ $< -- --# defines $(obj).depend target --include $(SRCTREE)/rules.mk -- --sinclude $(obj).depend -- --######################################################################### -diff --git a/nand_spl/board/freescale/mpc8313erdb/u-boot.lds b/nand_spl/board/freescale/mpc8313erdb/u-boot.lds -deleted file mode 100644 -index ad82589..0000000 ---- a/nand_spl/board/freescale/mpc8313erdb/u-boot.lds -+++ /dev/null -@@ -1,52 +0,0 @@ --/* -- * (C) Copyright 2006 -- * Wolfgang Denk, DENX Software Engineering, wd@denx.de. -- * -- * Copyright 2008 Freescale Semiconductor, Inc. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --OUTPUT_ARCH(powerpc) --SECTIONS --{ -- . = 0xfff00000; -- .text : { -- *(.text*) -- . = ALIGN(16); -- *(.eh_frame) -- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -- } -- -- . = ALIGN(8); -- .data : { -- *(.data*) -- *(.sdata*) -- _GOT2_TABLE_ = .; -- *(.got2) -- __got2_entries = (. - _GOT2_TABLE_) >> 2; -- } -- -- . = ALIGN(8); -- __bss_start = .; -- .bss (NOLOAD) : { *(.*bss) } -- _end = .; --} --ENTRY(_start) --ASSERT(_end <= 0xfff01000, "NAND bootstrap too big"); diff --git a/nand_spl/board/qi_lb60/Makefile b/nand_spl/board/qi_lb60/Makefile new file mode 100644 index 0000000..bd45379 @@ -15842,408 +12709,6 @@ index 0000000..7042388 + .bss : { *(.bss) } + uboot_end = .; +} -diff --git a/nand_spl/board/samsung/smdk6400/Makefile b/nand_spl/board/samsung/smdk6400/Makefile -deleted file mode 100644 -index ae9eb2a..0000000 ---- a/nand_spl/board/samsung/smdk6400/Makefile -+++ /dev/null -@@ -1,106 +0,0 @@ --# --# (C) Copyright 2006-2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# (C) Copyright 2008 --# Guennadi Liakhovetki, DENX Software Engineering, --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# -- --CONFIG_NAND_SPL = y -- --include $(TOPDIR)/config.mk --include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk -- --LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds --LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --AFLAGS += -DCONFIG_NAND_SPL --CFLAGS += -DCONFIG_NAND_SPL -- --SOBJS = start.o cpu_init.o lowlevel_init.o --COBJS = nand_boot.o nand_ecc.o s3c64xx.o -- --SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) --OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) --__OBJS := $(SOBJS) $(COBJS) --LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) -- --nandobj := $(OBJTREE)/nand_spl/ -- --ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin -- --all: $(obj).depend $(ALL) -- --$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ -- --$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- --$(nandobj)u-boot-spl: $(OBJS) -- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -- -Map $(nandobj)u-boot-spl.map \ -- -o $(nandobj)u-boot-spl -- --# create symbolic links for common files -- --# from cpu directory --$(obj)start.S: -- @rm -f $@ -- @ln -s $(TOPDIR)/cpu/arm1176/start.S $@ -- --# from SoC directory --$(obj)cpu_init.S: -- @rm -f $@ -- @ln -s $(TOPDIR)/cpu/arm1176/s3c64xx/cpu_init.S $@ -- --# from board directory --$(obj)lowlevel_init.S: -- @rm -f $@ -- @ln -s $(TOPDIR)/board/samsung/smdk6400/lowlevel_init.S $@ -- --# from nand_spl directory --$(obj)nand_boot.c: -- @rm -f $@ -- @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@ -- --# from drivers/mtd/nand directory --$(obj)nand_ecc.c: -- @rm -f $@ -- @ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@ -- --$(obj)s3c64xx.c: -- @rm -f $@ -- @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@ -- --######################################################################### -- --$(obj)%.o: $(obj)%.S -- $(CC) $(AFLAGS) -c -o $@ $< -- --$(obj)%.o: $(obj)%.c -- $(CC) $(CFLAGS) -c -o $@ $< -- --# defines $(obj).depend target --include $(SRCTREE)/rules.mk -- --sinclude $(obj).depend -- --######################################################################### -diff --git a/nand_spl/board/samsung/smdk6400/config.mk b/nand_spl/board/samsung/smdk6400/config.mk -deleted file mode 100644 -index 4b16230..0000000 ---- a/nand_spl/board/samsung/smdk6400/config.mk -+++ /dev/null -@@ -1,40 +0,0 @@ --# --# (C) Copyright 2006 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# --# --# Samsung S3C64xx Reference Platform (smdk6400) board -- --# TEXT_BASE for SPL: --# --# On S3C64xx platforms the SPL is located in SRAM at 0. --# --# TEXT_BASE = 0 -- --include $(TOPDIR)/board/$(BOARDDIR)/config.mk -- --# PAD_TO used to generate a 4kByte binary needed for the combined image --# -> PAD_TO = TEXT_BASE + 4096 --PAD_TO := $(shell expr $$[$(TEXT_BASE) + 4096]) -- --ifeq ($(debug),1) --PLATFORM_CPPFLAGS += -DDEBUG --endif -diff --git a/nand_spl/board/samsung/smdk6400/u-boot.lds b/nand_spl/board/samsung/smdk6400/u-boot.lds -deleted file mode 100644 -index 3ac6aa1..0000000 ---- a/nand_spl/board/samsung/smdk6400/u-boot.lds -+++ /dev/null -@@ -1,61 +0,0 @@ --/* -- * (C) Copyright 2002 -- * Gary Jennejohn, DENX Software Engineering, -- * -- * (C) Copyright 2008 -- * Guennadi Liakhovetki, DENX Software Engineering, -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") --OUTPUT_ARCH(arm) --ENTRY(_start) --SECTIONS --{ -- . = 0x00000000; -- -- . = ALIGN(4); -- .text : -- { -- start.o (.text) -- cpu_init.o (.text) -- nand_boot.o (.text) -- -- *(.text) -- } -- -- . = ALIGN(4); -- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } -- -- . = ALIGN(4); -- .data : { *(.data) } -- -- . = ALIGN(4); -- .got : { *(.got) } -- -- __u_boot_cmd_start = .; -- .u_boot_cmd : { *(.u_boot_cmd) } -- __u_boot_cmd_end = .; -- -- . = ALIGN(4); -- __bss_start = .; -- .bss : { *(.bss) . = ALIGN(4); } -- _end = .; --} -diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile -deleted file mode 100644 -index 20199c7..0000000 ---- a/nand_spl/board/sheldon/simpc8313/Makefile -+++ /dev/null -@@ -1,113 +0,0 @@ --# --# (C) Copyright 2007 --# Stefan Roese, DENX Software Engineering, sr@denx.de. --# (C) Copyright 2008 Freescale Semiconductor --# (C) Copyright Sheldon Instruments, Inc. 2008 --# --# See file CREDITS for list of people who contributed to this --# project. --# --# This program is free software; you can redistribute it and/or --# modify it under the terms of the GNU General Public License as --# published by the Free Software Foundation; either version 2 of --# the License, or (at your option) any later version. --# --# This program is distributed in the hope that it will be useful, --# but WITHOUT ANY WARRANTY; without even the implied warranty of --# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --# GNU General Public License for more details. --# --# You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 59 Temple Place, Suite 330, Boston, --# MA 02111-1307 USA --# -- --NAND_SPL := y --TEXT_BASE := 0xfff00000 -- --include $(TOPDIR)/config.mk -- --LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds --LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --AFLAGS += -DCONFIG_NAND_SPL --CFLAGS += -DCONFIG_NAND_SPL -- --SOBJS = start.o ticks.o --COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ -- time.o cache.o -- --SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) --OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) --__OBJS := $(SOBJS) $(COBJS) --LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) -- --nandobj := $(OBJTREE)/nand_spl/ -- --ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin -- --all: $(obj).depend $(ALL) -- --$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ -- --$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl -- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- --$(nandobj)u-boot-spl: $(OBJS) -- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ -- -Map $(nandobj)u-boot-spl.map \ -- -o $(nandobj)u-boot-spl -- --# create symbolic links for common files -- --$(obj)start.S: -- @rm -f $@ -- ln -s $(SRCTREE)/cpu/mpc83xx/start.S $@ -- --$(obj)nand_boot_fsl_elbc.c: -- @rm -f $@ -- ln -s $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ -- --$(obj)sdram.c: -- @rm -f $@ -- ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@ -- --$(obj)$(BOARD).c: -- @rm -f $@ -- ln -s $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@ -- --$(obj)ns16550.c: -- @rm -f $@ -- ln -s $(SRCTREE)/drivers/serial/ns16550.c $@ -- --$(obj)nand_init.c: -- @rm -f $@ -- ln -s $(SRCTREE)/cpu/mpc83xx/nand_init.c $@ -- --$(obj)cache.c: -- @rm -f $@ -- ln -s $(SRCTREE)/lib_ppc/cache.c $@ -- --$(obj)time.c: -- @rm -f $@ -- ln -s $(SRCTREE)/lib_ppc/time.c $@ -- --$(obj)ticks.S: -- @rm -f $@ -- ln -s $(SRCTREE)/lib_ppc/ticks.S $@ -- --######################################################################### -- --$(obj)%.o: $(obj)%.S -- $(CC) $(AFLAGS) -c -o $@ $< -- --$(obj)%.o: $(obj)%.c -- $(CC) $(CFLAGS) -c -o $@ $< -- --# defines $(obj).depend target --include $(SRCTREE)/rules.mk -- --sinclude $(obj).depend -- --######################################################################### -diff --git a/nand_spl/board/sheldon/simpc8313/u-boot.lds b/nand_spl/board/sheldon/simpc8313/u-boot.lds -deleted file mode 100644 -index ad82589..0000000 ---- a/nand_spl/board/sheldon/simpc8313/u-boot.lds -+++ /dev/null -@@ -1,52 +0,0 @@ --/* -- * (C) Copyright 2006 -- * Wolfgang Denk, DENX Software Engineering, wd@denx.de. -- * -- * Copyright 2008 Freescale Semiconductor, Inc. -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --OUTPUT_ARCH(powerpc) --SECTIONS --{ -- . = 0xfff00000; -- .text : { -- *(.text*) -- . = ALIGN(16); -- *(.eh_frame) -- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -- } -- -- . = ALIGN(8); -- .data : { -- *(.data*) -- *(.sdata*) -- _GOT2_TABLE_ = .; -- *(.got2) -- __got2_entries = (. - _GOT2_TABLE_) >> 2; -- } -- -- . = ALIGN(8); -- __bss_start = .; -- .bss (NOLOAD) : { *(.*bss) } -- _end = .; --} --ENTRY(_start) --ASSERT(_end <= 0xfff01000, "NAND bootstrap too big"); diff --git a/nand_spl/nand_boot_jz4740.c b/nand_spl/nand_boot_jz4740.c new file mode 100644 index 0000000..924a47a @@ -16706,3 +13171,6 @@ index 0000000..924a47a + */ + (*uboot)(); +} +-- +1.6.0.4 + diff --git a/target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch b/target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch new file mode 100644 index 000000000..112ec4f1e --- /dev/null +++ b/target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch @@ -0,0 +1,1595 @@ +From 9570fff140b889e8171a50ebe8db17e847147fcc Mon Sep 17 00:00:00 2001 +From: Xiangfu Liu +Date: Mon, 12 Oct 2009 11:28:05 +0800 +Subject: [PATCH] add xburst support + +--- + Makefile | 10 + + common/lcd.c | 44 ++++- + cpu/mips/Makefile | 5 +- + cpu/mips/cache.S | 283 ++++++++++---------------- + cpu/mips/config.mk | 6 +- + cpu/mips/cpu.c | 75 +++++++ + cpu/mips/start.S | 432 +++++++++++++++++++++++++++++++-------- + drivers/mtd/nand/nand_base.c | 87 ++++++++- + examples/standalone/mips.lds | 2 +- + include/asm-mips/addrspace.h | 2 +- + include/asm-mips/global_data.h | 9 + + include/lcd.h | 56 +++++- + lib_mips/board.c | 18 ++- + lib_mips/time.c | 4 + + 14 files changed, 745 insertions(+), 288 deletions(-) + +diff --git a/Makefile b/Makefile +index e4499d7..e492d6a 100644 +--- a/Makefile ++++ b/Makefile +@@ -3381,6 +3381,16 @@ qemu_mips_config : unconfig + @$(MKCONFIG) -a qemu-mips mips mips qemu-mips + + ######################################################################### ++## MIPS32 Jz47XX ++######################################################################### ++qi_lb60_config : unconfig ++ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h ++ @echo "Compile NAND boot image for Qi_LB60" ++ @$(MKCONFIG) -a qi_lb60 mips mips qi_lb60 ++ @echo "TEXT_BASE = 0x80100000" > $(obj)board/qi_lb60/config.tmp ++ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ++ ++######################################################################### + ## MIPS64 5Kc + ######################################################################### + +diff --git a/common/lcd.c b/common/lcd.c +index dc8fea6..a2ea260 100644 +--- a/common/lcd.c ++++ b/common/lcd.c +@@ -64,7 +64,9 @@ + #ifdef CONFIG_LCD_LOGO + # include /* Get logo data, width and height */ + # if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) +-# error Default Color Map overlaps with Logo Color Map ++# ifndef CONFIG_JzRISC /* JzRISC core */ ++# error Default Color Map overlaps with Logo Color Map ++# endif + # endif + #endif + +@@ -336,6 +338,9 @@ static void test_pattern (void) + } + #endif /* LCD_TEST_PATTERN */ + ++#ifdef CONFIG_JzRISC /* JzRISC core */ ++extern int flush_cache_all(void); ++#endif + + /************************************************************************/ + /* ** GENERIC Initialization Routines */ +@@ -398,10 +403,18 @@ static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) + test_pattern(); + #else + /* set framebuffer to background color */ ++#if LCD_BPP == LCD_COLOR32 ++ long long i; ++ int *lcdbase_p = (int *)lcd_base; ++ for(i=0;i + * +@@ -22,33 +22,21 @@ + * MA 02111-1307 USA + */ + ++ + #include +-#include ++#include + #include + #include + #include + #include + +-#define RA t8 +- +-/* +- * 16kB is the maximum size of instruction and data caches on MIPS 4K, +- * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. +- * +- * Note that the above size is the maximum size of primary cache. U-Boot +- * doesn't have L2 cache support for now. +- */ +-#define MIPS_MAX_CACHE_SIZE 0x10000 ++#ifndef CONFIG_JzRISC + +-#define INDEX_BASE CKSEG0 ++ /* 16KB is the maximum size of instruction and data caches on ++ * MIPS 4K. ++ */ ++#define MIPS_MAX_CACHE_SIZE 0x4000 + +- .macro cache_op op addr +- .set push +- .set noreorder +- .set mips3 +- cache \op, 0(\addr) +- .set pop +- .endm + + /* + * cacheop macro to automate cache operations +@@ -119,79 +107,7 @@ + #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ + icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + +- .macro f_fill64 dst, offset, val +- LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +-#if LONGSIZE == 4 +- LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) +- LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +-#endif +- .endm +- +-/* +- * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) +- */ +-LEAF(mips_init_icache) +- blez a1, 9f +- mtc0 zero, CP0_TAGLO +- /* clear tag to invalidate */ +- PTR_LI t0, INDEX_BASE +- PTR_ADDU t1, t0, a1 +-1: cache_op Index_Store_Tag_I t0 +- PTR_ADDU t0, a2 +- bne t0, t1, 1b +- /* fill once, so data field parity is correct */ +- PTR_LI t0, INDEX_BASE +-2: cache_op Fill t0 +- PTR_ADDU t0, a2 +- bne t0, t1, 2b +- /* invalidate again - prudent but not strictly neccessary */ +- PTR_LI t0, INDEX_BASE +-1: cache_op Index_Store_Tag_I t0 +- PTR_ADDU t0, a2 +- bne t0, t1, 1b +-9: jr ra +- END(mips_init_icache) +- + /* +- * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) +- */ +-LEAF(mips_init_dcache) +- blez a1, 9f +- mtc0 zero, CP0_TAGLO +- /* clear all tags */ +- PTR_LI t0, INDEX_BASE +- PTR_ADDU t1, t0, a1 +-1: cache_op Index_Store_Tag_D t0 +- PTR_ADDU t0, a2 +- bne t0, t1, 1b +- /* load from each line (in cached space) */ +- PTR_LI t0, INDEX_BASE +-2: LONG_L zero, 0(t0) +- PTR_ADDU t0, a2 +- bne t0, t1, 2b +- /* clear all tags */ +- PTR_LI t0, INDEX_BASE +-1: cache_op Index_Store_Tag_D t0 +- PTR_ADDU t0, a2 +- bne t0, t1, 1b +-9: jr ra +- END(mips_init_dcache) +- +-/******************************************************************************* +-* + * mips_cache_reset - low level initialisation of the primary caches + * + * This routine initialises the primary caches to ensure that they +@@ -204,112 +120,129 @@ LEAF(mips_init_dcache) + * a source of parity. + * + * RETURNS: N/A +-* + */ +-NESTED(mips_cache_reset, 0, ra) +- move RA, ra ++ .globl mips_cache_reset ++ .ent mips_cache_reset ++mips_cache_reset: ++ + li t2, CONFIG_SYS_ICACHE_SIZE + li t3, CONFIG_SYS_DCACHE_SIZE + li t4, CONFIG_SYS_CACHELINE_SIZE + move t5, t4 + ++ + li v0, MIPS_MAX_CACHE_SIZE + +- /* +- * Now clear that much memory starting from zero. ++ /* Now clear that much memory starting from zero. + */ +- PTR_LI a0, CKSEG1 +- PTR_ADDU a1, a0, v0 +-2: PTR_ADDIU a0, 64 +- f_fill64 a0, -64, zero +- bne a0, a1, 2b +- +- /* +- * The caches are probably in an indeterminate state, +- * so we force good parity into them by doing an +- * invalidate, load/fill, invalidate for each line. ++ ++ li a0, KSEG1 ++ addu a1, a0, v0 ++ ++2: sw zero, 0(a0) ++ sw zero, 4(a0) ++ sw zero, 8(a0) ++ sw zero, 12(a0) ++ sw zero, 16(a0) ++ sw zero, 20(a0) ++ sw zero, 24(a0) ++ sw zero, 28(a0) ++ addu a0, 32 ++ bltu a0, a1, 2b ++ ++ /* Set invalid tag. + */ + +- /* +- * Assume bottom of RAM will generate good parity for the cache. ++ mtc0 zero, CP0_TAGLO ++ ++ /* ++ * The caches are probably in an indeterminate state, ++ * so we force good parity into them by doing an ++ * invalidate, load/fill, invalidate for each line. ++ */ ++ ++ /* Assume bottom of RAM will generate good parity for the cache. + */ + +- /* +- * Initialize the I-cache first, ++ li a0, K0BASE ++ move a2, t2 # icacheSize ++ move a3, t4 # icacheLineSize ++ move a1, a2 ++ icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) ++ ++ /* To support Orion/R4600, we initialise the data cache in 3 passes. + */ +- move a1, t2 +- move a2, t4 +- PTR_LA t7, mips_init_icache +- jalr t7 + +- /* +- * then initialize D-cache. ++ /* 1: initialise dcache tags. + */ +- move a1, t3 +- move a2, t5 +- PTR_LA t7, mips_init_dcache +- jalr t7 + +- jr RA +- END(mips_cache_reset) ++ li a0, K0BASE ++ move a2, t3 # dcacheSize ++ move a3, t5 # dcacheLineSize ++ move a1, a2 ++ icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + +-/******************************************************************************* +-* +-* dcache_status - get cache status +-* +-* RETURNS: 0 - cache disabled; 1 - cache enabled +-* +-*/ +-LEAF(dcache_status) +- mfc0 t0, CP0_CONFIG +- li t1, CONF_CM_UNCACHED +- andi t0, t0, CONF_CM_CMASK +- move v0, zero +- beq t0, t1, 2f +- li v0, 1 +-2: jr ra +- END(dcache_status) +- +-/******************************************************************************* +-* ++ /* 2: fill dcache. ++ */ ++ ++ li a0, K0BASE ++ move a2, t3 # dcacheSize ++ move a3, t5 # dcacheLineSize ++ move a1, a2 ++ icacheopn(a0,a1,a2,a3,1lw,(dummy)) ++ ++ /* 3: clear dcache tags. ++ */ ++ ++ li a0, K0BASE ++ move a2, t3 # dcacheSize ++ move a3, t5 # dcacheLineSize ++ move a1, a2 ++ icacheop(a0,a1,a2,a3,Index_Store_Tag_D) ++ ++ j ra ++ .end mips_cache_reset ++ ++ ++/* ++ * dcache_status - get cache status ++ * ++ * RETURNS: 0 - cache disabled; 1 - cache enabled ++ */ ++ .globl dcache_status ++ .ent dcache_status ++dcache_status: ++ ++ mfc0 v0, CP0_CONFIG ++ andi v0, v0, 1 ++ j ra ++ ++ .end dcache_status ++ ++/* + * dcache_disable - disable cache + * + * RETURNS: N/A +-* + */ +-LEAF(dcache_disable) ++ .globl dcache_disable ++ .ent dcache_disable ++dcache_disable: ++ + mfc0 t0, CP0_CONFIG + li t1, -8 + and t0, t0, t1 + ori t0, t0, CONF_CM_UNCACHED +- mtc0 t0, CP0_CONFIG +- jr ra +- END(dcache_disable) ++ mtc0 t0, CP0_CONFIG ++ j ra + +-/******************************************************************************* +-* +-* dcache_enable - enable cache +-* +-* RETURNS: N/A +-* +-*/ +-LEAF(dcache_enable) +- mfc0 t0, CP0_CONFIG +- ori t0, CONF_CM_CMASK +- xori t0, CONF_CM_CMASK +- ori t0, CONF_CM_CACHABLE_NONCOHERENT +- mtc0 t0, CP0_CONFIG +- jr ra +- END(dcache_enable) +- +-#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS +-/******************************************************************************* +-* +-* mips_cache_lock - lock RAM area pointed to by a0 in cache. +-* +-* RETURNS: N/A +-* +-*/ ++ .end dcache_disable ++ ++ ++/* ++ * mips_cache_lock - lock RAM area pointed to by a0 in cache. ++ * ++ * RETURNS: N/A ++ */ + #if defined(CONFIG_PURPLE) + # define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2) + #else +@@ -318,14 +251,14 @@ LEAF(dcache_enable) + .globl mips_cache_lock + .ent mips_cache_lock + mips_cache_lock: +- li a1, CKSEG0 - CACHE_LOCK_SIZE ++ li a1, K0BASE - CACHE_LOCK_SIZE + addu a0, a1 + li a2, CACHE_LOCK_SIZE + li a3, CONFIG_SYS_CACHELINE_SIZE + move a1, a2 + icacheop(a0,a1,a2,a3,0x1d) + +- jr ra +- ++ j ra + .end mips_cache_lock +-#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */ ++ ++#endif /* CONFIG_JzRISC */ +diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk +index a173c54..8d27e52 100644 +--- a/cpu/mips/config.mk ++++ b/cpu/mips/config.mk +@@ -25,15 +25,15 @@ MIPSFLAGS:=$(shell \ + if [ "$v" -lt "14" ]; then \ + echo "-mcpu=4kc"; \ + else \ +- echo "-march=4kc -mtune=4kc"; \ ++ echo "-march=4kc -mtune=r4600"; \ + fi) + + ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) + ENDIANNESS = -EL + else +-ENDIANNESS = -EB ++#ENDIANNESS = -EB + endif + +-MIPSFLAGS += $(ENDIANNESS) ++MIPSFLAGS += $(ENDIANNESS) -mabicalls -mips32 -O2 + + PLATFORM_CPPFLAGS += $(MIPSFLAGS) +diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c +index d5a1604..48e1cea 100644 +--- a/cpu/mips/cpu.c ++++ b/cpu/mips/cpu.c +@@ -28,6 +28,12 @@ + #include + #include + ++#ifdef CONFIG_JZ4740 ++#include ++#endif ++ ++#if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL) ++ + #define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ +@@ -40,6 +46,19 @@ + + void __attribute__((weak)) _machine_restart(void) + { ++#ifdef CONFIG_JZ4740 ++ __wdt_select_extalclk(); ++ __wdt_select_clk_div64(); ++ __wdt_set_data(100); ++ __wdt_set_count(0); ++ __tcu_start_wdt_clock(); ++ __wdt_start(); ++ while(1); ++#endif ++#if defined(CONFIG_JzRISC) ++ void (*f)(void) = (void *) 0xbfc00000; ++ f(); ++#endif + } + + int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +@@ -110,3 +129,59 @@ int cpu_eth_init(bd_t *bis) + #endif + return 0; + } ++ ++#endif /* !CONFIG_NAND_SPL !CONFIG_MSC_SPL */ ++ ++#ifdef CONFIG_JzRISC ++void flush_icache_all(void) ++{ ++ u32 addr, t = 0; ++ ++ asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ ++ asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ ++ ++ for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; ++ addr += CONFIG_SYS_CACHELINE_SIZE) { ++ asm volatile ( ++ ".set mips3\n\t" ++ " cache %0, 0(%1)\n\t" ++ ".set mips2\n\t" ++ : ++ : "I" (Index_Store_Tag_I), "r"(addr)); ++ } ++ ++ /* invalicate btb */ ++ asm volatile ( ++ ".set mips32\n\t" ++ "mfc0 %0, $16, 7\n\t" ++ "nop\n\t" ++ "ori %0,2\n\t" ++ "mtc0 %0, $16, 7\n\t" ++ ".set mips2\n\t" ++ : ++ : "r" (t)); ++} ++ ++void flush_dcache_all(void) ++{ ++ u32 addr; ++ ++ for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; ++ addr += CONFIG_SYS_CACHELINE_SIZE) { ++ asm volatile ( ++ ".set mips3\n\t" ++ " cache %0, 0(%1)\n\t" ++ ".set mips2\n\t" ++ : ++ : "I" (Index_Writeback_Inv_D), "r"(addr)); ++ } ++ ++ asm volatile ("sync"); ++} ++ ++void flush_cache_all(void) ++{ ++ flush_dcache_all(); ++ flush_icache_all(); ++} ++#endif /* CONFIG_JzRISC */ +diff --git a/cpu/mips/start.S b/cpu/mips/start.S +index 57db589..fa6e352 100644 +--- a/cpu/mips/start.S ++++ b/cpu/mips/start.S +@@ -23,32 +23,33 @@ + */ + + #include ++#include + #include + #include ++#include ++#include + +- /* +- * For the moment disable interrupts, mark the kernel mode and +- * set ST0_KX so that the CPU does not spit fire when using +- * 64-bit addresses. +- */ +- .macro setup_c0_status set clr +- .set push +- mfc0 t0, CP0_STATUS +- or t0, ST0_CU0 | \set | 0x1f | \clr +- xor t0, 0x1f | \clr +- mtc0 t0, CP0_STATUS +- .set noreorder +- sll zero, 3 # ehb +- .set pop +- .endm +- +- .macro setup_c0_status_reset +-#ifdef CONFIG_64BIT +- setup_c0_status ST0_KX 0 +-#else +- setup_c0_status 0 0 ++#ifdef CONFIG_JZ4730 ++#include ++#endif ++ ++#ifdef CONFIG_JZ4740 ++#include ++#endif ++ ++#ifdef CONFIG_JZ4750 ++#include ++#endif ++ ++#ifdef CONFIG_JZ4750D ++#include ++#endif ++ ++#if defined(CONFIG_JZ4750) || defined(CONFIG_JZ4750D) ++#define JZ4750_NANDBOOT_CFG0 (0x55555500 | (CFG_NAND_BW8*0xff)) ++#define JZ4750_NANDBOOT_CFG1 0x55555555 ++#define JZ4750_NANDBOOT_CFG2 ((CFG_NAND_PAGE_SIZE==2048)&0xff0000) | ((CFG_NAND_PAGE_SIZE!=512)&0xff00) | ((CFG_NAND_ROW_CYCLE==3)&0xff) + #endif +- .endm + + #define RVECENT(f,n) \ + b f; nop +@@ -61,6 +62,28 @@ + .globl _start + .text + _start: ++#if defined(CONFIG_JZ4740) ++#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) ++ .word JZ4740_NORBOOT_CFG /* fetched during NOR Boot */ ++#else ++#if defined(CONFIG_NAND_SPL) ++ .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */ ++#endif ++#endif ++#endif /* CONFIG_JZ4740 */ ++#if defined(CONFIG_JZ4750) || defined(CONFIG_JZ4750D) ++#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) ++ .word JZ4750_NORBOOT_CFG /* fetched during NOR Boot */ ++#else ++#if defined(CONFIG_NAND_SPL) && !defined(CONFIG_MSC_SPL) ++ /* First three words fetched by CPU during NAND Boot */ ++ .word JZ4750_NANDBOOT_CFG0 ++ .word JZ4750_NANDBOOT_CFG1 ++ .word JZ4750_NANDBOOT_CFG2 ++#endif ++#endif ++#endif /* CONFIG_JZ4750 || CONFIG_JZ4750D */ ++#if !defined(CONFIG_JzRISC) + RVECENT(reset,0) /* U-boot entry point */ + RVECENT(reset,1) /* software reboot */ + #if defined(CONFIG_INCA_IP) +@@ -213,7 +236,7 @@ _start: + .word 0x00000000 + .word 0x03e00008 + .word 0x00000000 +- .word 0x00000000 ++ .word 0x00000000 + /* 0xbfc00428 */ + .word 0xdc870000 + .word 0xfca70000 +@@ -224,74 +247,192 @@ _start: + .word 0x00000000 + .word 0x03e00008 + .word 0x00000000 +- .word 0x00000000 ++ .word 0x00000000 + #endif /* CONFIG_PURPLE */ + .align 4 ++#endif /* CONFIG_JzRISC */ ++ + reset: + ++#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) ++ ++#ifdef CONFIG_JZ4730 ++ ++ /* Disable interrupts */ ++ la t0, INTC_IMR ++ li t1, 0xffffffff ++ sw t1, 0(t0) ++ ++ /* ++ * Clear SCR.HGP ++ */ ++ la t0, CPM_SCR ++ lw t1, 0(t0) ++ ori t1, 0x8 ++ xori t1, 0x8 ++ sw t1, 0(t0) ++ ++ /* ++ * Set usb port0 as host ++ */ ++ la t0, HARB_HAPOR ++ lw t1, 0(t0) ++ ori t1, HARB_HAPOR_UCHSEL ++ sw t1, 0(t0) ++ ++ /* ++ * Check reset status ++ */ ++ la t0, CPM_RSTR ++ lw t1, 0(t0) ++ andi t1, 0x4 ++ bnez t1, resume_from_hibernate ++ nop ++#endif /* CONFIG_JZ4730 */ ++ ++#ifndef CONFIG_NAND_SPL + /* Clear watch registers. + */ + mtc0 zero, CP0_WATCHLO + mtc0 zero, CP0_WATCHHI ++#endif + +- /* WP(Watch Pending), SW0/1 should be cleared. */ +- mtc0 zero, CP0_CAUSE ++ /* STATUS register */ ++#ifdef CONFIG_JzRISC ++ /* ++ * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1 ++ */ ++ li t0, 0x0040FC04 ++ mtc0 t0, CP0_STATUS ++#else ++#ifdef CONFIG_TB0229 ++ li k0, ST0_CU0 ++#else ++ mfc0 k0, CP0_STATUS ++#endif ++ li k1, ~ST0_IE ++ and k0, k1 ++ mtc0 k0, CP0_STATUS ++#endif + +- setup_c0_status_reset ++ /* CAUSE register */ ++#ifdef CONFIG_JzRISC ++ /* IV=1, use the specical interrupt vector (0x200) */ ++ li t1, 0x00800000 ++ mtc0 t1, CP0_CAUSE ++#else ++ mtc0 zero, CP0_CAUSE ++#endif + ++#ifndef CONFIG_JzRISC + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE ++#endif + +-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) ++#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ ++ ++#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) + /* CONFIG0 register */ + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG +-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif + +- /* Initialize $gp. ++ /* Initialize GOT pointer. ++ */ ++ bal 1f ++ nop ++ .word _GLOBAL_OFFSET_TABLE_ ++ 1: ++ move gp, ra ++ lw t1, 0(ra) ++ move gp, t1 ++ ++#ifdef CONFIG_INCA_IP ++ /* Disable INCA-IP Watchdog. + */ +- bal 1f ++ la t9, disable_incaip_wdt ++ jalr t9 + nop +- .word _gp +-1: +- lw gp, 0(ra) ++#endif + +-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) ++/* JzRISC will init external memory in board_init_f, ++ which uses cache as stack and calls into C code. */ ++#ifndef CONFIG_JzRISC + /* Initialize any external memory. + */ +- la t9, lowlevel_init +- jalr t9 ++ la t9, lowlevel_init ++ jalr t9 + nop ++#endif + ++#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) + /* Initialize caches... + */ +- la t9, mips_cache_reset +- jalr t9 ++#ifdef CONFIG_JzRISC ++ .set mips32 ++ mtc0 zero, CP0_TAGLO ++ mtc0 zero, CP0_TAGHI ++ ++ li t0, K0BASE ++ ori t1, t0, CONFIG_SYS_DCACHE_SIZE ++1: ++ cache Index_Store_Tag_D, 0(t0) ++ bne t0, t1, 1b ++ addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE ++ ++ li t0, K0BASE ++ ori t1, t0, CONFIG_SYS_ICACHE_SIZE ++2: ++ cache Index_Store_Tag_I, 0(t0) ++ bne t0, t1, 2b ++ addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE ++ ++ /* Invalidate BTB */ ++ mfc0 t0, CP0_CONFIG, 7 ++ nop ++ ori t0, 2 ++ mtc0 t0, CP0_CONFIG, 7 + nop + ++ .set mips2 ++#else ++ la t9, mips_cache_reset ++ jalr t9 ++ nop ++#endif ++ + /* ... and enable them. + */ + li t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG +-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ ++ nop ++ ++#endif /* !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT) */ + + /* Set up temporary stack. + */ +-#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS ++#ifndef CONFIG_JzRISC + li a0, CONFIG_SYS_INIT_SP_OFFSET +- la t9, mips_cache_lock +- jalr t9 ++ la t9, mips_cache_lock ++ jalr t9 + nop + #endif + ++#ifdef CONFIG_NAND_SPL ++ la sp, 0x80004000 ++ la t9, nand_boot ++ j t9 ++ nop ++#else + li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET + la sp, 0(t0) + + la t9, board_init_f +- jr t9 ++ j t9 + nop + ++ + /* + * void relocate_code (addr_sp, gd, addr_moni) + * +@@ -305,37 +446,28 @@ reset: + .globl relocate_code + .ent relocate_code + relocate_code: +- move sp, a0 /* Set new stack pointer */ ++ move sp, a0 /* Set new stack pointer */ + +- li t0, CONFIG_SYS_MONITOR_BASE ++ li t0, TEXT_BASE + la t3, in_ram + lw t2, -12(t3) /* t2 <-- uboot_end_data */ + move t1, a2 +- move s2, a2 /* s2 <-- destination address */ + + /* +- * Fix $gp: ++ * Fix GOT pointer: + * +- * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address ++ * New GOT-PTR = (old GOT-PTR - TEXT_BASE) + Destination Address + */ + move t6, gp +- sub gp, CONFIG_SYS_MONITOR_BASE +- add gp, a2 /* gp now adjusted */ +- sub s1, gp, t6 /* s1 <-- relocation offset */ ++ sub gp, TEXT_BASE ++ add gp, a2 /* gp now adjusted */ ++ sub t6, gp, t6 /* t6 <-- relocation offset */ + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ +- +- /* +- * Save destination address and size for later usage in flush_cache() +- */ +- move s0, a1 /* save gd in s0 */ +- move a0, t1 /* a0 <-- destination addr */ +- sub a1, t2, t0 /* a1 <-- size */ +- + /* On the purple board we copy the code earlier in a special way + * in order to solve flash problems + */ +@@ -345,47 +477,61 @@ relocate_code: + sw t3, 0(t1) + addu t0, 4 + ble t0, t2, 1b +- addu t1, 4 /* delay slot */ ++ addu t1, 4 /* delay slot */ + #endif + + /* If caches were enabled, we would have to flush them here. + */ +- +- /* a0 & a1 are already set up for flush_cache(start, size) */ +- la t9, flush_cache +- jalr t9 ++#ifdef CONFIG_JzRISC ++ /* flush d-cache */ ++ .set mips32 ++ li t0, KSEG0 ++ addi t1, t0, CONFIG_SYS_DCACHE_SIZE ++2: ++ cache Index_Writeback_Inv_D, 0(t0) ++ bne t0, t1, 2b ++ addi t0, CONFIG_SYS_CACHELINE_SIZE ++ ++ sync ++ ++ /* flush i-cache */ ++ li t0, KSEG0 ++ addi t1, t0, CONFIG_SYS_ICACHE_SIZE ++3: ++ cache Index_Invalidate_I, 0(t0) ++ bne t0, t1, 3b ++ addi t0, CONFIG_SYS_CACHELINE_SIZE ++ ++ /* Invalidate BTB */ ++ mfc0 t0, CP0_CONFIG, 7 ++ nop ++ ori t0, 2 ++ mtc0 t0, CP0_CONFIG, 7 + nop + ++ .set mips0 ++#endif ++ + /* Jump to where we've relocated ourselves. + */ +- addi t0, s2, in_ram - _start +- jr t0 ++ addi t0, a2, in_ram - _start ++ j t0 + nop + +- .word _gp +- .word _GLOBAL_OFFSET_TABLE_ + .word uboot_end_data + .word uboot_end + .word num_got_entries + + in_ram: +- /* +- * Now we want to update GOT. +- * +- * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object +- * generated by GNU ld. Skip these reserved entries from relocation. ++ /* Now we want to update GOT. + */ + lw t3, -4(t0) /* t3 <-- num_got_entries */ +- lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */ +- lw t5, -20(t0) /* t5 <-- _gp */ +- sub t4, t5 /* compute offset*/ +- add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */ +- addi t4, t4, 8 /* Skipping first two entries. */ ++ addi t4, gp, 8 /* Skipping first two entries. */ + li t2, 2 + 1: + lw t1, 0(t4) + beqz t1, 2f +- add t1, s1 ++ add t1, t6 + sw t1, 0(t4) + 2: + addi t2, 1 +@@ -396,26 +542,134 @@ in_ram: + */ + lw t1, -12(t0) /* t1 <-- uboot_end_data */ + lw t2, -8(t0) /* t2 <-- uboot_end */ +- add t1, s1 /* adjust pointers */ +- add t2, s1 ++ add t1, t6 /* adjust pointers */ ++ add t2, t6 + + sub t1, 4 +-1: +- addi t1, 4 ++1: addi t1, 4 + bltl t1, t2, 1b + sw zero, 0(t1) /* delay slot */ + +- move a0, s0 /* a0 <-- gd */ ++ move a0, a1 + la t9, board_init_r +- jr t9 +- move a1, s2 /* delay slot */ ++ j t9 ++ move a1, a2 /* delay slot */ + + .end relocate_code + ++#endif /* CONFIG_NAND_SPL */ ++ ++#if !defined(CONFIG_JzRISC) + /* Exception handlers. + */ + romReserved: +- b romReserved ++ b romReserved + + romExcHandle: +- b romExcHandle ++ b romExcHandle ++#endif ++ ++#ifdef CONFIG_JZ4730 ++ ++/* These are the runtime values, modify them according to your platform. */ ++#define PLCR1_VAL 0x1b000520 ++#define CFCR_VAL 0x0c526220 ++ ++#define DMCR_VAL0 0x042a3211 ++#define DMCR_VAL1 0x05aa3211 /*(DMCR_VAL0|EMC_DMCR_RFSH|EMC_DMCR_MRSET)*/ ++ ++#define RTCOR_VAL 0x10 ++#define RTCSR_VAL 0x83 ++ ++ /* ++ * cpu was reset from hibernate mode ++ */ ++resume_from_hibernate: ++ /* ++ * Init PLL ++ */ ++ la t0, 0xB0000000 /* CFCR */ ++ li t1, CFCR_VAL ++ sw t1, 0(t0) ++ ++ la t0, 0xB0000010 /* PLCR1 */ ++ li t1, PLCR1_VAL ++ sw t1, 0(t0) ++ nop;nop;nop;nop ++ ++ /* Init caches */ ++ .set mips32 ++ mtc0 zero, CP0_TAGLO ++ mtc0 zero, CP0_TAGHI ++ ++ li t0, K0BASE ++ ori t1, t0, CONFIG_SYS_DCACHE_SIZE ++1: ++ cache Index_Store_Tag_D, 0(t0) ++ cache Index_Store_Tag_I, 0(t0) ++ bne t0, t1, 1b ++ addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE ++ ++ /* ++ * Init SDRAM ++ */ ++ la t0, 0xB0010070 /* GPALR2 */ ++ lw t1, 0(t0) ++ li t2, 0x3FFFFFFF ++ and t1, t2 ++ li t2, 0x40000000 ++ or t1, t2 ++ sw t1, 0(t0) ++ ++ la t0, 0xB0010074 /* GPAUR2 */ ++ lw t1, 0(t0) ++ li t2, 0xFFFF0000 ++ and t1, t2 ++ li t2, 0x00005555 ++ or t1, t2 ++ sw t1, 0(t0) ++ ++ la t0, 0xB3010000 /* EMC base address */ ++ ++ li t1, DMCR_VAL0 /* DMCR */ ++ sw t1, 0x80(t0) ++ ++ li t1, RTCOR_VAL ++ sh t1, 0x8c(t0) /* RTCOR */ ++ ++ li t1, RTCSR_VAL ++ sh t1, 0x84(t0) /* RTCSR */ ++ ++ /* precharge all chip-selects */ ++ ori t1, t0, 0xa088 ++ sb $0, 0(t1) ++ ori t1, t0, 0xb088 ++ sb $0, 0(t1) ++ ++ /* delay about 200us */ ++ li t1, 0x20000 ++1: ++ bnez t1, 1b ++ sub t1, 1 ++ ++ la t1, DMCR_VAL1 /* DMCR */ ++ sw t1, 0x80(t0) ++ ++ /* write sdram mode register for each chip-select */ ++ ori t1, t0, 0xa088 ++ sb $0, 0(t1) ++ ori t1, t0, 0xb088 ++ sb $0, 0(t1) ++ ++ /* ++ * jump to resume entry point ++ */ ++ la t0, CPM_SPR ++ lw t1, 0(t0) ++ li t0, 0x80000000 ++ or t0, t1 ++ ++ j t0 ++ nop ++ ++#endif /* CONFIG_JZ4730 */ +diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c +index 360b070..88717e9 100644 +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -109,6 +109,22 @@ static struct nand_ecclayout nand_oob_16 = { + . length = 8}} + }; + ++#if defined(CONFIG_JZ4740) ++static struct nand_ecclayout nand_oob_64 = { ++ .eccbytes = 36, ++ .eccpos = { ++ 6, 7, 8, 9, 10, 11, 12, 13, ++ 14, 15, 16, 17, 18, 19, 20, 21, ++ 22, 23, 24, 25, 26, 27, 28, 29, ++ 30, 31, 32, 33, 34, 35, 36, 37, ++ 38, 39, 40, 41}, ++ .oobfree ={ ++ {.offset = 2, ++ .length = 4}, ++ {.offset = 42, ++ .length = 22}} ++}; ++#else + static struct nand_ecclayout nand_oob_64 = { + .eccbytes = 24, + .eccpos = { +@@ -119,6 +135,7 @@ static struct nand_ecclayout nand_oob_64 = { + {.offset = 2, + .length = 38}} + }; ++#endif + + static struct nand_ecclayout nand_oob_128 = { + .eccbytes = 48, +@@ -1068,6 +1085,60 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + } + + /** ++ * nand_read_page_hwecc_rs - [REPLACABLE] hardware rs ecc based page read function ++ * @mtd: mtd info structure ++ * @chip: nand chip info structure ++ * @buf: buffer to store read data ++ * ++ * Not for syndrome calculating ecc controllers which need a special oob layout ++ */ ++static int nand_read_page_hwecc_rs(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf) ++{ ++ int i, eccsize = chip->ecc.size; ++ int eccbytes = chip->ecc.bytes; ++ int eccsteps = chip->ecc.steps; ++ uint8_t *p = buf; ++ uint8_t *ecc_calc = chip->buffers->ecccalc; ++ uint8_t *ecc_code = chip->buffers->ecccode; ++ uint32_t *eccpos = chip->ecc.layout->eccpos; ++ uint32_t page; ++ uint8_t flag = 0; ++ ++ page = (buf[3]<<24) + (buf[2]<<16) + (buf[1]<<8) + buf[0]; ++ ++ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); ++ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); ++ ++ for (i = 0; i < chip->ecc.total; i++) { ++ ecc_code[i] = chip->oob_poi[eccpos[i]]; ++ if (ecc_code[i] != 0xff) ++ flag = 1; ++ } ++ ++ eccsteps = chip->ecc.steps; ++ p = buf; ++ ++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0x00, -1); ++ for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { ++ int stat; ++ if (flag) { ++ chip->ecc.hwctl(mtd, NAND_ECC_READ); ++ chip->read_buf(mtd, p, eccsize); ++ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); ++ if (stat < 0) ++ mtd->ecc_stats.failed++; ++ else ++ mtd->ecc_stats.corrected += stat; ++ } ++ else { ++ chip->ecc.hwctl(mtd, NAND_ECC_READ); ++ chip->read_buf(mtd, p, eccsize); ++ } ++ } ++ return 0; ++} ++/** + * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read + * @mtd: mtd info structure + * @chip: nand chip info structure +@@ -1222,8 +1293,15 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, + ret = chip->ecc.read_page_raw(mtd, chip, bufpoi); + else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) + ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); +- else ++ else { ++#if defined(CONFIG_JZ4740) ++ bufpoi[0] = (uint8_t)page; ++ bufpoi[1] = (uint8_t)(page >> 8); ++ bufpoi[2] = (uint8_t)(page >> 16); ++ bufpoi[3] = (uint8_t)(page >> 24); ++#endif + ret = chip->ecc.read_page(mtd, chip, bufpoi); ++ } + if (ret < 0) + break; + +@@ -2730,8 +2808,13 @@ int nand_scan_tail(struct mtd_info *mtd) + switch (chip->ecc.mode) { + case NAND_ECC_HW: + /* Use standard hwecc read page function ? */ +- if (!chip->ecc.read_page) ++ if (!chip->ecc.read_page) { ++#if defined(CONFIG_JZ4740) ++ chip->ecc.read_page = nand_read_page_hwecc_rs; ++#else + chip->ecc.read_page = nand_read_page_hwecc; ++#endif ++ } + if (!chip->ecc.write_page) + chip->ecc.write_page = nand_write_page_hwecc; + if (!chip->ecc.read_oob) +diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds +index 717b201..d4a45f8 100644 +--- a/examples/standalone/mips.lds ++++ b/examples/standalone/mips.lds +@@ -23,8 +23,8 @@ + + /* + OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +-*/ + OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") ++*/ + OUTPUT_ARCH(mips) + SECTIONS + { +diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h +index 3a1e6d6..2ee6920 100644 +--- a/include/asm-mips/addrspace.h ++++ b/include/asm-mips/addrspace.h +@@ -131,7 +131,7 @@ + * Returns the uncached address of a sdram address + */ + #ifndef __ASSEMBLY__ +-#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) ++#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) || defined(CONFIG_JzRISC) + /* We use a 36 bit physical address map here and + cannot access physical memory directly from core */ + #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) +diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h +index b2c4891..db88704 100644 +--- a/include/asm-mips/global_data.h ++++ b/include/asm-mips/global_data.h +@@ -39,6 +39,15 @@ + typedef struct global_data { + bd_t *bd; + unsigned long flags; ++#if defined(CONFIG_JZSOC) ++ /* There are other clocks in the Jz47xx or Jz5730*/ ++ unsigned long cpu_clk; /* CPU core clock */ ++ unsigned long sys_clk; /* System bus clock */ ++ unsigned long per_clk; /* Peripheral bus clock */ ++ unsigned long mem_clk; /* Memory bus clock */ ++ unsigned long dev_clk; /* Device clock */ ++ unsigned long fb_base; /* base address of framebuffer */ ++#endif + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + phys_size_t ram_size; /* RAM size */ +diff --git a/include/lcd.h b/include/lcd.h +index 1f85daa..997e246 100644 +--- a/include/lcd.h ++++ b/include/lcd.h +@@ -181,8 +181,44 @@ typedef struct vidinfo { + u_long mmio; /* Memory mapped registers */ + } vidinfo_t; + +-#else ++#elif defined(CONFIG_JZSOC) ++/* ++ * LCD controller stucture for JZSOC: JZ4730 JZ4740 ++ */ ++struct jz_fb_dma_descriptor { ++ u_long fdadr; /* Frame descriptor address register */ ++ u_long fsadr; /* Frame source address register */ ++ u_long fidr; /* Frame ID register */ ++ u_long ldcmd; /* Command register */ ++}; + ++/* ++ * Jz LCD info ++ */ ++struct jz_fb_info { ++ ++ u_long fdadr0; /* physical address of frame/palette descriptor */ ++ u_long fdadr1; /* physical address of frame descriptor */ ++ ++ /* DMA descriptors */ ++ struct jz_fb_dma_descriptor * dmadesc_fblow; ++ struct jz_fb_dma_descriptor * dmadesc_fbhigh; ++ struct jz_fb_dma_descriptor * dmadesc_palette; ++ u_long screen; /* address of frame buffer */ ++ u_long palette; /* address of palette memory */ ++ u_int palette_size; ++}; ++typedef struct vidinfo { ++ ushort vl_col; /* Number of columns (i.e. 640) */ ++ ushort vl_row; /* Number of rows (i.e. 480) */ ++ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ ++ ++ struct jz_fb_info jz_fb; ++} vidinfo_t; ++ ++extern vidinfo_t panel_info; ++ ++#else + typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 160) */ + ushort vl_row; /* Number of rows (i.e. 100) */ +@@ -194,7 +230,7 @@ typedef struct vidinfo { + void *priv; /* Pointer to driver-specific data */ + } vidinfo_t; + +-#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */ ++#endif /* CONFIG_MPC823, CONFIG_PXA250, CONFIG_MCC200 or CONFIG_JZ4740 */ + + extern vidinfo_t panel_info; + +@@ -234,6 +270,7 @@ void lcd_show_board_info(void); + #define LCD_COLOR4 2 + #define LCD_COLOR8 3 + #define LCD_COLOR16 4 ++#define LCD_COLOR32 5 + + /*----------------------------------------------------------------------*/ + #if defined(CONFIG_LCD_INFO_BELOW_LOGO) +@@ -285,13 +322,22 @@ void lcd_show_board_info(void); + # define CONSOLE_COLOR_GREY 14 + # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ + +-#else ++#elif LCD_BPP == LCD_COLOR16 + + /* + * 16bpp color definitions + */ + # define CONSOLE_COLOR_BLACK 0x0000 +-# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ ++# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ ++ ++#elif LCD_BPP == LCD_COLOR32 ++/* ++ * 18,24,32 bpp color definitions ++ */ ++# define CONSOLE_COLOR_BLACK 0x00000000 ++# define CONSOLE_COLOR_WHITE 0xffffffff /* Must remain last / highest */ ++ ++#else + + #endif /* color definitions */ + +@@ -322,7 +368,7 @@ void lcd_show_board_info(void); + #if LCD_BPP == LCD_MONOCHROME + # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ + (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) +-#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) ++#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR32) + # define COLOR_MASK(c) (c) + #else + # error Unsupported LCD BPP. +diff --git a/lib_mips/board.c b/lib_mips/board.c +index aa5b129..ea5166c 100644 +--- a/lib_mips/board.c ++++ b/lib_mips/board.c +@@ -45,6 +45,10 @@ DECLARE_GLOBAL_DATA_PTR; + + #undef DEBUG + ++#if defined(CONFIG_JZSOC) ++extern int jz_board_init(void); ++#endif ++ + extern int timer_init(void); + + extern int incaip_set_cpuclk(void); +@@ -109,7 +113,6 @@ void *sbrk (ptrdiff_t increment) + return ((void *) old); + } + +- + static int init_func_ram (void) + { + #ifdef CONFIG_BOARD_TYPES +@@ -129,7 +132,6 @@ static int init_func_ram (void) + + static int display_banner(void) + { +- + printf ("\n\n%s\n\n", version_string); + return (0); + } +@@ -178,6 +180,9 @@ static int init_baudrate (void) + typedef int (init_fnc_t) (void); + + init_fnc_t *init_sequence[] = { ++#if defined(CONFIG_JZSOC) ++ jz_board_init, /* init gpio/clocks/dram etc. */ ++#endif + board_early_init_f, + timer_init, + env_init, /* initialize environment */ +@@ -193,7 +198,6 @@ init_fnc_t *init_sequence[] = { + NULL, + }; + +- + void board_init_f(ulong bootflag) + { + gd_t gd_data, *id; +@@ -233,6 +237,12 @@ void board_init_f(ulong bootflag) + addr &= ~(4096 - 1); + debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); + ++#ifdef CONFIG_LCD ++ /* reserve memory for LCD display (always full pages) */ ++ addr = lcd_setmem (addr); ++ gd->fb_base = addr; ++#endif /* CONFIG_LCD */ ++ + /* Reserve memory for U-Boot code, data & bss + * round down to next 16 kB limit + */ +@@ -379,9 +389,9 @@ void board_init_r (gd_t *id, ulong dest_addr) + size = flash_init(); + display_flash_config (size); + bd->bi_flashsize = size; ++ bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; + #endif + +- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; + #if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE + bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */ + #else +diff --git a/lib_mips/time.c b/lib_mips/time.c +index 07e356d..4654bf4 100644 +--- a/lib_mips/time.c ++++ b/lib_mips/time.c +@@ -24,6 +24,8 @@ + #include + #include + ++#ifndef CONFIG_JzRISC ++ + static unsigned long timestamp; + + /* how many counter cycles in a jiffy */ +@@ -96,3 +98,5 @@ ulong get_tbclk(void) + { + return CONFIG_SYS_HZ; + } ++ ++#endif /* !CONFIG_JzRISC */ +-- +1.6.0.4 + diff --git a/target/linux/xburst/image/u-boot/patches/0002-fix-mmc.patch b/target/linux/xburst/image/u-boot/patches/0002-fix-mmc.patch deleted file mode 100644 index b82ebb309..000000000 --- a/target/linux/xburst/image/u-boot/patches/0002-fix-mmc.patch +++ /dev/null @@ -1,89 +0,0 @@ -diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c -index c23534d..16e8688 100644 ---- a/board/qi_lb60/qi_lb60.c -+++ b/board/qi_lb60/qi_lb60.c -@@ -45,47 +45,45 @@ static void gpio_init(void) - __gpio_as_i2c(); - - /* -+ * Initialize MSC pins -+ */ -+ __gpio_as_msc(); -+ /* __gpio_set_pin(2 + 3 * 32); */ -+ -+ /* - * Initialize Other pins - */ - /* unsigned int i; -- __gpio_as_output( GPIO_AUDIO_POP ); -- __gpio_set_pin( GPIO_AUDIO_POP ); -- -- -- for (i = 0; i < 8; i++){ -- __gpio_as_output( GPIO_KEYOUT_BASE + i ); -- __gpio_set_pin( GPIO_KEYOUT_BASE + i ); -+ for (i = 0; i < 8; i++) { -+ __gpio_as_output(GPIO_KEYOUT_BASE + i); -+ __gpio_set_pin(GPIO_KEYOUT_BASE + i); - } - - for (i = 0; i < 7; i++){ -- __gpio_as_input( GPIO_KEYIN_BASE + i ); -- __gpio_enable_pull( GPIO_KEYIN_BASE + i ); -+ __gpio_as_input(GPIO_KEYIN_BASE + i); -+ __gpio_enable_pull(GPIO_KEYIN_BASE + i); - } -- - __gpio_as_input( GPIO_KEYIN_8 ); - __gpio_enable_pull( GPIO_KEYIN_8 ); -- - */ -- __gpio_as_output( GPIO_LCD_CS ); -- __gpio_clear_pin( GPIO_LCD_CS ); -+ __gpio_as_output(GPIO_AUDIO_POP); -+ __gpio_set_pin(GPIO_AUDIO_POP); - -- __gpio_as_output( GPIO_AMP_EN ); -- __gpio_clear_pin( GPIO_AMP_EN ); -+ __gpio_as_output(GPIO_LCD_CS); -+ __gpio_clear_pin(GPIO_LCD_CS); - -- __gpio_as_output( GPIO_SDPW_EN ); -- __gpio_set_pin( GPIO_SDPW_EN ); -+ __gpio_as_output(GPIO_AMP_EN); -+ __gpio_clear_pin(GPIO_AMP_EN); - -- __gpio_as_input( GPIO_SD_DETECT ); -- __gpio_enable_pull( GPIO_SD_DETECT ); -+ __gpio_as_output(GPIO_SDPW_EN); -+ __gpio_disable_pull(GPIO_SDPW_EN); -+ __gpio_clear_pin(GPIO_SDPW_EN); - -- __gpio_as_input( GPIO_USB_DETECT ); -- __gpio_enable_pull( GPIO_USB_DETECT ); -+ __gpio_as_input(GPIO_SD_DETECT); -+ __gpio_disable_pull(GPIO_SD_DETECT); - -- /* -- * Initialize MSC pins -- */ -- __gpio_as_msc(); -- __gpio_set_pin(2 + 3 * 32); -+ __gpio_as_input(GPIO_USB_DETECT); -+ __gpio_enable_pull(GPIO_USB_DETECT); - } - - void board_early_init(void) -diff --git a/cpu/mips/jz_mmc.c b/cpu/mips/jz_mmc.c -index 8a7c310..ec0a518 100644 ---- a/cpu/mips/jz_mmc.c -+++ b/cpu/mips/jz_mmc.c -@@ -61,7 +61,7 @@ do { \ - ({ \ - int detected = 1; \ - __gpio_as_input(GPIO_SD_CD_N); \ -- if (__gpio_get_pin(GPIO_SD_CD_N)) \ -+ if (!__gpio_get_pin(GPIO_SD_CD_N)) \ - detected = 0; \ - detected; \ - }) diff --git a/target/linux/xburst/image/u-boot/patches/0003-add-2GB-nand-support.patch b/target/linux/xburst/image/u-boot/patches/0003-add-2GB-nand-support.patch deleted file mode 100644 index eb12bf3de..000000000 --- a/target/linux/xburst/image/u-boot/patches/0003-add-2GB-nand-support.patch +++ /dev/null @@ -1,176 +0,0 @@ -diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c -index 16e8688..572d22b 100644 ---- a/board/qi_lb60/qi_lb60.c -+++ b/board/qi_lb60/qi_lb60.c -@@ -48,12 +48,11 @@ static void gpio_init(void) - * Initialize MSC pins - */ - __gpio_as_msc(); -- /* __gpio_set_pin(2 + 3 * 32); */ - - /* - * Initialize Other pins - */ --/* unsigned int i; -+ unsigned int i; - for (i = 0; i < 8; i++) { - __gpio_as_output(GPIO_KEYOUT_BASE + i); - __gpio_set_pin(GPIO_KEYOUT_BASE + i); -@@ -63,9 +62,9 @@ static void gpio_init(void) - __gpio_as_input(GPIO_KEYIN_BASE + i); - __gpio_enable_pull(GPIO_KEYIN_BASE + i); - } -- __gpio_as_input( GPIO_KEYIN_8 ); -- __gpio_enable_pull( GPIO_KEYIN_8 ); --*/ -+ /* __gpio_as_input( GPIO_KEYIN_8 ); */ -+ /* __gpio_enable_pull( GPIO_KEYIN_8 ); */ -+ - __gpio_as_output(GPIO_AUDIO_POP); - __gpio_set_pin(GPIO_AUDIO_POP); - -diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h -index 68a2e87..3944eca 100644 ---- a/include/configs/qi_lb60.h -+++ b/include/configs/qi_lb60.h -@@ -13,7 +13,6 @@ - #ifndef __CONFIG_H - #define __CONFIG_H - --#define DEBUG - #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ - #define CONFIG_JzRISC 1 /* JzRISC core */ - #define CONFIG_JZSOC 1 /* Jz SoC */ -@@ -23,16 +22,16 @@ - #define CONFIG_DOS_PARTITION 1 - #define CONFIG_PCMCIA_SLOT_A 1 - --#define CONFIG_LCD 1 /* LCD support */ -+#define CONFIG_LCD 1 /* LCD support */ - #define LCD_BPP LCD_COLOR32/*5:18,24,32 bits per pixel */ - #define CONFIG_JZLCD_FOXCONN_PT035TN01 - - /* NAND Boot config code */ - #define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 - --#define CONFIG_CPU_SPEED 252000000 /* CPU clock: 252 MHz */ -+#define CONFIG_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ - #define CONFIG_EXTAL 12000000 /* EXTAL freq: 12 MHz */ --#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */ -+#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */ - #define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_CPU_SPEED - - #define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */ -@@ -46,16 +45,16 @@ - #define CONFIG_SYS_NO_FLASH 1 - - #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL) --#define CONFIG_BOOTDELAY 5 --#define CONFIG_BOOTFILE "uImage" /* file to load */ --#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw" --#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" --#define CONFIG_AUTOLOAD "n" /* No autoload */ -- --#define CONFIG_DRIVER_CS8900 1 --#define CS8900_BASE (0xa8000000) -+#define CONFIG_BOOTDELAY 0 -+#define CONFIG_BOOTFILE "uImage" /* file to load */ -+#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 rootfstype=jffs2 root=/dev/mtdblock2 rw rootwait" -+ /* "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootdelay=2" */ -+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x300000;bootm" -+ -+#define CONFIG_DRIVER_CS8900 1 -+#define CS8900_BASE (0xa8000000) - #define CS8900_BUS16 --#define CONFIG_ETHADDR 00:2a:cc:2a:af:fe /* Ethernet address */ -+#define CONFIG_ETHADDR 00:2a:cc:2a:af:fe /* Ethernet address */ - - /* allow to overwrite serial and ethaddr */ - #define CONFIG_ENV_OVERWRITE -@@ -92,10 +91,10 @@ - - #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - --#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */ -+#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */ - - #define CONFIG_SYS_MEMTEST_START 0x80100000 --#define CONFIG_SYS_MEMTEST_END 0x80800000 -+#define CONFIG_SYS_MEMTEST_END 0x80800000 - - #define CONFIG_RX_ETH_BUFFER 16 /* use 16 rx buffers on jz47xx eth */ - -@@ -107,17 +106,23 @@ - /* - * NAND FLASH configuration - */ --#define CONFIG_NAND_PAGE_SIZE 2048 --#define CONFIG_NAND_BLOCK_SIZE (256 << 10) /* NAND chip block size */ --#define CONFIG_NAND_BADBLOCK_PAGE 127 --/* NAND bad block was marked at this page in a block, starting from 0 */ --#define CONFIG_NAND_ECC_POS 6 --/* Ecc offset position in oob area, default value is 6 if it isn't defined. */ -- -+#define QI_LB60_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1 -+ * if board nand flash is 2GB, set to 2 -+ * for change the PAGE_SIZE and BLOCK_SIZE -+ * will delete when there is no 1GB flash -+ */ -+ -+#define CONFIG_NAND_PAGE_SIZE (2048 * QI_LB60_NAND_SIZE) -+/* nand chip block size */ -+#define CONFIG_NAND_BLOCK_SIZE (256 * QI_LB60_NAND_SIZE << 10) -+/* nand bad block was marked at this page in a block, start from 0 */ -+#define CONFIG_NAND_BADBLOCK_PAGE 127 -+/* ECC offset position in oob area, default value is 6 if it isn't defined */ -+#define CONFIG_NAND_ECC_POS (6 * QI_LB60_NAND_SIZE) - #define CONFIG_SYS_MAX_NAND_DEVICE 1 - #define NAND_MAX_CHIPS 1 - #define CONFIG_SYS_NAND_BASE 0xB8000000 --#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips*/ -+#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/ - #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE - - /* -@@ -150,25 +155,8 @@ - /* environment starts here */ - #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) - --/* -- * NOR FLASH and environment organization -- */ --#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ --#define CONFIG_SYS_MAX_FLASH_SECT (128)/* max number of sectors on one chip */ -- --#define PHYS_FLASH_1 0xa8000000 /* Flash Bank #1 */ -- --/* The following #defines are needed to get flash environment right */ --/* in pi/config.mk TEXT_BAS=0x88000000 */ -+/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */ - #define CONFIG_SYS_MONITOR_BASE TEXT_BASE --/* Reserve 256 kB for Monitor*/ --#define CONFIG_MONITOR_LEN (256*1024) -- --#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -- --/* timeout values are in ticks */ --#define CONFIG_FLASH_ERASE_TOUT (2 * CONFIG_HZ) /* Timeout for Flash Erase */ --#define CONFIG_FLASH_WRITE_TOUT (2 * CONFIG_HZ) /* Timeout for Flash Write */ - - /* - * SDRAM Info. -diff --git a/lib_mips/board.c b/lib_mips/board.c -index 539f78f..6a0e060 100644 ---- a/lib_mips/board.c -+++ b/lib_mips/board.c -@@ -389,9 +389,9 @@ void board_init_r (gd_t *id, ulong dest_addr) - size = flash_init(); - display_flash_config (size); - bd->bi_flashsize = size; -+ bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - #endif - -- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - #if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */ - #else