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get rid of CRLF encoding in various files

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21462 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
2010-05-16 00:20:17 +00:00
parent 6848738976
commit 388a290343
10 changed files with 596 additions and 596 deletions
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100
package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h
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@@ -1,50 +1,50 @@
/* Settings for Denali DDR SDRAM controller */ /* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ /* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B #define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0 #define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0 #define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0 #define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0 #define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200 #define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605 #define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303 #define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102 #define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a #define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203 #define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02 #define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8 #define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1 #define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0 #define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c #define MC_DC15_VALUE 0xf3c
#define MC_DC16_VALUE 0xC800 #define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd #define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300 #define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200 #define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA03 #define MC_DC20_VALUE 0xA03
#define MC_DC21_VALUE 0x1d00 #define MC_DC21_VALUE 0x1d00
#define MC_DC22_VALUE 0x1d1d #define MC_DC22_VALUE 0x1d1d
#define MC_DC23_VALUE 0x0 #define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5e /* was 0x7f */ #define MC_DC24_VALUE 0x5e /* was 0x7f */
#define MC_DC25_VALUE 0x0 #define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0 #define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0 #define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510 #define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89 #define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300 #define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0 #define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0 #define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0 #define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0 #define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0 #define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0 #define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0 #define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0 #define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0 #define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0 #define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0 #define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0 #define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0 #define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0 #define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500 #define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400 //#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0 #define MC_DC46_VALUE 0x0

100
package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h
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@@ -1,50 +1,50 @@
/* Settings for Denali DDR SDRAM controller */ /* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ /* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B #define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0 #define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0 #define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0 #define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0 #define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200 #define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605 #define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303 #define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102 #define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a #define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203 #define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02 #define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8 #define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1 #define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0 #define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ #define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800 #define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd #define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300 #define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200 #define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ #define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1200 #define MC_DC21_VALUE 0x1200
#define MC_DC22_VALUE 0x1212 #define MC_DC22_VALUE 0x1212
#define MC_DC23_VALUE 0x0 #define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ #define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0 #define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0 #define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0 #define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510 #define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89 #define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300 #define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0 #define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0 #define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0 #define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0 #define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0 #define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0 #define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0 #define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0 #define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0 #define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0 #define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0 #define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0 #define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0 #define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0 #define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500 #define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400 //#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0 #define MC_DC46_VALUE 0x0

100
package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
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@@ -1,50 +1,50 @@
/* Settings for Denali DDR SDRAM controller */ /* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ /* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B #define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0 #define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0 #define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0 #define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0 #define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200 #define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605 #define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303 #define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102 #define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a #define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203 #define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02 #define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8 #define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1 #define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0 #define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c #define MC_DC15_VALUE 0xf3c
#define MC_DC16_VALUE 0xC800 #define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd #define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300 #define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200 #define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA03 #define MC_DC20_VALUE 0xA03
#define MC_DC21_VALUE 0x1d00 #define MC_DC21_VALUE 0x1d00
#define MC_DC22_VALUE 0x1d1d #define MC_DC22_VALUE 0x1d1d
#define MC_DC23_VALUE 0x0 #define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5e /* was 0x7f */ #define MC_DC24_VALUE 0x5e /* was 0x7f */
#define MC_DC25_VALUE 0x0 #define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0 #define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0 #define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510 #define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89 #define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300 #define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0 #define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0 #define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0 #define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0 #define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0 #define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0 #define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0 #define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0 #define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0 #define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0 #define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0 #define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0 #define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0 #define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0 #define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500 #define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400 //#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0 #define MC_DC46_VALUE 0x0

100
package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h
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@@ -1,50 +1,50 @@
/* Settings for Denali DDR SDRAM controller */ /* Settings for Denali DDR SDRAM controller */
/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ /* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
#define MC_DC0_VALUE 0x1B1B #define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0 #define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0 #define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0 #define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0 #define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200 #define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605 #define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303 #define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102 #define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x70a #define MC_DC9_VALUE 0x70a
#define MC_DC10_VALUE 0x203 #define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xc02 #define MC_DC11_VALUE 0xc02
#define MC_DC12_VALUE 0x1C8 #define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1 #define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0 #define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ #define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800 #define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd #define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300 #define MC_DC18_VALUE 0x300
#define MC_DC19_VALUE 0x200 #define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ #define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1200 #define MC_DC21_VALUE 0x1200
#define MC_DC22_VALUE 0x1212 #define MC_DC22_VALUE 0x1212
#define MC_DC23_VALUE 0x0 #define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ #define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0 #define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0 #define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0 #define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510 #define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89 #define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300 #define MC_DC30_VALUE 0x8300
#define MC_DC31_VALUE 0x0 #define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0 #define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0 #define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0 #define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0 #define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0 #define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0 #define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0 #define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0 #define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0 #define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0 #define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0 #define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0 #define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0 #define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x500 #define MC_DC45_VALUE 0x500
//#define MC_DC45_VALUE 0x400 //#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0 #define MC_DC46_VALUE 0x0

102
package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
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@@ -1,51 +1,51 @@
/* Settings for Denali DDR SDRAM controller */ /* Settings for Denali DDR SDRAM controller */
/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ /* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
#define MC_DC0_VALUE 0x1B1B #define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0x0 #define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0 #define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x0 #define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0 #define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200 #define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x306 #define MC_DC6_VALUE 0x306
#define MC_DC7_VALUE 0x303 #define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102 #define MC_DC8_VALUE 0x102
#define MC_DC9_VALUE 0x80B #define MC_DC9_VALUE 0x80B
#define MC_DC10_VALUE 0x203 #define MC_DC10_VALUE 0x203
#define MC_DC11_VALUE 0xD02 #define MC_DC11_VALUE 0xD02
#define MC_DC12_VALUE 0x1C8 #define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1 #define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0 #define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/ #define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800 #define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xF #define MC_DC17_VALUE 0xF
#define MC_DC18_VALUE 0x301 #define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200 #define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ #define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1200 #define MC_DC21_VALUE 0x1200
#define MC_DC22_VALUE 0x1212 #define MC_DC22_VALUE 0x1212
#define MC_DC23_VALUE 0x0 #define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */ #define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0 #define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0 #define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x0 #define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x5FB #define MC_DC28_VALUE 0x5FB
#define MC_DC29_VALUE 0x35DF #define MC_DC29_VALUE 0x35DF
#define MC_DC30_VALUE 0x99E9 #define MC_DC30_VALUE 0x99E9
#define MC_DC31_VALUE 0x0 #define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0 #define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0 #define MC_DC33_VALUE 0x0
#define MC_DC34_VALUE 0x0 #define MC_DC34_VALUE 0x0
#define MC_DC35_VALUE 0x0 #define MC_DC35_VALUE 0x0
#define MC_DC36_VALUE 0x0 #define MC_DC36_VALUE 0x0
#define MC_DC37_VALUE 0x0 #define MC_DC37_VALUE 0x0
#define MC_DC38_VALUE 0x0 #define MC_DC38_VALUE 0x0
#define MC_DC39_VALUE 0x0 #define MC_DC39_VALUE 0x0
#define MC_DC40_VALUE 0x0 #define MC_DC40_VALUE 0x0
#define MC_DC41_VALUE 0x0 #define MC_DC41_VALUE 0x0
#define MC_DC42_VALUE 0x0 #define MC_DC42_VALUE 0x0
#define MC_DC43_VALUE 0x0 #define MC_DC43_VALUE 0x0
#define MC_DC44_VALUE 0x0 #define MC_DC44_VALUE 0x0
#define MC_DC45_VALUE 0x600 #define MC_DC45_VALUE 0x600
//#define MC_DC45_VALUE 0x400 //#define MC_DC45_VALUE 0x400
#define MC_DC46_VALUE 0x0 #define MC_DC46_VALUE 0x0

98
target/linux/etrax/files/arch/cris/arch-v10/drivers/etraxi2c.h
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@@ -1,49 +1,49 @@
#ifndef _LINUX_ETRAXI2C_H #ifndef _LINUX_ETRAXI2C_H
#define _LINUX_ETRAXI2C_H #define _LINUX_ETRAXI2C_H
/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */ /* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */
#define ETRAXI2C_IOCTYPE 44 #define ETRAXI2C_IOCTYPE 44
/* supported ioctl _IOC_NR's */ /* supported ioctl _IOC_NR's */
/* in write operations, the argument contains both i2c /* in write operations, the argument contains both i2c
* slave, register and value. * slave, register and value.
*/ */
#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value)) #define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value))
#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8)) #define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8))
#define I2C_ARGSLAVE(arg) ((arg) >> 16) #define I2C_ARGSLAVE(arg) ((arg) >> 16)
#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff) #define I2C_ARGREG(arg) (((arg) >> 8) & 0xff)
#define I2C_ARGVALUE(arg) ((arg) & 0xff) #define I2C_ARGVALUE(arg) ((arg) & 0xff)
#define I2C_WRITEREG 0x1 /* write to an I2C register */ #define I2C_WRITEREG 0x1 /* write to an I2C register */
#define I2C_READREG 0x2 /* read from an I2C register */ #define I2C_READREG 0x2 /* read from an I2C register */
/* /*
EXAMPLE usage: EXAMPLE usage:
i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
*/ */
/* Extended part */ /* Extended part */
#define I2C_READ 0x4 /* reads from I2C device */ #define I2C_READ 0x4 /* reads from I2C device */
#define I2C_WRITE 0x3 /* writes to I2C device */ #define I2C_WRITE 0x3 /* writes to I2C device */
#define I2C_WRITEREAD 0x5 /* writes to I2C device where to start reading */ #define I2C_WRITEREAD 0x5 /* writes to I2C device where to start reading */
typedef struct _I2C_DATA typedef struct _I2C_DATA
{ {
unsigned char slave; /* I2C address (8-bit representation) of slave device */ unsigned char slave; /* I2C address (8-bit representation) of slave device */
unsigned char wbuf[256]; /* Write buffer (length = 256 bytes) */ unsigned char wbuf[256]; /* Write buffer (length = 256 bytes) */
unsigned int wlen; /* Number of bytes to write from wbuf[] */ unsigned int wlen; /* Number of bytes to write from wbuf[] */
unsigned char rbuf[256]; /* Read buffer (length = 256 bytes) */ unsigned char rbuf[256]; /* Read buffer (length = 256 bytes) */
unsigned int rlen; /* Number of bytes to read into rbuf[] */ unsigned int rlen; /* Number of bytes to read into rbuf[] */
} I2C_DATA; } I2C_DATA;
#endif #endif

40
target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_errno.h
View File

@@ -1,20 +1,20 @@
#ifndef _I2C_ERRNO_H #ifndef _I2C_ERRNO_H
#define _I2C_ERRNO_H #define _I2C_ERRNO_H
#define EI2CNOERRORS 0 /* All fine */ #define EI2CNOERRORS 0 /* All fine */
#define EI2CBUSNFREE 1 /* I2C bus not free */ #define EI2CBUSNFREE 1 /* I2C bus not free */
#define EI2CWADDRESS 2 /* Address write failed */ #define EI2CWADDRESS 2 /* Address write failed */
#define EI2CRADDRESS 3 /* Address read failed */ #define EI2CRADDRESS 3 /* Address read failed */
#define EI2CSENDDATA 4 /* Sending data failed */ #define EI2CSENDDATA 4 /* Sending data failed */
#define EI2CRECVDATA 5 /* Receiving data failed */ #define EI2CRECVDATA 5 /* Receiving data failed */
#define EI2CSTRTCOND 6 /* Start condition failed */ #define EI2CSTRTCOND 6 /* Start condition failed */
#define EI2CRSTACOND 7 /* Repeated start condition failed */ #define EI2CRSTACOND 7 /* Repeated start condition failed */
#define EI2CSTOPCOND 8 /* Stop condition failed */ #define EI2CSTOPCOND 8 /* Stop condition failed */
#define EI2CNOSNDBYT 9 /* Number of send bytes is 0, while there's a send buffer defined */ #define EI2CNOSNDBYT 9 /* Number of send bytes is 0, while there's a send buffer defined */
#define EI2CNOSNDBUF 10 /* No send buffer defined, while number of send bytes is not 0 */ #define EI2CNOSNDBUF 10 /* No send buffer defined, while number of send bytes is not 0 */
#define EI2CNORCVBYT 11 /* Number of receive bytes is 0, while there's a receive buffer defined */ #define EI2CNORCVBYT 11 /* Number of receive bytes is 0, while there's a receive buffer defined */
#define EI2CNORCVBUF 12 /* No receive buffer defined, while number of receive bytes is not 0 */ #define EI2CNORCVBUF 12 /* No receive buffer defined, while number of receive bytes is not 0 */
#define EI2CNOACKNLD 13 /* No acknowledge received from slave */ #define EI2CNOACKNLD 13 /* No acknowledge received from slave */
#define EI2CNOMNUMBR 14 /* No MAJOR number received from kernel while registering the device */ #define EI2CNOMNUMBR 14 /* No MAJOR number received from kernel while registering the device */
#endif /* _I2C_ERRNO_H */ #endif /* _I2C_ERRNO_H */

60
target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_gvc.h
View File

@@ -1,30 +1,30 @@
#ifndef _I2C_H #ifndef _I2C_H
#define _I2C_H #define _I2C_H
int i2c_init(void); int i2c_init(void);
/* High level I2C actions */ /* High level I2C actions */
int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg); unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
/* Low level I2C */ /* Low level I2C */
int i2c_start(void); int i2c_start(void);
int i2c_stop(void); int i2c_stop(void);
int i2c_outbyte(unsigned char x); int i2c_outbyte(unsigned char x);
unsigned char i2c_inbyte(void); unsigned char i2c_inbyte(void);
int i2c_getack(void); int i2c_getack(void);
void i2c_sendack(void); void i2c_sendack(void);
void i2c_sendnack(void); void i2c_sendnack(void);
/**GVC**/ /**GVC**/
/* New low level I2C functions */ /* New low level I2C functions */
int i2c_read( unsigned char slave, unsigned char* rbuf, unsigned char rlen ); int i2c_read( unsigned char slave, unsigned char* rbuf, unsigned char rlen );
int i2c_write( unsigned char slave, unsigned char* wbuf, unsigned char wlen ); int i2c_write( unsigned char slave, unsigned char* wbuf, unsigned char wlen );
int i2c_writeread( unsigned char slave int i2c_writeread( unsigned char slave
, unsigned char* wbuf , unsigned char* wbuf
, unsigned char wlen , unsigned char wlen
, unsigned char* rbuf , unsigned char* rbuf
, unsigned char rlen , unsigned char rlen
); );
/**END GVC**/ /**END GVC**/
#endif /* _I2C_H */ #endif /* _I2C_H */

84
target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile
View File

@@ -1,42 +1,42 @@
# #
# linux/arch/mips/boot/compressed/Makefile # linux/arch/mips/boot/compressed/Makefile
# #
# create a compressed zImage from the original vmlinux # create a compressed zImage from the original vmlinux
# #
targets := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o targets := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o
OBJS := $(obj)/head.o $(obj)/misc.o OBJS := $(obj)/head.o $(obj)/misc.o
LD_ARGS := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic LD_ARGS := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic
OBJCOPY_ARGS := -O elf32-tradlittlemips OBJCOPY_ARGS := -O elf32-tradlittlemips
ENTRY := $(obj)/../tools/entry ENTRY := $(obj)/../tools/entry
FILESIZE := $(obj)/../tools/filesize FILESIZE := $(obj)/../tools/filesize
drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
strip-flags = $(addprefix --remove-section=,$(drop-sections)) strip-flags = $(addprefix --remove-section=,$(drop-sections))
$(obj)/vmlinux.bin.gz: vmlinux $(obj)/vmlinux.bin.gz: vmlinux
rm -f $(obj)/vmlinux.bin.gz rm -f $(obj)/vmlinux.bin.gz
$(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin
gzip -v9f $(obj)/vmlinux.bin gzip -v9f $(obj)/vmlinux.bin
$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux $(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux
$(CC) $(KBUILD_AFLAGS) \ $(CC) $(KBUILD_AFLAGS) \
-DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \ -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \
-DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \ -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \
-DLOADADDR=$(loadaddr) \ -DLOADADDR=$(loadaddr) \
-c -o $(obj)/head.o $< -c -o $(obj)/head.o $<
$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o $(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o
$(OBJCOPY) \ $(OBJCOPY) \
--add-section=.image=$(obj)/vmlinux.bin.gz \ --add-section=.image=$(obj)/vmlinux.bin.gz \
--set-section-flags=.image=contents,alloc,load,readonly,data \ --set-section-flags=.image=contents,alloc,load,readonly,data \
$(obj)/dummy.o $(obj)/piggy.o $(obj)/dummy.o $(obj)/piggy.o
$(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o
$(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap
zImage: $(obj)/vmlinuz zImage: $(obj)/vmlinuz
$(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage

408
tools/firmware-utils/src/nand_ecc.c
View File

@@ -1,204 +1,204 @@
/* /*
* calculate ecc code for nand flash * calculate ecc code for nand flash
* *
* Copyright (C) 2008 yajin <yajin@vm-kernel.org> * Copyright (C) 2008 yajin <yajin@vm-kernel.org>
* Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or * published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License. * (at your option) version 3 of the License.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
#include <sys/types.h> #include <sys/types.h>
#include <sys/stat.h> #include <sys/stat.h>
#include <unistd.h> #include <unistd.h>
#include <stdlib.h> #include <stdlib.h>
#include <stdint.h> #include <stdint.h>
#include <fcntl.h> #include <fcntl.h>
#include <stdio.h> #include <stdio.h>
#define DEF_NAND_PAGE_SIZE 2048 #define DEF_NAND_PAGE_SIZE 2048
#define DEF_NAND_OOB_SIZE 64 #define DEF_NAND_OOB_SIZE 64
#define DEF_NAND_ECC_OFFSET 0x28 #define DEF_NAND_ECC_OFFSET 0x28
static int page_size = DEF_NAND_PAGE_SIZE; static int page_size = DEF_NAND_PAGE_SIZE;
static int oob_size = DEF_NAND_OOB_SIZE; static int oob_size = DEF_NAND_OOB_SIZE;
static int ecc_offset = DEF_NAND_ECC_OFFSET; static int ecc_offset = DEF_NAND_ECC_OFFSET;
/* /*
* Pre-calculated 256-way 1 byte column parity * Pre-calculated 256-way 1 byte column parity
*/ */
static const uint8_t nand_ecc_precalc_table[] = { static const uint8_t nand_ecc_precalc_table[] = {
0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
}; };
/** /**
* nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block
* @dat: raw data * @dat: raw data
* @ecc_code: buffer for ECC * @ecc_code: buffer for ECC
*/ */
int nand_calculate_ecc(const uint8_t *dat, int nand_calculate_ecc(const uint8_t *dat,
uint8_t *ecc_code) uint8_t *ecc_code)
{ {
uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; uint8_t idx, reg1, reg2, reg3, tmp1, tmp2;
int i; int i;
/* Initialize variables */ /* Initialize variables */
reg1 = reg2 = reg3 = 0; reg1 = reg2 = reg3 = 0;
/* Build up column parity */ /* Build up column parity */
for(i = 0; i < 256; i++) { for(i = 0; i < 256; i++) {
/* Get CP0 - CP5 from table */ /* Get CP0 - CP5 from table */
idx = nand_ecc_precalc_table[*dat++]; idx = nand_ecc_precalc_table[*dat++];
reg1 ^= (idx & 0x3f); reg1 ^= (idx & 0x3f);
/* All bit XOR = 1 ? */ /* All bit XOR = 1 ? */
if (idx & 0x40) { if (idx & 0x40) {
reg3 ^= (uint8_t) i; reg3 ^= (uint8_t) i;
reg2 ^= ~((uint8_t) i); reg2 ^= ~((uint8_t) i);
} }
} }
/* Create non-inverted ECC code from line parity */ /* Create non-inverted ECC code from line parity */
tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */ tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */
tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */
tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */ tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */
tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */
tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */ tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */
tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */
tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */ tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */
tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */
tmp2 = (reg3 & 0x08) << 4; /* B3 -> B7 */ tmp2 = (reg3 & 0x08) << 4; /* B3 -> B7 */
tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */
tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */ tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */
tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */
tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */ tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */
tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */
tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */ tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */
tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */ tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */
/* Calculate final ECC code */ /* Calculate final ECC code */
#ifdef CONFIG_MTD_NAND_ECC_SMC #ifdef CONFIG_MTD_NAND_ECC_SMC
ecc_code[0] = ~tmp2; ecc_code[0] = ~tmp2;
ecc_code[1] = ~tmp1; ecc_code[1] = ~tmp1;
#else #else
ecc_code[0] = ~tmp1; ecc_code[0] = ~tmp1;
ecc_code[1] = ~tmp2; ecc_code[1] = ~tmp2;
#endif #endif
ecc_code[2] = ((~reg1) << 2) | 0x03; ecc_code[2] = ((~reg1) << 2) | 0x03;
return 0; return 0;
} }
/* /*
* usage: bb-nandflash-ecc start_address size * usage: bb-nandflash-ecc start_address size
*/ */
void usage(const char *prog) void usage(const char *prog)
{ {
fprintf(stderr, "Usage: %s [options] <input> <output>\n" fprintf(stderr, "Usage: %s [options] <input> <output>\n"
"Options:\n" "Options:\n"
" -p <pagesize> NAND page size (default: %d)\n" " -p <pagesize> NAND page size (default: %d)\n"
" -o <oobsize> NAND OOB size (default: %d)\n" " -o <oobsize> NAND OOB size (default: %d)\n"
" -e <offset> NAND ECC offset (default: %d)\n" " -e <offset> NAND ECC offset (default: %d)\n"
"\n", prog, DEF_NAND_PAGE_SIZE, DEF_NAND_OOB_SIZE, "\n", prog, DEF_NAND_PAGE_SIZE, DEF_NAND_OOB_SIZE,
DEF_NAND_ECC_OFFSET); DEF_NAND_ECC_OFFSET);
exit(1); exit(1);
} }
/*start_address/size does not include oob /*start_address/size does not include oob
*/ */
int main(int argc, char **argv) int main(int argc, char **argv)
{ {
uint8_t *page_data = NULL; uint8_t *page_data = NULL;
uint8_t *ecc_data; uint8_t *ecc_data;
int infd = -1, outfd = -1; int infd = -1, outfd = -1;
int ret = 1; int ret = 1;
ssize_t bytes; ssize_t bytes;
int ch; int ch;
while ((ch = getopt(argc, argv, "e:o:p:")) != -1) { while ((ch = getopt(argc, argv, "e:o:p:")) != -1) {
switch(ch) { switch(ch) {
case 'p': case 'p':
page_size = strtoul(optarg, NULL, 0); page_size = strtoul(optarg, NULL, 0);
break; break;
case 'o': case 'o':
oob_size = strtoul(optarg, NULL, 0); oob_size = strtoul(optarg, NULL, 0);
break; break;
case 'e': case 'e':
ecc_offset = strtoul(optarg, NULL, 0); ecc_offset = strtoul(optarg, NULL, 0);
break; break;
default: default:
usage(argv[0]); usage(argv[0]);
} }
} }
argc -= optind; argc -= optind;
if (argc < 2) if (argc < 2)
usage(argv[0]); usage(argv[0]);
argv += optind; argv += optind;
infd = open(argv[0], O_RDONLY, 0); infd = open(argv[0], O_RDONLY, 0);
if (infd < 0) { if (infd < 0) {
perror("open input file"); perror("open input file");
goto out; goto out;
} }
outfd = open(argv[1], O_WRONLY|O_CREAT|O_TRUNC, 0644); outfd = open(argv[1], O_WRONLY|O_CREAT|O_TRUNC, 0644);
if (outfd < 0) { if (outfd < 0) {
perror("open output file"); perror("open output file");
goto out; goto out;
} }
page_data = malloc(page_size + oob_size); page_data = malloc(page_size + oob_size);
while ((bytes = read(infd, page_data, page_size)) == page_size) { while ((bytes = read(infd, page_data, page_size)) == page_size) {
int j; int j;
ecc_data = page_data + page_size + ecc_offset; ecc_data = page_data + page_size + ecc_offset;
for (j = 0; j < page_size / 256; j++) for (j = 0; j < page_size / 256; j++)
{ {
nand_calculate_ecc(page_data + j * 256, ecc_data); nand_calculate_ecc(page_data + j * 256, ecc_data);
ecc_data += 3; ecc_data += 3;
} }
write(outfd, page_data, page_size + oob_size); write(outfd, page_data, page_size + oob_size);
} }
ret = 0; ret = 0;
out: out:
if (infd >= 0) if (infd >= 0)
close(infd); close(infd);
if (outfd >= 0) if (outfd >= 0)
close(outfd); close(outfd);
if (page_data) if (page_data)
free(page_data); free(page_data);
return ret; return ret;
} }