mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
ramips: move the ethernet driver into a separate directory
Also clean up the Kconfig symbols. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30670 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
1025
target/linux/ramips/files/drivers/net/ethernet/ramips/ramips.c
Normal file
1025
target/linux/ramips/files/drivers/net/ethernet/ramips/ramips.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,401 @@
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#include <linux/ioport.h>
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#include <rt305x_regs.h>
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#include <rt305x_esw_platform.h>
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#define RT305X_ESW_REG_FCT0 0x08
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#define RT305X_ESW_REG_PFC1 0x14
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#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
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#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
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#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
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#define RT305X_ESW_REG_FPA 0x84
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#define RT305X_ESW_REG_SOCPC 0x8c
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#define RT305X_ESW_REG_POC1 0x90
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#define RT305X_ESW_REG_POC2 0x94
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#define RT305X_ESW_REG_POC3 0x98
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#define RT305X_ESW_REG_SGC 0x9c
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#define RT305X_ESW_REG_PCR0 0xc0
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#define RT305X_ESW_REG_PCR1 0xc4
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#define RT305X_ESW_REG_FPA2 0xc8
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#define RT305X_ESW_REG_FCT2 0xcc
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#define RT305X_ESW_REG_SGC2 0xe4
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#define RT305X_ESW_REG_P0LED 0xa4
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#define RT305X_ESW_REG_P1LED 0xa8
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#define RT305X_ESW_REG_P2LED 0xac
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#define RT305X_ESW_REG_P3LED 0xb0
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#define RT305X_ESW_REG_P4LED 0xb4
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#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
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#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
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#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
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#define RT305X_ESW_PCR1_WT_DONE BIT(0)
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#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
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#define RT305X_ESW_PVIDC_PVID_M 0xfff
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#define RT305X_ESW_PVIDC_PVID_S 12
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#define RT305X_ESW_VLANI_VID_M 0xfff
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#define RT305X_ESW_VLANI_VID_S 12
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#define RT305X_ESW_VMSC_MSC_M 0xff
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#define RT305X_ESW_VMSC_MSC_S 8
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#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
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#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
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#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
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#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
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#define RT305X_ESW_POC1_EN_BP_S 0
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#define RT305X_ESW_POC1_EN_FC_S 8
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#define RT305X_ESW_POC1_DIS_RMC2CPU_S 16
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#define RT305X_ESW_POC1_DIS_PORT_S 23
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#define RT305X_ESW_POC3_UNTAG_EN_S 0
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#define RT305X_ESW_POC3_ENAGING_S 8
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#define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16
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#define RT305X_ESW_PORT0 0
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#define RT305X_ESW_PORT1 1
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#define RT305X_ESW_PORT2 2
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#define RT305X_ESW_PORT3 3
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#define RT305X_ESW_PORT4 4
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#define RT305X_ESW_PORT5 5
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#define RT305X_ESW_PORT6 6
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#define RT305X_ESW_PORTS_INTERNAL \
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(BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
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BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
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BIT(RT305X_ESW_PORT4))
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#define RT305X_ESW_PORTS_NOCPU \
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(RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
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#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
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#define RT305X_ESW_PORTS_ALL \
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(RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
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#define RT305X_ESW_NUM_VLANS 16
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#define RT305X_ESW_NUM_PORTS 7
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struct rt305x_esw {
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void __iomem *base;
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struct rt305x_esw_platform_data *pdata;
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spinlock_t reg_rw_lock;
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};
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static inline void
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rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
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{
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__raw_writel(val, esw->base + reg);
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}
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static inline u32
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rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
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{
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return __raw_readl(esw->base + reg);
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}
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static inline void
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rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
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unsigned long val)
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{
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unsigned long t;
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t = __raw_readl(esw->base + reg) & ~mask;
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__raw_writel(t | val, esw->base + reg);
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}
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static void
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rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
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unsigned long val)
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{
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unsigned long flags;
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spin_lock_irqsave(&esw->reg_rw_lock, flags);
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rt305x_esw_rmw_raw(esw, reg, mask, val);
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spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
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}
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static u32
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rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
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u32 write_data)
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{
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unsigned long t_start = jiffies;
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int ret = 0;
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while (1) {
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if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
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RT305X_ESW_PCR1_WT_DONE))
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break;
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if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
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ret = 1;
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goto out;
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}
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}
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write_data &= 0xffff;
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rt305x_esw_wr(esw,
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(write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
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(phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
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(phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
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RT305X_ESW_REG_PCR0);
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t_start = jiffies;
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while (1) {
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if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
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RT305X_ESW_PCR1_WT_DONE)
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break;
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if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
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ret = 1;
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break;
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}
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}
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out:
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if (ret)
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printk(KERN_ERR "ramips_eth: MDIO timeout\n");
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return ret;
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}
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static void
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rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
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{
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unsigned s;
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s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
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rt305x_esw_rmw(esw,
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RT305X_ESW_REG_VLANI(vlan / 2),
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RT305X_ESW_VLANI_VID_M << s,
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(vid & RT305X_ESW_VLANI_VID_M) << s);
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}
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static void
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rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
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{
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unsigned s;
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s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
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rt305x_esw_rmw(esw,
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RT305X_ESW_REG_PVIDC(port / 2),
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RT305X_ESW_PVIDC_PVID_M << s,
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(pvid & RT305X_ESW_PVIDC_PVID_M) << s);
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}
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static void
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rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
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{
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unsigned s;
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s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
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rt305x_esw_rmw(esw,
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RT305X_ESW_REG_VMSC(vlan / 4),
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RT305X_ESW_VMSC_MSC_M << s,
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(msc & RT305X_ESW_VMSC_MSC_M) << s);
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}
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static void
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rt305x_esw_hw_init(struct rt305x_esw *esw)
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{
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int i;
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/* vodoo from original driver */
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rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
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rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
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rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
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/* Enable Back Pressure, and Flow Control */
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rt305x_esw_wr(esw,
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((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) |
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(RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)),
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RT305X_ESW_REG_POC1);
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/* Enable Aging, and VLAN TAG removal */
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rt305x_esw_wr(esw,
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((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) |
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(RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)),
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RT305X_ESW_REG_POC3);
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rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
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rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
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/* Setup SoC Port control register */
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rt305x_esw_wr(esw,
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(RT305X_ESW_SOCPC_CRC_PADDING |
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(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
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(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
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(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
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RT305X_ESW_REG_SOCPC);
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rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
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rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
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/* Force Link/Activity on ports */
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rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED);
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rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED);
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rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED);
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rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED);
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rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED);
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rt305x_mii_write(esw, 0, 31, 0x8000);
|
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for (i = 0; i < 5; i++) {
|
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/* TX10 waveform coefficient */
|
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rt305x_mii_write(esw, i, 0, 0x3100);
|
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/* TX10 waveform coefficient */
|
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rt305x_mii_write(esw, i, 26, 0x1601);
|
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/* TX100/TX10 AD/DA current bias */
|
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rt305x_mii_write(esw, i, 29, 0x7058);
|
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/* TX100 slew rate control */
|
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rt305x_mii_write(esw, i, 30, 0x0018);
|
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}
|
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|
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/* PHY IOT */
|
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/* select global register */
|
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rt305x_mii_write(esw, 0, 31, 0x0);
|
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/* tune TP_IDL tail and head waveform */
|
||||
rt305x_mii_write(esw, 0, 22, 0x052f);
|
||||
/* set TX10 signal amplitude threshold to minimum */
|
||||
rt305x_mii_write(esw, 0, 17, 0x0fe0);
|
||||
/* set squelch amplitude to higher threshold */
|
||||
rt305x_mii_write(esw, 0, 18, 0x40ba);
|
||||
/* longer TP_IDL tail length */
|
||||
rt305x_mii_write(esw, 0, 14, 0x65);
|
||||
/* select local register */
|
||||
rt305x_mii_write(esw, 0, 31, 0x8000);
|
||||
|
||||
for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
|
||||
rt305x_esw_set_vlan_id(esw, i, 0);
|
||||
rt305x_esw_set_vmsc(esw, i, 0);
|
||||
}
|
||||
|
||||
for (i = 0; i < RT305X_ESW_NUM_PORTS; i++)
|
||||
rt305x_esw_set_pvid(esw, i, 1);
|
||||
|
||||
switch (esw->pdata->vlan_config) {
|
||||
case RT305X_ESW_VLAN_CONFIG_NONE:
|
||||
break;
|
||||
|
||||
case RT305X_ESW_VLAN_CONFIG_BYPASS:
|
||||
/* Pass all vlan tags to all ports */
|
||||
for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
|
||||
rt305x_esw_set_vlan_id(esw, i, i+1);
|
||||
rt305x_esw_set_vmsc(esw, i, RT305X_ESW_PORTS_ALL);
|
||||
}
|
||||
/* Disable VLAN TAG removal, keep aging on. */
|
||||
rt305x_esw_wr(esw,
|
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RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S,
|
||||
RT305X_ESW_REG_POC3);
|
||||
break;
|
||||
|
||||
case RT305X_ESW_VLAN_CONFIG_LLLLW:
|
||||
rt305x_esw_set_vlan_id(esw, 0, 1);
|
||||
rt305x_esw_set_vlan_id(esw, 1, 2);
|
||||
rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
|
||||
|
||||
rt305x_esw_set_vmsc(esw, 0,
|
||||
BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
|
||||
BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
|
||||
BIT(RT305X_ESW_PORT6));
|
||||
rt305x_esw_set_vmsc(esw, 1,
|
||||
BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6));
|
||||
break;
|
||||
|
||||
case RT305X_ESW_VLAN_CONFIG_WLLLL:
|
||||
rt305x_esw_set_vlan_id(esw, 0, 1);
|
||||
rt305x_esw_set_vlan_id(esw, 1, 2);
|
||||
rt305x_esw_set_pvid(esw, RT305X_ESW_PORT0, 2);
|
||||
|
||||
rt305x_esw_set_vmsc(esw, 0,
|
||||
BIT(RT305X_ESW_PORT1) | BIT(RT305X_ESW_PORT2) |
|
||||
BIT(RT305X_ESW_PORT3) | BIT(RT305X_ESW_PORT4) |
|
||||
BIT(RT305X_ESW_PORT6));
|
||||
rt305x_esw_set_vmsc(esw, 1,
|
||||
BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT6));
|
||||
break;
|
||||
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
rt305x_esw_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rt305x_esw_platform_data *pdata;
|
||||
struct rt305x_esw *esw;
|
||||
struct resource *res;
|
||||
int err;
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (!pdata)
|
||||
return -EINVAL;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "no memory resource found\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
|
||||
if (!esw) {
|
||||
dev_err(&pdev->dev, "no memory for private data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
esw->base = ioremap(res->start, resource_size(res));
|
||||
if (!esw->base) {
|
||||
dev_err(&pdev->dev, "ioremap failed\n");
|
||||
err = -ENOMEM;
|
||||
goto free_esw;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, esw);
|
||||
|
||||
esw->pdata = pdata;
|
||||
spin_lock_init(&esw->reg_rw_lock);
|
||||
rt305x_esw_hw_init(esw);
|
||||
|
||||
return 0;
|
||||
|
||||
free_esw:
|
||||
kfree(esw);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
rt305x_esw_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rt305x_esw *esw;
|
||||
|
||||
esw = platform_get_drvdata(pdev);
|
||||
if (esw) {
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
iounmap(esw->base);
|
||||
kfree(esw);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rt305x_esw_driver = {
|
||||
.probe = rt305x_esw_probe,
|
||||
.remove = rt305x_esw_remove,
|
||||
.driver = {
|
||||
.name = "rt305x-esw",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init
|
||||
rt305x_esw_init(void)
|
||||
{
|
||||
return platform_driver_register(&rt305x_esw_driver);
|
||||
}
|
||||
|
||||
static void
|
||||
rt305x_esw_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&rt305x_esw_driver);
|
||||
}
|
||||
@@ -0,0 +1,248 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* based on Ralink SDK3.3
|
||||
* Copyright (C) 2009 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef RAMIPS_ETH_H
|
||||
#define RAMIPS_ETH_H
|
||||
|
||||
#include <linux/mii.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#define NUM_RX_DESC 256
|
||||
#define NUM_TX_DESC 256
|
||||
|
||||
#define RAMIPS_DELAY_EN_INT 0x80
|
||||
#define RAMIPS_DELAY_MAX_INT 0x04
|
||||
#define RAMIPS_DELAY_MAX_TOUT 0x04
|
||||
#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT)
|
||||
#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN)
|
||||
#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000
|
||||
|
||||
/* interrupt bits */
|
||||
#define RAMIPS_CNT_PPE_AF BIT(31)
|
||||
#define RAMIPS_CNT_GDM_AF BIT(29)
|
||||
#define RAMIPS_PSE_P2_FC BIT(26)
|
||||
#define RAMIPS_PSE_BUF_DROP BIT(24)
|
||||
#define RAMIPS_GDM_OTHER_DROP BIT(23)
|
||||
#define RAMIPS_PSE_P1_FC BIT(22)
|
||||
#define RAMIPS_PSE_P0_FC BIT(21)
|
||||
#define RAMIPS_PSE_FQ_EMPTY BIT(20)
|
||||
#define RAMIPS_GE1_STA_CHG BIT(18)
|
||||
#define RAMIPS_TX_COHERENT BIT(17)
|
||||
#define RAMIPS_RX_COHERENT BIT(16)
|
||||
#define RAMIPS_TX_DONE_INT3 BIT(11)
|
||||
#define RAMIPS_TX_DONE_INT2 BIT(10)
|
||||
#define RAMIPS_TX_DONE_INT1 BIT(9)
|
||||
#define RAMIPS_TX_DONE_INT0 BIT(8)
|
||||
#define RAMIPS_RX_DONE_INT0 BIT(2)
|
||||
#define RAMIPS_TX_DLY_INT BIT(1)
|
||||
#define RAMIPS_RX_DLY_INT BIT(0)
|
||||
|
||||
/* registers */
|
||||
#define RAMIPS_FE_OFFSET 0x0000
|
||||
#define RAMIPS_GDMA_OFFSET 0x0020
|
||||
#define RAMIPS_PSE_OFFSET 0x0040
|
||||
#define RAMIPS_GDMA2_OFFSET 0x0060
|
||||
#define RAMIPS_CDMA_OFFSET 0x0080
|
||||
#define RAMIPS_PDMA_OFFSET 0x0100
|
||||
#define RAMIPS_PPE_OFFSET 0x0200
|
||||
#define RAMIPS_CMTABLE_OFFSET 0x0400
|
||||
#define RAMIPS_POLICYTABLE_OFFSET 0x1000
|
||||
|
||||
#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00)
|
||||
#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04)
|
||||
#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08)
|
||||
#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C)
|
||||
#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10)
|
||||
#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14)
|
||||
#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18)
|
||||
#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C)
|
||||
|
||||
#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00)
|
||||
#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04)
|
||||
#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08)
|
||||
#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C)
|
||||
#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10)
|
||||
|
||||
#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00)
|
||||
#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04)
|
||||
#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08)
|
||||
#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C)
|
||||
#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10)
|
||||
|
||||
#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00)
|
||||
#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04)
|
||||
#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08)
|
||||
#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C)
|
||||
|
||||
#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00)
|
||||
#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04)
|
||||
|
||||
#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00)
|
||||
#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04)
|
||||
#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08)
|
||||
#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C)
|
||||
#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10)
|
||||
#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14)
|
||||
#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18)
|
||||
#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C)
|
||||
#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20)
|
||||
#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24)
|
||||
#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28)
|
||||
#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C)
|
||||
#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30)
|
||||
#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34)
|
||||
#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38)
|
||||
#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C)
|
||||
#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40)
|
||||
#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44)
|
||||
#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48)
|
||||
#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C)
|
||||
#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50)
|
||||
#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54)
|
||||
#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58)
|
||||
#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C)
|
||||
#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x60)
|
||||
#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x64)
|
||||
#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68)
|
||||
#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C)
|
||||
|
||||
/* MDIO_CFG register bits */
|
||||
#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29)
|
||||
#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16)
|
||||
#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15)
|
||||
#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13)
|
||||
#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13)
|
||||
#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
|
||||
#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12)
|
||||
#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11)
|
||||
#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10)
|
||||
#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9)
|
||||
#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8)
|
||||
#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
|
||||
#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
|
||||
#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
|
||||
#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
|
||||
#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5)
|
||||
#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4)
|
||||
#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
|
||||
#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
|
||||
#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
|
||||
#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
|
||||
#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0
|
||||
#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1
|
||||
#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2
|
||||
#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3
|
||||
|
||||
/* uni-cast port */
|
||||
#define RAMIPS_GDM1_ICS_EN BIT(22)
|
||||
#define RAMIPS_GDM1_TCS_EN BIT(21)
|
||||
#define RAMIPS_GDM1_UCS_EN BIT(20)
|
||||
#define RAMIPS_GDM1_JMB_EN BIT(19)
|
||||
#define RAMIPS_GDM1_STRPCRC BIT(16)
|
||||
#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12)
|
||||
#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12)
|
||||
#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12)
|
||||
|
||||
/* checksums */
|
||||
#define RAMIPS_ICS_GEN_EN BIT(2)
|
||||
#define RAMIPS_UCS_GEN_EN BIT(1)
|
||||
#define RAMIPS_TCS_GEN_EN BIT(0)
|
||||
|
||||
/* dma ring */
|
||||
#define RAMIPS_PST_DRX_IDX0 BIT(16)
|
||||
#define RAMIPS_PST_DTX_IDX3 BIT(3)
|
||||
#define RAMIPS_PST_DTX_IDX2 BIT(2)
|
||||
#define RAMIPS_PST_DTX_IDX1 BIT(1)
|
||||
#define RAMIPS_PST_DTX_IDX0 BIT(0)
|
||||
|
||||
#define RAMIPS_TX_WB_DDONE BIT(6)
|
||||
#define RAMIPS_RX_DMA_BUSY BIT(3)
|
||||
#define RAMIPS_TX_DMA_BUSY BIT(1)
|
||||
#define RAMIPS_RX_DMA_EN BIT(2)
|
||||
#define RAMIPS_TX_DMA_EN BIT(0)
|
||||
|
||||
#define RAMIPS_PDMA_SIZE_4DWORDS (0 << 4)
|
||||
#define RAMIPS_PDMA_SIZE_8DWORDS (1 << 4)
|
||||
#define RAMIPS_PDMA_SIZE_16DWORDS (2 << 4)
|
||||
|
||||
#define RAMIPS_US_CYC_CNT_MASK 0xff
|
||||
#define RAMIPS_US_CYC_CNT_SHIFT 0x8
|
||||
#define RAMIPS_US_CYC_CNT_DIVISOR 1000000
|
||||
|
||||
#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
|
||||
#define RX_DMA_LSO BIT(30)
|
||||
#define RX_DMA_DONE BIT(31)
|
||||
|
||||
struct ramips_rx_dma {
|
||||
unsigned int rxd1;
|
||||
unsigned int rxd2;
|
||||
unsigned int rxd3;
|
||||
unsigned int rxd4;
|
||||
} __packed __aligned(4);
|
||||
|
||||
#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
|
||||
#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
|
||||
#define TX_DMA_LSO BIT(30)
|
||||
#define TX_DMA_DONE BIT(31)
|
||||
#define TX_DMA_QN(_x) ((_x) << 16)
|
||||
#define TX_DMA_PN(_x) ((_x) << 24)
|
||||
#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
|
||||
#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
|
||||
|
||||
struct ramips_tx_dma {
|
||||
unsigned int txd1;
|
||||
unsigned int txd2;
|
||||
unsigned int txd3;
|
||||
unsigned int txd4;
|
||||
} __packed __aligned(4);
|
||||
|
||||
struct raeth_priv
|
||||
{
|
||||
dma_addr_t rx_desc_dma;
|
||||
struct tasklet_struct rx_tasklet;
|
||||
struct ramips_rx_dma *rx;
|
||||
struct sk_buff *rx_skb[NUM_RX_DESC];
|
||||
dma_addr_t rx_dma[NUM_RX_DESC];
|
||||
|
||||
dma_addr_t tx_desc_dma;
|
||||
struct tasklet_struct tx_housekeeping_tasklet;
|
||||
struct ramips_tx_dma *tx;
|
||||
struct sk_buff *tx_skb[NUM_TX_DESC];
|
||||
|
||||
unsigned int skb_free_idx;
|
||||
|
||||
spinlock_t page_lock;
|
||||
struct net_device *netdev;
|
||||
struct device *parent;
|
||||
struct ramips_eth_platform_data *plat;
|
||||
|
||||
int link;
|
||||
int speed;
|
||||
int duplex;
|
||||
int tx_fc;
|
||||
int rx_fc;
|
||||
|
||||
struct mii_bus *mii_bus;
|
||||
int mii_irq[PHY_MAX_ADDR];
|
||||
struct phy_device *phy_dev;
|
||||
spinlock_t phy_lock;
|
||||
};
|
||||
|
||||
#endif /* RAMIPS_ETH_H */
|
||||
Reference in New Issue
Block a user