mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 11:55:30 +02:00
[s3c24xx] glamo-mci: Cleanup mmc clock rate control.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16936 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
fae902def7
commit
3bbf9530b1
@ -76,6 +76,7 @@ struct reg_range {
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char *name;
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char dump;
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};
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struct reg_range reg_range[] = {
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{ 0x0000, 0x76, "General", 1 },
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{ 0x0200, 0x18, "Host Bus", 1 },
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@ -86,7 +87,7 @@ struct reg_range reg_range[] = {
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/* { 0x0c00, 0xcc, "MPEG", 0 }, */
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{ 0x1100, 0xb2, "LCD 1", 1 },
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{ 0x1200, 0x64, "LCD 2", 1 },
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{ 0x1400, 0x40, "MMC", 1 },
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{ 0x1400, 0x42, "MMC", 1 },
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/* { 0x1500, 0x080, "MPU 0", 0 },
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{ 0x1580, 0x080, "MPU 1", 0 },
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{ 0x1600, 0x080, "Cmd Queue", 0 },
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@ -478,7 +479,7 @@ int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
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break;
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case GLAMO_ENGINE_2D:
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__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
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GLAMO_CLOCK_2D_EN_M7CLK |
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GLAMO_CLOCK_2D_EN_M7CLK |
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GLAMO_CLOCK_2D_EN_GCLK |
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GLAMO_CLOCK_2D_DG_M7CLK |
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GLAMO_CLOCK_2D_DG_GCLK,
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@ -544,7 +545,40 @@ u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
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}
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EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
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struct glamo_script reset_regs[] = {
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static const struct glamo_script engine_div_regs[__NUM_GLAMO_ENGINES] = {
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[GLAMO_ENGINE_LCD] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_DCLK},
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[GLAMO_ENGINE_MMC] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_TCLK},
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[GLAMO_ENGINE_2D] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_GCLK},
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};
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void glamo_engine_div_enable(struct glamo_core *glamo, enum glamo_engine engine)
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{
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uint16_t reg = engine_div_regs[engine].reg;
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uint16_t bit = engine_div_regs[engine].val;
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uint16_t val;
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spin_lock(&glamo->lock);
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val = __reg_read(glamo, reg);
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__reg_write(glamo, reg, val | bit);
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spin_unlock(&glamo->lock);
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mdelay(5);
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}
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EXPORT_SYMBOL_GPL(glamo_engine_div_enable);
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void glamo_engine_div_disable(struct glamo_core *glamo, enum glamo_engine engine)
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{
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uint16_t reg = engine_div_regs[engine].reg;
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uint16_t bit = engine_div_regs[engine].val;
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uint16_t val;
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spin_lock(&glamo->lock);
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val = __reg_read(glamo, reg);
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__reg_write(glamo, reg, val & ~bit);
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spin_unlock(&glamo->lock);
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}
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EXPORT_SYMBOL_GPL(glamo_engine_div_disable);
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static const struct glamo_script reset_regs[] = {
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[GLAMO_ENGINE_LCD] = {
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GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
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},
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@ -572,18 +606,18 @@ struct glamo_script reset_regs[] = {
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void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
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{
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struct glamo_script *rst;
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uint16_t reg = reset_regs[engine].reg;
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uint16_t val = reset_regs[engine].val;
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if (engine >= ARRAY_SIZE(reset_regs)) {
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dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
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return;
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}
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rst = &reset_regs[engine];
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spin_lock(&glamo->lock);
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__reg_set_bit(glamo, rst->reg, rst->val);
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__reg_clear_bit(glamo, rst->reg, rst->val);
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__reg_set_bit(glamo, reg, val);
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__reg_clear_bit(glamo, reg, val);
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spin_unlock(&glamo->lock);
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}
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EXPORT_SYMBOL_GPL(glamo_engine_reset);
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@ -599,21 +633,12 @@ void glamo_lcm_reset(struct platform_device *pdev, int level)
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}
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EXPORT_SYMBOL_GPL(glamo_lcm_reset);
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enum glamo_pll {
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GLAMO_PLL1,
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GLAMO_PLL2,
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};
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static int glamo_pll_rate(struct glamo_core *glamo,
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int glamo_pll_rate(struct glamo_core *glamo,
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enum glamo_pll pll)
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{
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u_int16_t reg;
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unsigned int div = 512;
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unsigned int osci = glamo->pdata->osci_clock_rate;
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if (osci == 32768)
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div = 1;
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switch (pll) {
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case GLAMO_PLL1:
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reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
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@ -624,18 +649,19 @@ static int glamo_pll_rate(struct glamo_core *glamo,
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default:
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return -EINVAL;
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}
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return (osci/div)*reg;
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return osci*reg;
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}
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EXPORT_SYMBOL_GPL(glamo_pll_rate);
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int glamo_engine_reclock(struct glamo_core *glamo,
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enum glamo_engine engine,
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int ps)
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int hz)
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{
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int pll, khz;
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u_int16_t reg, mask, val = 0;
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int pll;
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u_int16_t reg, mask, div;
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if (!ps)
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return 0;
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if (!hz)
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return -EINVAL;
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switch (engine) {
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case GLAMO_ENGINE_LCD:
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@ -643,6 +669,11 @@ int glamo_engine_reclock(struct glamo_core *glamo,
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reg = GLAMO_REG_CLOCK_GEN7;
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mask = 0xff;
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break;
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case GLAMO_ENGINE_MMC:
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pll = GLAMO_PLL1;
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reg = GLAMO_REG_CLOCK_GEN8;
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mask = 0xff;
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break;
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default:
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dev_warn(&glamo->pdev->dev,
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"reclock of engine 0x%x not supported\n", engine);
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@ -651,23 +682,22 @@ int glamo_engine_reclock(struct glamo_core *glamo,
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}
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pll = glamo_pll_rate(glamo, pll);
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khz = 1000000000UL / ps;
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if (khz)
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val = (pll / khz) / 1000;
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div = pll / hz;
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if (div != 0 && pll / div <= hz)
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--div;
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if (div > mask)
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div = mask;
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dev_dbg(&glamo->pdev->dev,
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"PLL %d, kHZ %d, div %d\n", pll, khz, val);
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"PLL %d, kHZ %d, div %d\n", pll, hz / 1000, div);
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if (val) {
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val--;
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reg_set_bit_mask(glamo, reg, mask, val);
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mdelay(5); /* wait some time to stabilize */
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reg_set_bit_mask(glamo, reg, mask, div);
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mdelay(5); /* wait some time to stabilize */
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return 0;
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} else {
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return -EINVAL;
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}
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return pll / (div + 1);
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}
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EXPORT_SYMBOL_GPL(glamo_engine_reclock);
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@ -675,7 +705,7 @@ EXPORT_SYMBOL_GPL(glamo_engine_reclock);
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* script support
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***********************************************************************/
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int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
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int glamo_run_script(struct glamo_core *glamo, const struct glamo_script *script,
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int len, int may_sleep)
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{
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int i;
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@ -746,7 +776,7 @@ int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
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}
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EXPORT_SYMBOL(glamo_run_script);
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static struct glamo_script glamo_init_script[] = {
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static const struct glamo_script glamo_init_script[] = {
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{ GLAMO_REG_CLOCK_HOST, 0x1000 },
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{ 0xfffe, 2 },
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{ GLAMO_REG_CLOCK_MEMORY, 0x1000 },
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@ -17,6 +17,11 @@
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#define GLAMO_MMC_BUFFER_SIZE (64 * 1024)
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#define GLAMO_FB_SIZE (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE)
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enum glamo_pll {
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GLAMO_PLL1,
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GLAMO_PLL2,
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};
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struct glamo_core {
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int irq;
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int irq_works; /* 0 means PCB does not support Glamo IRQ */
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@ -38,8 +43,14 @@ struct glamo_script {
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u_int16_t val;
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};
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void glamo_engine_div_enable(struct glamo_core *glamo, enum glamo_engine engine);
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void glamo_engine_div_disable(struct glamo_core *glamo, enum glamo_engine engine);
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int glamo_pll_rate(struct glamo_core *glamo, enum glamo_pll pll);
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int glamo_run_script(struct glamo_core *glamo,
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struct glamo_script *script, int len, int may_sleep);
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const struct glamo_script *script, int len, int may_sleep);
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int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine);
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int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine);
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@ -321,7 +321,7 @@ static void glamofb_program_mode(struct glamofb_handle* gfb) {
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if (var->pixclock)
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glamo_engine_reclock(gcore,
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GLAMO_ENGINE_LCD,
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gfb->fb->var.pixclock);
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(1000000000UL / gfb->fb->var.pixclock) * 1000);
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reg_set_bit_mask(gfb,
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GLAMO_REG_LCD_WIDTH,
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@ -23,15 +23,41 @@
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#include <linux/crc7.h>
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#include <linux/scatterlist.h>
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#include <linux/io.h>
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#include <linux/regulator/consumer.h>
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#include <linux/mfd/glamo.h>
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#include "glamo-mci.h"
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#include "glamo-core.h"
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#include "glamo-regs.h"
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#define DRIVER_NAME "glamo-mci"
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static void glamo_mci_send_request(struct mmc_host *mmc);
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struct glamo_mci_host {
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struct platform_device *pdev;
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struct glamo_mmc_platform_data *pdata;
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struct mmc_host *mmc;
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struct resource *mmio_mem;
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struct resource *data_mem;
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void __iomem *mmio_base;
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u16 __iomem *data_base;
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struct regulator *regulator;
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struct mmc_request *mrq;
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unsigned int clk_rate;
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unsigned short vdd;
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char power_mode;
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unsigned char request_counter;
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struct timer_list disable_timer;
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struct work_struct irq_work;
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unsigned clk_enabled : 1;
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};
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static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request* mrq);
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static void glamo_mci_send_command(struct glamo_mci_host *host,
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struct mmc_command *cmd);
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@ -48,7 +74,7 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
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* for example
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*/
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static int sd_max_clk = 50000000 / 3;
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static int sd_max_clk = 50000000;
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module_param(sd_max_clk, int, 0644);
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/*
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@ -85,35 +111,6 @@ static int sd_post_power_clock = 1000000;
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module_param(sd_post_power_clock, int, 0644);
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/*
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* SD Signal drive strength
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*
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* you can override this on kernel commandline using
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*
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* glamo_mci.sd_drive=0
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*
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* for example
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*/
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static int sd_drive;
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module_param(sd_drive, int, 0644);
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/*
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* SD allow SD clock to run while idle
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*
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* you can override this on kernel commandline using
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*
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* glamo_mci.sd_idleclk=0
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*
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* for example
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*/
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static int sd_idleclk = 0; /* disallow idle clock by default */
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module_param(sd_idleclk, int, 0644);
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/* used to stash real idleclk state in suspend: we force it to run in there */
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static int suspend_sd_idleclk;
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static inline void glamo_reg_write(struct glamo_mci_host *glamo,
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u_int16_t reg, u_int16_t val)
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{
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@ -140,11 +137,34 @@ static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
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glamo_reg_write(glamo, reg, tmp);
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}
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static void do_pio_read(struct glamo_mci_host *host)
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static void glamo_mci_clock_disable(struct glamo_mci_host *host) {
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if (host->clk_enabled) {
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/* glamo_engine_div_disable(host->pdata->core, GLAMO_ENGINE_MMC);*/
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host->clk_enabled = 0;
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printk("clk disabled\n");
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}
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}
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static void glamo_mci_clock_enable(struct glamo_mci_host *host) {
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del_timer_sync(&host->disable_timer);
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if (!host->clk_enabled) {
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glamo_engine_div_enable(host->pdata->core, GLAMO_ENGINE_MMC);
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host->clk_enabled = 1;
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printk("clk enabled\n");
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}
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}
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static void glamo_mci_disable_timer(unsigned long data) {
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struct glamo_mci_host *host = (struct glamo_mci_host *)data;
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glamo_mci_clock_disable(host);
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}
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static void do_pio_read(struct glamo_mci_host *host, struct mmc_data *data)
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{
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struct scatterlist *sg;
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u16 __iomem *from_ptr = host->data_base;
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struct mmc_data *data = host->mrq->data;
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void *sg_pointer;
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dev_dbg(&host->pdev->dev, "pio_read():\n");
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@ -159,14 +179,13 @@ static void do_pio_read(struct glamo_mci_host *host)
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}
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dev_dbg(&host->pdev->dev, "pio_read(): "
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"complete (no more data).\n");
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"complete (no more data).\n");
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}
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static void do_pio_write(struct glamo_mci_host *host)
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static void do_pio_write(struct glamo_mci_host *host, struct mmc_data *data)
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{
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struct scatterlist *sg;
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u16 __iomem *to_ptr = host->data_base;
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struct mmc_data *data = host->mrq->data;
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void *sg_pointer;
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dev_dbg(&host->pdev->dev, "pio_write():\n");
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@ -182,117 +201,41 @@ static void do_pio_write(struct glamo_mci_host *host)
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dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
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}
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static void glamo_mci_fix_card_div(struct glamo_mci_host *host, int div)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->pdata->core->lock, flags);
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if (div < 0) {
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/* stop clock - remove clock from divider input */
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writew(readw(host->pdata->core->base +
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GLAMO_REG_CLOCK_GEN5_1) & (~GLAMO_CLOCK_GEN51_EN_DIV_TCLK),
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host->pdata->core->base + GLAMO_REG_CLOCK_GEN5_1);
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} else {
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if (host->force_slow_during_powerup)
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div = host->clk_rate / sd_post_power_clock;
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else if (host->pdata->glamo_mmc_use_slow &&
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host->pdata->glamo_mmc_use_slow())
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div = div * sd_slow_ratio;
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if (div > 255)
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div = 255;
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/*
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* set the nearest prescaler factor
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*
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* register shared with SCLK divisor -- no chance of race because
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* we don't use sensor interface
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*/
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writew((readw(host->pdata->core->base +
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GLAMO_REG_CLOCK_GEN8) & 0xff00) | div,
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host->pdata->core->base + GLAMO_REG_CLOCK_GEN8);
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/* enable clock to divider input */
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writew(readw(host->pdata->core->base +
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GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
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host->pdata->core->base + GLAMO_REG_CLOCK_GEN5_1);
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}
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spin_unlock_irqrestore(&host->pdata->core->lock, flags);
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mdelay(5);
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}
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static int glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq)
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{
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int div = 0;
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int real_rate = 0;
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if (freq) {
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/* Set clock */
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for (div = 0; div < 255; div++) {
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real_rate = host->clk_rate / (div + 1);
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if (real_rate <= freq)
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break;
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}
|
||||
|
||||
host->clk_div = div;
|
||||
glamo_mci_fix_card_div(host, div);
|
||||
glamo_mci_clock_enable(host);
|
||||
real_rate = glamo_engine_reclock(host->pdata->core, GLAMO_ENGINE_MMC, freq);
|
||||
} else {
|
||||
/* stop clock */
|
||||
host->clk_div = 0xff;
|
||||
|
||||
if (!sd_idleclk && !host->force_slow_during_powerup)
|
||||
/* clock off */
|
||||
glamo_mci_fix_card_div(host, -1);
|
||||
glamo_mci_clock_disable(host);
|
||||
}
|
||||
host->real_rate = real_rate;
|
||||
|
||||
return real_rate;
|
||||
}
|
||||
|
||||
static void glamo_mci_request_done(struct glamo_mci_host *host, struct
|
||||
mmc_request *mrq) {
|
||||
mod_timer(&host->disable_timer, jiffies + HZ / 16);
|
||||
|
||||
mmc_request_done(host->mmc, mrq);
|
||||
}
|
||||
|
||||
|
||||
static void glamo_mci_irq_worker(struct work_struct *work)
|
||||
{
|
||||
struct glamo_mci_host *host =
|
||||
container_of(work, struct glamo_mci_host, irq_work);
|
||||
struct mmc_command *cmd = host->mrq->cmd;
|
||||
|
||||
if (cmd->data->flags & MMC_DATA_READ) {
|
||||
do_pio_read(host);
|
||||
}
|
||||
|
||||
/* issue STOP if we have been given one to use */
|
||||
if (host->mrq->stop) {
|
||||
glamo_mci_send_command(host, host->mrq->stop);
|
||||
}
|
||||
|
||||
if (!sd_idleclk && !host->force_slow_during_powerup)
|
||||
/* clock off */
|
||||
glamo_mci_fix_card_div(host, -1);
|
||||
|
||||
host->mrq = NULL;
|
||||
mmc_request_done(host->mmc, cmd->mrq);
|
||||
}
|
||||
|
||||
static irqreturn_t glamo_mci_irq(int irq, void *devid)
|
||||
{
|
||||
struct glamo_mci_host *host = (struct glamo_mci_host*)devid;
|
||||
u16 status;
|
||||
struct glamo_mci_host *host = container_of(work, struct glamo_mci_host,
|
||||
irq_work);
|
||||
struct mmc_command *cmd;
|
||||
unsigned long flags;
|
||||
uint16_t status;
|
||||
|
||||
if (host->suspending) { /* bad news, dangerous time */
|
||||
dev_err(&host->pdev->dev, "****glamo_mci_irq before resumed\n");
|
||||
goto leave;
|
||||
}
|
||||
if (!host->mrq || !host->mrq->cmd)
|
||||
return;
|
||||
|
||||
if (!host->mrq)
|
||||
goto leave;
|
||||
cmd = host->mrq->cmd;
|
||||
if (!cmd)
|
||||
goto leave;
|
||||
|
||||
spin_lock_irqsave(&host->lock, flags);
|
||||
|
||||
status = readw(host->mmio_base + GLAMO_REG_MMC_RB_STAT1);
|
||||
status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
|
||||
dev_dbg(&host->pdev->dev, "status = 0x%04x\n", status);
|
||||
|
||||
/* we ignore a data timeout report if we are also told the data came */
|
||||
@ -300,36 +243,34 @@ static irqreturn_t glamo_mci_irq(int irq, void *devid)
|
||||
status &= ~GLAMO_STAT1_MMC_DTOUT;
|
||||
|
||||
if (status & (GLAMO_STAT1_MMC_RTOUT |
|
||||
GLAMO_STAT1_MMC_DTOUT))
|
||||
GLAMO_STAT1_MMC_DTOUT))
|
||||
cmd->error = -ETIMEDOUT;
|
||||
if (status & (GLAMO_STAT1_MMC_BWERR |
|
||||
GLAMO_STAT1_MMC_BRERR))
|
||||
GLAMO_STAT1_MMC_BRERR))
|
||||
cmd->error = -EILSEQ;
|
||||
if (cmd->error) {
|
||||
dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
|
||||
goto done;
|
||||
}
|
||||
|
||||
/*
|
||||
* disable the initial slow start after first bulk transfer
|
||||
*/
|
||||
if (host->force_slow_during_powerup)
|
||||
host->force_slow_during_powerup--;
|
||||
/* issue STOP if we have been given one to use */
|
||||
if (host->mrq->stop)
|
||||
glamo_mci_send_command(host, host->mrq->stop);
|
||||
|
||||
/*
|
||||
* we perform the memcpy out of Glamo memory outside of IRQ context
|
||||
* so we don't block other interrupts
|
||||
*/
|
||||
schedule_work(&host->irq_work);
|
||||
|
||||
goto unlock;
|
||||
if (cmd->data->flags & MMC_DATA_READ)
|
||||
do_pio_read(host, cmd->data);
|
||||
|
||||
done:
|
||||
host->mrq = NULL;
|
||||
mmc_request_done(host->mmc, cmd->mrq);
|
||||
unlock:
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
leave:
|
||||
glamo_mci_request_done(host, cmd->mrq);
|
||||
}
|
||||
|
||||
static irqreturn_t glamo_mci_irq(int irq, void *devid)
|
||||
{
|
||||
struct glamo_mci_host *host = (struct glamo_mci_host*)devid;
|
||||
|
||||
schedule_work(&host->irq_work);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
@ -341,13 +282,12 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
|
||||
unsigned int timeout = 1000000;
|
||||
u16 * reg_resp = (u16 *)(host->mmio_base + GLAMO_REG_MMC_CMD_RSP1);
|
||||
u16 status;
|
||||
int triggers_int = 1;
|
||||
|
||||
/* if we can't do it, reject as busy */
|
||||
if (!readw(host->mmio_base + GLAMO_REG_MMC_RB_STAT1) &
|
||||
GLAMO_STAT1_MMC_IDLE) {
|
||||
host->mrq = NULL;
|
||||
if (!glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
|
||||
GLAMO_STAT1_MMC_IDLE) {
|
||||
cmd->error = -EBUSY;
|
||||
mmc_request_done(host->mmc, host->mrq);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -360,9 +300,9 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
|
||||
u8a[5] = (crc7(0, u8a, 5) << 1) | 0x01; /* crc7 on first 5 bytes of packet */
|
||||
|
||||
/* issue the wire-order array including CRC in register order */
|
||||
writew((u8a[4] << 8) | u8a[5], host->mmio_base + GLAMO_REG_MMC_CMD_REG1);
|
||||
writew((u8a[2] << 8) | u8a[3], host->mmio_base + GLAMO_REG_MMC_CMD_REG2);
|
||||
writew((u8a[0] << 8) | u8a[1], host->mmio_base + GLAMO_REG_MMC_CMD_REG3);
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
|
||||
|
||||
/* command index toggle */
|
||||
fire |= (host->request_counter & 1) << 12;
|
||||
@ -440,27 +380,36 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
|
||||
/* multiblock with stop */
|
||||
fire |= GLAMO_FIRE_MMC_CC_MBWS;
|
||||
else
|
||||
/* multiblock NO stop-- 'RESERVED'? */
|
||||
/* multiblock NO stop-- 'RESERVED'? */
|
||||
fire |= GLAMO_FIRE_MMC_CC_MBWNS;
|
||||
break;
|
||||
case MMC_STOP_TRANSMISSION:
|
||||
fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
|
||||
triggers_int = 0;
|
||||
break;
|
||||
default:
|
||||
fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
|
||||
triggers_int = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (triggers_int)
|
||||
host->mrq = cmd->mrq;
|
||||
|
||||
/* always largest timeout */
|
||||
writew(0xfff, host->mmio_base + GLAMO_REG_MMC_TIMEOUT);
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
|
||||
|
||||
/* Generate interrupt on txfer */
|
||||
glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, ~0x3e,
|
||||
0x0800 | GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
|
||||
GLAMO_BASIC_MMC_EN_COMPL_INT | (sd_drive << 6));
|
||||
glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
|
||||
0x0800 |
|
||||
GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
|
||||
GLAMO_BASIC_MMC_EN_COMPL_INT |
|
||||
GLAMO_BASIC_MMC_EN_DATA_PUPS |
|
||||
GLAMO_BASIC_MMC_EN_CMD_PUP);
|
||||
|
||||
/* send the command out on the wire */
|
||||
/* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
|
||||
writew(fire, host->mmio_base + GLAMO_REG_MMC_CMD_FIRE);
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
|
||||
|
||||
/* we are deselecting card? because it isn't going to ack then... */
|
||||
if ((cmd->opcode == 7) && (cmd->arg == 0))
|
||||
@ -470,15 +419,14 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
|
||||
* we must spin until response is ready or timed out
|
||||
* -- we don't get interrupts unless there is a bulk rx
|
||||
*/
|
||||
udelay(5);
|
||||
do
|
||||
status = readw(host->mmio_base + GLAMO_REG_MMC_RB_STAT1);
|
||||
status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
|
||||
while (((((status >> 15) & 1) != (host->request_counter & 1)) ||
|
||||
(!(status & (GLAMO_STAT1_MMC_RB_RRDY |
|
||||
GLAMO_STAT1_MMC_RTOUT |
|
||||
GLAMO_STAT1_MMC_DTOUT |
|
||||
GLAMO_STAT1_MMC_BWERR |
|
||||
GLAMO_STAT1_MMC_BRERR)))) && (timeout--));
|
||||
GLAMO_STAT1_MMC_RTOUT |
|
||||
GLAMO_STAT1_MMC_DTOUT |
|
||||
GLAMO_STAT1_MMC_BWERR |
|
||||
GLAMO_STAT1_MMC_BRERR)))) && (timeout--));
|
||||
|
||||
if ((status & (GLAMO_STAT1_MMC_RTOUT |
|
||||
GLAMO_STAT1_MMC_DTOUT)) ||
|
||||
@ -492,17 +440,17 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
|
||||
if (cmd->flags & MMC_RSP_PRESENT) {
|
||||
if (cmd->flags & MMC_RSP_136) {
|
||||
cmd->resp[3] = readw(®_resp[0]) |
|
||||
(readw(®_resp[1]) << 16);
|
||||
(readw(®_resp[1]) << 16);
|
||||
cmd->resp[2] = readw(®_resp[2]) |
|
||||
(readw(®_resp[3]) << 16);
|
||||
(readw(®_resp[3]) << 16);
|
||||
cmd->resp[1] = readw(®_resp[4]) |
|
||||
(readw(®_resp[5]) << 16);
|
||||
(readw(®_resp[5]) << 16);
|
||||
cmd->resp[0] = readw(®_resp[6]) |
|
||||
(readw(®_resp[7]) << 16);
|
||||
(readw(®_resp[7]) << 16);
|
||||
} else {
|
||||
cmd->resp[0] = (readw(®_resp[0]) >> 8) |
|
||||
(readw(®_resp[1]) << 8) |
|
||||
((readw(®_resp[2])) << 24);
|
||||
(readw(®_resp[1]) << 8) |
|
||||
((readw(®_resp[2])) << 24);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -511,28 +459,63 @@ static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
|
||||
struct mmc_data *data)
|
||||
{
|
||||
/* set up the block info */
|
||||
writew(data->blksz, host->mmio_base + GLAMO_REG_MMC_DATBLKLEN);
|
||||
writew(data->blocks, host->mmio_base + GLAMO_REG_MMC_DATBLKCNT);
|
||||
dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
|
||||
data->blksz, data->blocks);
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
|
||||
|
||||
data->bytes_xfered = 0;
|
||||
|
||||
/* if write, prep the write into the shared RAM before the command */
|
||||
if (data->flags & MMC_DATA_WRITE) {
|
||||
do_pio_write(host);
|
||||
do_pio_write(host, data);
|
||||
}
|
||||
|
||||
dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
|
||||
data->blksz, data->blocks);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void glamo_mci_send_request(struct mmc_host *mmc)
|
||||
static int glamo_mci_irq_poll(struct glamo_mci_host *host,
|
||||
struct mmc_command *cmd)
|
||||
{
|
||||
int timeout = 1000000;
|
||||
/*
|
||||
* if the glamo INT# line isn't wired (*cough* it can happen)
|
||||
* I'm afraid we have to spin on the IRQ status bit and "be
|
||||
* our own INT# line"
|
||||
*/
|
||||
/*
|
||||
* we have faith we will get an "interrupt"...
|
||||
* but something insane like suspend problems can mean
|
||||
* we spin here forever, so we timeout after a LONG time
|
||||
*/
|
||||
while ((!(readw(host->pdata->core->base +
|
||||
GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
|
||||
(timeout--));
|
||||
|
||||
if (timeout < 0) {
|
||||
if (cmd->data->error)
|
||||
cmd->data->error = -ETIMEDOUT;
|
||||
dev_err(&host->pdev->dev, "Payload timeout\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
/* ack this interrupt source */
|
||||
writew(GLAMO_IRQ_MMC, host->pdata->core->base +
|
||||
GLAMO_REG_IRQ_CLEAR);
|
||||
|
||||
/* yay we are an interrupt controller! -- call the ISR
|
||||
* it will stop clock to card
|
||||
*/
|
||||
glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
||||
{
|
||||
struct glamo_mci_host *host = mmc_priv(mmc);
|
||||
struct mmc_request *mrq = host->mrq;
|
||||
struct mmc_command *cmd = mrq->cmd;
|
||||
int timeout = 1000000;
|
||||
|
||||
host->request_counter++;
|
||||
/* this guy has data to read/write? */
|
||||
if (cmd->data) {
|
||||
if(glamo_mci_prepare_pio(host, cmd->data)) {
|
||||
cmd->data->error = -EIO;
|
||||
@ -545,11 +528,7 @@ static void glamo_mci_send_request(struct mmc_host *mmc)
|
||||
cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
|
||||
cmd->flags);
|
||||
|
||||
/* resume requested clock rate
|
||||
* scale it down by sd_slow_ratio if platform requests it
|
||||
*/
|
||||
glamo_mci_fix_card_div(host, host->clk_div);
|
||||
|
||||
glamo_mci_clock_enable(host);
|
||||
glamo_mci_send_command(host, cmd);
|
||||
|
||||
/*
|
||||
@ -558,6 +537,12 @@ static void glamo_mci_send_request(struct mmc_host *mmc)
|
||||
if (!cmd->data || cmd->error)
|
||||
goto done;
|
||||
|
||||
|
||||
if (!host->pdata->core->irq_works) {
|
||||
if (glamo_mci_irq_poll(host, mrq->cmd))
|
||||
goto done;
|
||||
}
|
||||
|
||||
/*
|
||||
* Otherwise can can use the interrupt as async completion --
|
||||
* if there is read data coming, or we wait for write data to complete,
|
||||
@ -565,95 +550,30 @@ static void glamo_mci_send_request(struct mmc_host *mmc)
|
||||
* will service it
|
||||
*/
|
||||
dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
|
||||
/*
|
||||
* if the glamo INT# line isn't wired (*cough* it can happen)
|
||||
* I'm afraid we have to spin on the IRQ status bit and "be
|
||||
* our own INT# line"
|
||||
*/
|
||||
if (!host->pdata->core->irq_works) {
|
||||
/*
|
||||
* we have faith we will get an "interrupt"...
|
||||
* but something insane like suspend problems can mean
|
||||
* we spin here forever, so we timeout after a LONG time
|
||||
*/
|
||||
while ((!(readw(host->pdata->core->base +
|
||||
GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
|
||||
(timeout--));
|
||||
|
||||
if (timeout < 0) {
|
||||
if (cmd->data->error)
|
||||
cmd->data->error = -ETIMEDOUT;
|
||||
dev_err(&host->pdev->dev, "Payload timeout\n");
|
||||
goto bail;
|
||||
}
|
||||
/* ack this interrupt source */
|
||||
writew(GLAMO_IRQ_MMC, host->pdata->core->base +
|
||||
GLAMO_REG_IRQ_CLEAR);
|
||||
|
||||
/* yay we are an interrupt controller! -- call the ISR
|
||||
* it will stop clock to card
|
||||
*/
|
||||
glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
|
||||
}
|
||||
return;
|
||||
done:
|
||||
host->mrq = NULL;
|
||||
mmc_request_done(host->mmc, cmd->mrq);
|
||||
bail:
|
||||
if (!sd_idleclk && !host->force_slow_during_powerup)
|
||||
/* stop the clock to card */
|
||||
glamo_mci_fix_card_div(host, -1);
|
||||
glamo_mci_request_done(host, mrq);
|
||||
}
|
||||
|
||||
static void glamo_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
||||
{
|
||||
struct glamo_mci_host *host = mmc_priv(mmc);
|
||||
|
||||
host->mrq = mrq;
|
||||
glamo_mci_send_request(mmc);
|
||||
}
|
||||
|
||||
static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
||||
{
|
||||
struct glamo_mci_host *host = mmc_priv(mmc);
|
||||
int bus_width = 0;
|
||||
int powering = 0;
|
||||
static void glamo_mci_set_power_mode(struct glamo_mci_host *host,
|
||||
unsigned char power_mode) {
|
||||
int ret;
|
||||
|
||||
if (host->suspending) {
|
||||
dev_err(&host->pdev->dev, "IGNORING glamo_mci_set_ios while "
|
||||
"suspended\n");
|
||||
if (power_mode == host->power_mode)
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set power */
|
||||
switch(ios->power_mode) {
|
||||
switch(power_mode) {
|
||||
case MMC_POWER_UP:
|
||||
ret = regulator_enable(host->regulator);
|
||||
if (ret)
|
||||
dev_err(&host->pdev->dev, "Failed to enable regulator: %d\n", ret);
|
||||
break;
|
||||
case MMC_POWER_ON:
|
||||
/*
|
||||
* we should use very slow clock until first bulk
|
||||
* transfer completes OK
|
||||
*/
|
||||
host->force_slow_during_powerup = 1;
|
||||
|
||||
if (host->power_mode_current == MMC_POWER_OFF) {
|
||||
glamo_engine_enable(host->pdata->core,
|
||||
GLAMO_ENGINE_MMC);
|
||||
powering = 1;
|
||||
if (host->power_mode == MMC_POWER_OFF) {
|
||||
ret = regulator_enable(host->regulator);
|
||||
if (ret)
|
||||
dev_err(&host->pdev->dev, "Failed to enable regulator: %d\n", ret);
|
||||
}
|
||||
break;
|
||||
|
||||
case MMC_POWER_ON:
|
||||
break;
|
||||
case MMC_POWER_OFF:
|
||||
default:
|
||||
if (host->power_mode_current == MMC_POWER_OFF)
|
||||
break;
|
||||
/* never want clocking with dead card */
|
||||
glamo_mci_fix_card_div(host, -1);
|
||||
|
||||
glamo_engine_disable(host->pdata->core,
|
||||
GLAMO_ENGINE_MMC);
|
||||
|
||||
@ -662,44 +582,50 @@ static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
||||
dev_warn(&host->pdev->dev, "Failed to disable regulator: %d\n", ret);
|
||||
break;
|
||||
}
|
||||
host->power_mode_current = ios->power_mode;
|
||||
host->power_mode = power_mode;
|
||||
}
|
||||
|
||||
if (host->vdd_current != ios->vdd) {
|
||||
static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
||||
{
|
||||
struct glamo_mci_host *host = mmc_priv(mmc);
|
||||
int bus_width = 0;
|
||||
int rate;
|
||||
int sd_drive;
|
||||
int ret;
|
||||
|
||||
/* Set power */
|
||||
glamo_mci_set_power_mode(host, ios->power_mode);
|
||||
|
||||
if (host->vdd != ios->vdd) {
|
||||
ret = mmc_regulator_set_ocr(host->regulator, ios->vdd);
|
||||
if (ret)
|
||||
dev_err(&host->pdev->dev, "Failed to set regulator voltage: %d\n", ret);
|
||||
else
|
||||
host->vdd_current = ios->vdd;
|
||||
host->vdd = ios->vdd;
|
||||
}
|
||||
glamo_mci_set_card_clock(host, ios->clock);
|
||||
|
||||
/* after power-up, we are meant to give it >= 74 clocks so it can
|
||||
* initialize itself. Doubt any modern cards need it but anyway...
|
||||
*/
|
||||
if (powering)
|
||||
mdelay(1);
|
||||
|
||||
if (!sd_idleclk && !host->force_slow_during_powerup)
|
||||
/* stop the clock to card, because we are idle until transfer */
|
||||
glamo_mci_fix_card_div(host, -1);
|
||||
rate = glamo_mci_set_card_clock(host, ios->clock);
|
||||
|
||||
if ((ios->power_mode == MMC_POWER_ON) ||
|
||||
(ios->power_mode == MMC_POWER_UP)) {
|
||||
dev_info(&host->pdev->dev,
|
||||
"powered (vdd = %d) clk: %lukHz div=%d (req: %ukHz). "
|
||||
"Bus width=%d\n",(int)ios->vdd,
|
||||
host->real_rate / 1000, (int)host->clk_div,
|
||||
"powered (vdd = %hu) clk: %dkHz div=%hu (req: %ukHz). "
|
||||
"Bus width=%d\n", ios->vdd,
|
||||
rate / 1000, 0,
|
||||
ios->clock / 1000, (int)ios->bus_width);
|
||||
} else
|
||||
} else {
|
||||
dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
|
||||
}
|
||||
|
||||
/* set bus width */
|
||||
if (ios->bus_width == MMC_BUS_WIDTH_4)
|
||||
bus_width = GLAMO_BASIC_MMC_EN_4BIT_DATA;
|
||||
|
||||
sd_drive = (rate * 4) / host->clk_rate;
|
||||
if (sd_drive > 3)
|
||||
sd_drive = 3;
|
||||
|
||||
glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
|
||||
GLAMO_BASIC_MMC_EN_4BIT_DATA |
|
||||
GLAMO_BASIC_MMC_EN_DR_STR0 |
|
||||
GLAMO_BASIC_MMC_EN_DR_STR1,
|
||||
GLAMO_BASIC_MMC_EN_4BIT_DATA | 0xb0,
|
||||
bus_width | sd_drive << 6);
|
||||
}
|
||||
|
||||
@ -713,7 +639,7 @@ static int glamo_mci_get_ro(struct mmc_host *mmc)
|
||||
}
|
||||
|
||||
static struct mmc_host_ops glamo_mci_ops = {
|
||||
.request = glamo_mci_request,
|
||||
.request = glamo_mci_send_request,
|
||||
.set_ios = glamo_mci_set_ios,
|
||||
.get_ro = glamo_mci_get_ro,
|
||||
};
|
||||
@ -736,9 +662,9 @@ static int glamo_mci_probe(struct platform_device *pdev)
|
||||
host->mmc = mmc;
|
||||
host->pdev = pdev;
|
||||
host->pdata = pdev->dev.platform_data;
|
||||
host->power_mode_current = MMC_POWER_OFF;
|
||||
host->power_mode = MMC_POWER_OFF;
|
||||
host->clk_enabled = 0;
|
||||
|
||||
spin_lock_init(&host->lock);
|
||||
INIT_WORK(&host->irq_work, glamo_mci_irq_worker);
|
||||
|
||||
host->regulator = regulator_get(pdev->dev.parent, "SD_3V3");
|
||||
@ -810,9 +736,8 @@ static int glamo_mci_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
|
||||
host->vdd_current = 0;
|
||||
host->clk_rate = 50000000; /* really it's 49152000 */
|
||||
host->clk_div = 16;
|
||||
host->vdd = 0;
|
||||
host->clk_rate = glamo_pll_rate(host->pdata->core, GLAMO_PLL1);
|
||||
|
||||
/* explain our host controller capabilities */
|
||||
mmc->ops = &glamo_mci_ops;
|
||||
@ -821,7 +746,7 @@ static int glamo_mci_probe(struct platform_device *pdev)
|
||||
MMC_CAP_MMC_HIGHSPEED |
|
||||
MMC_CAP_SD_HIGHSPEED;
|
||||
mmc->f_min = host->clk_rate / 256;
|
||||
mmc->f_max = sd_max_clk;
|
||||
mmc->f_max = host->clk_rate;
|
||||
|
||||
mmc->max_blk_count = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
|
||||
mmc->max_blk_size = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
|
||||
@ -841,21 +766,24 @@ static int glamo_mci_probe(struct platform_device *pdev)
|
||||
glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
|
||||
glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
|
||||
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
|
||||
(u16)(host->data_mem->start));
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
|
||||
(u16)(host->data_mem->start >> 16));
|
||||
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
|
||||
(u16)(host->data_mem->start));
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
|
||||
(u16)(host->data_mem->start >> 16));
|
||||
|
||||
setup_timer(&host->disable_timer, glamo_mci_disable_timer,
|
||||
(unsigned long)host);
|
||||
|
||||
if ((ret = mmc_add_host(mmc))) {
|
||||
dev_err(&pdev->dev, "failed to add mmc host.\n");
|
||||
goto probe_freeirq;
|
||||
}
|
||||
|
||||
writew((u16)(host->data_mem->start),
|
||||
host->mmio_base + GLAMO_REG_MMC_WDATADS1);
|
||||
writew((u16)((host->data_mem->start) >> 16),
|
||||
host->mmio_base + GLAMO_REG_MMC_WDATADS2);
|
||||
|
||||
writew((u16)host->data_mem->start, host->mmio_base +
|
||||
GLAMO_REG_MMC_RDATADS1);
|
||||
writew((u16)(host->data_mem->start >> 16), host->mmio_base +
|
||||
GLAMO_REG_MMC_RDATADS2);
|
||||
|
||||
dev_info(&pdev->dev,"initialisation done.\n");
|
||||
return 0;
|
||||
|
||||
@ -904,51 +832,41 @@ static int glamo_mci_remove(struct platform_device *pdev)
|
||||
static int glamo_mci_suspend(struct platform_device *dev, pm_message_t state)
|
||||
{
|
||||
struct mmc_host *mmc = platform_get_drvdata(dev);
|
||||
struct glamo_mci_host *host = mmc_priv(mmc);
|
||||
struct glamo_mci_host *host = mmc_priv(mmc);
|
||||
int ret;
|
||||
|
||||
cancel_work_sync(&host->irq_work);
|
||||
|
||||
/*
|
||||
* possible workaround for SD corruption during suspend - resume
|
||||
* make sure the clock was running during suspend and consequently
|
||||
* resume
|
||||
*/
|
||||
glamo_mci_fix_card_div(host, host->clk_div);
|
||||
|
||||
/* we are going to do more commands to override this in
|
||||
* mmc_suspend_host(), so we need to change sd_idleclk for the
|
||||
* duration as well
|
||||
*/
|
||||
suspend_sd_idleclk = sd_idleclk;
|
||||
sd_idleclk = 1;
|
||||
|
||||
ret = mmc_suspend_host(mmc, state);
|
||||
|
||||
host->suspending++;
|
||||
glamo_mci_clock_enable(host);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int glamo_mci_resume(struct platform_device *dev)
|
||||
static int glamo_mci_resume(struct platform_device *dev)
|
||||
{
|
||||
struct mmc_host *mmc = platform_get_drvdata(dev);
|
||||
struct glamo_mci_host *host = mmc_priv(mmc);
|
||||
struct glamo_mci_host *host = mmc_priv(mmc);
|
||||
int ret;
|
||||
|
||||
sd_idleclk = 1;
|
||||
glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
|
||||
glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
|
||||
|
||||
glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
|
||||
glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
|
||||
(u16)(host->data_mem->start));
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
|
||||
(u16)(host->data_mem->start >> 16));
|
||||
|
||||
host->suspending--;
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
|
||||
(u16)(host->data_mem->start));
|
||||
glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
|
||||
(u16)(host->data_mem->start >> 16));
|
||||
mdelay(5);
|
||||
|
||||
ret = mmc_resume_host(mmc);
|
||||
ret = mmc_resume_host(host->mmc);
|
||||
/* glamo_mci_clock_disable(host);*/
|
||||
|
||||
/* put sd_idleclk back to pre-suspend state */
|
||||
sd_idleclk = suspend_sd_idleclk;
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(glamo_mci_resume);
|
||||
|
||||
|
@ -1,43 +0,0 @@
|
||||
/*
|
||||
* linux/drivers/mmc/host/glamo-mmc.h - GLAMO MCI driver
|
||||
*
|
||||
* Copyright (C) 2007-2008 Openmoko, Inc, Andy Green <andy@openmoko.com>
|
||||
* based on S3C MMC driver -->
|
||||
* Copyright (C) 2004-2006 Thomas Kleffel, All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/regulator/consumer.h>
|
||||
|
||||
struct glamo_mci_host {
|
||||
struct platform_device *pdev;
|
||||
struct glamo_mmc_platform_data *pdata;
|
||||
struct mmc_host *mmc;
|
||||
struct resource *mmio_mem;
|
||||
struct resource *data_mem;
|
||||
void __iomem *mmio_base;
|
||||
u16 __iomem *data_base;
|
||||
|
||||
int suspending;
|
||||
|
||||
int power_mode_current;
|
||||
unsigned int vdd_current;
|
||||
|
||||
unsigned long clk_rate;
|
||||
unsigned long clk_div;
|
||||
unsigned long real_rate;
|
||||
|
||||
int force_slow_during_powerup;
|
||||
|
||||
struct mmc_request *mrq;
|
||||
struct work_struct irq_work;
|
||||
|
||||
spinlock_t lock;
|
||||
|
||||
unsigned int request_counter;
|
||||
|
||||
struct regulator *regulator;
|
||||
};
|
Loading…
Reference in New Issue
Block a user