qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00
Code Activity

[xburst] time.c: Timer enable registers are only 8bit width.

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20796 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
lars
2010-04-11 16:24:06 +00:00
parent 8ff8151448
commit 3d00b9bbe1
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
View File

@@ -98,12 +98,12 @@ static void jz4740_init_timer(void)
static void jz4740_timer_enable(unsigned int timer) static void jz4740_timer_enable(unsigned int timer)
{ {
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
} }
static void jz4740_timer_disable(unsigned int timer) static void jz4740_timer_disable(unsigned int timer)
{ {
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
} }