qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00
Code Activity

[lantiq] prepare dsl driver for 3.6 and split fw into a seperate package

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34096 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2012-11-06 07:38:18 +00:00
parent 019f172430
commit 3db2942505
5 changed files with 72 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
package/system/ltq-dsl/src/Makefile
View File

@@ -1,6 +1,8 @@
obj-m = lantiq_mei.o lantiq_atm.o
lantiq_atm-objs := ifxmips_atm_core.o
CFLAGS_MODULE+=-DSOC_TYPE_XWAY
EXTRA_CFLAGS+=-DSOC_TYPE_XWAY
ifeq ($(BUILD_VARIANT),danube)
CFLAGS_MODULE+=-DCONFIG_DANUBE
EXTRA_CFLAGS+=-DCONFIG_DANUBE

1
package/system/ltq-dsl/src/ifxmips_atm_ppe_danube.h
View File

@@ -122,6 +122,7 @@
/*
* Mailbox IGU1 Interrupt
*/
#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
#define PPE_MAILBOX_IGU1_INT LTQ_PPE_MBOX_INT

8
package/system/ltq-dsl/src/lantiq_mei.c
View File

@@ -81,6 +81,14 @@
#define ltq_w32_mask(clear, set, reg) ltq_w32((ltq_r32(reg) & ~clear) | set, reg)
*/
#define LTQ_RCU_BASE_ADDR 0x1F203000
#define LTQ_ICU_BASE_ADDR 0x1F880200
#define LTQ_MEI_BASE_ADDR 0x1E116000
#define LTQ_PMU_BASE_ADDR 0x1F102000
#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
#define LTQ_RCU_RST_REQ_DFE (1 << 7)
#define LTQ_RCU_RST_REQ_AFE (1 << 11)