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[ar71xx] ag71xx driver: use same FIFO configuration for all SOC
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13560 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -38,7 +38,7 @@
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#define ETH_FCS_LEN 4
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#define ETH_FCS_LEN 4
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#define AG71XX_DRV_NAME "ag71xx"
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#define AG71XX_DRV_NAME "ag71xx"
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#define AG71XX_DRV_VERSION "0.5.13"
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#define AG71XX_DRV_VERSION "0.5.14"
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#define AG71XX_NAPI_WEIGHT 64
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#define AG71XX_NAPI_WEIGHT 64
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#define AG71XX_OOM_REFILL (1 + HZ/10)
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#define AG71XX_OOM_REFILL (1 + HZ/10)
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@ -227,7 +227,7 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
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#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
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#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
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#define FIFO_CFG4_FC BIT(2) /* False Carrier */
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#define FIFO_CFG4_FC BIT(2) /* False Carrier */
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#define FIFO_CFG4_CE BIT(3) /* Code Error */
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#define FIFO_CFG4_CE BIT(3) /* Code Error */
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#define FIFO_CFG4_CRC BIT(4) /* CRC error */
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#define FIFO_CFG4_CR BIT(4) /* CRC error */
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#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
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#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
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#define FIFO_CFG4_LO BIT(6) /* Length out of range */
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#define FIFO_CFG4_LO BIT(6) /* Length out of range */
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#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
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#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
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@ -258,6 +258,8 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
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#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
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#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
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#define FIFO_CFG5_LE BIT(14) /* Long Event */
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#define FIFO_CFG5_LE BIT(14) /* Long Event */
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#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
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#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
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#define FIFO_CFG5_16 BIT(16) /* unknown */
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#define FIFO_CFG5_17 BIT(17) /* unknown */
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#define FIFO_CFG5_SF BIT(18) /* Short Frame */
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#define FIFO_CFG5_SF BIT(18) /* Short Frame */
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#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
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#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
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@ -296,17 +296,6 @@ static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
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ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
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ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
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}
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}
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#define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
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MAC_CFG1_SRX | MAC_CFG1_STX)
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#define AR71XX_FIFO_CFG5_INIT 0x0007ffef
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#define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
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MAC_CFG1_SRX | MAC_CFG1_STX | \
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MAC_CFG1_TFC | MAC_CFG1_RFC)
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#define AR91XX_FIFO_CFG5_INIT 0x0007efef
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#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
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static void ag71xx_dma_reset(struct ag71xx *ag)
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static void ag71xx_dma_reset(struct ag71xx *ag)
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{
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{
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int i;
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int i;
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@ -342,6 +331,25 @@ static void ag71xx_dma_reset(struct ag71xx *ag)
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ag71xx_dump_dma_regs(ag);
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ag71xx_dump_dma_regs(ag);
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}
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}
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#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
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MAC_CFG1_SRX | MAC_CFG1_STX)
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#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
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#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
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FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
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FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
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FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
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FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
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FIFO_CFG4_VT)
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#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
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FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
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FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
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FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
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FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
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FIFO_CFG5_17 | FIFO_CFG5_SF)
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static void ag71xx_hw_init(struct ag71xx *ag)
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static void ag71xx_hw_init(struct ag71xx *ag)
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{
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{
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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@ -355,8 +363,7 @@ static void ag71xx_hw_init(struct ag71xx *ag)
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mdelay(100);
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mdelay(100);
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/* setup MAC configuration registers */
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/* setup MAC configuration registers */
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
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pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
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ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
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ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
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MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
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MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
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@ -370,10 +377,8 @@ static void ag71xx_hw_init(struct ag71xx *ag)
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
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pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
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: AR71XX_FIFO_CFG5_INIT);
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ag71xx_dma_reset(ag);
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ag71xx_dma_reset(ag);
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}
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}
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