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[uboot-xburst] update u-boot to 2010.06

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fixed:
 when nand read. do ecc check not just bad block.
 try to fix mmc driver. will keeping work on that.

change:
 remove bootdelay when press [S] + power.
 create a xburst in mips/ folder.
 cleanup start.S cache.S cpu.c
 follow the new sturcture of u-boot.

Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
This commit is contained in:
Xiangfu Liu 2010-07-09 13:25:39 +08:00
parent 8839e9f75a
commit 3fd52fe91a
56 changed files with 1419 additions and 4141 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
package/uboot-xburst/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=u-boot PKG_NAME:=u-boot
PKG_VERSION:=2010.03 PKG_VERSION:=2010.06
PKG_RELEASE:=1 PKG_RELEASE:=1
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION) PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)

32
package/uboot-xburst/files/board/nanonote/Makefile → package/uboot-xburst/files/arch/mips/cpu/xburst/Makefile
View File

@ -1,6 +1,9 @@
# #
# (C) Copyright 2006 # (C) Copyright 2000-2006
# Ingenic Semiconductor, <jlwei@ingenic.cn> # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
# #
# This program is free software; you can redistribute it and/or # This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as # modify it under the terms of the GNU General Public License as
@ -20,21 +23,28 @@
include $(TOPDIR)/config.mk include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a LIB = $(obj)lib$(CPU).a
OBJS = $(BOARD).o START = start.o
SOBJS = COBJS = cpu.o interrupts.o jz4740.o jz_serial.o
$(LIB): .depend $(OBJS) $(SOBJS) COBJS += jz_mmc.o
$(AR) crv $@ $(OBJS) $(SOBJS) COBJS += nanonote_gpm940b0.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
######################################################################### #########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) # defines $(obj).depend target
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
include $(SRCTREE)/rules.mk include $(SRCTREE)/rules.mk
sinclude .depend sinclude $(obj).depend
######################################################################### #########################################################################

263
package/uboot-xburst/files/arch/mips/cpu/xburst/cache.S Normal file
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@ -0,0 +1,263 @@
/*
* Cache-handling routined for MIPS CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#ifndef CONFIG_JzRISC
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,9f ; \
move size,maxsize ; \
9:
#define _align(minaddr, maxaddr, linesize) \
.set noat ; \
subu AT,linesize,1 ; \
not AT ; \
and minaddr,AT ; \
addu maxaddr,-1 ; \
and maxaddr,AT ; \
.set at
/* general operations */
#define doop1(op1) \
cache op1,0(a0)
#define doop2(op1, op2) \
cache op1,0(a0) ; \
nop ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define doop1lw(op1) \
lw zero,0(a0)
#define doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
10: doop##tag##ops ; \
bne minaddr,maxaddr,10b ; \
add minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
_mincache(n, cacheSize); \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
/*
* mips_cache_reset - low level initialisation of the primary caches
*
* This routine initialises the primary caches to ensure that they
* have good parity. It must be called by the ROM before any cached locations
* are used to prevent the possibility of data with bad parity being written to
* memory.
* To initialise the instruction cache it is essential that a source of data
* with good parity is available. This routine
* will initialise an area of memory starting at location zero to be used as
* a source of parity.
*
* RETURNS: N/A
*/
.globl mips_cache_reset
.ent mips_cache_reset
mips_cache_reset:
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t4, CONFIG_SYS_CACHELINE_SIZE
move t5, t4
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
*/
li a0, KSEG1
addu a1, a0, v0
2: sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
sw zero, 16(a0)
sw zero, 20(a0)
sw zero, 24(a0)
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
/* Set invalid tag.
*/
mtc0 zero, CP0_TAGLO
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/* Assume bottom of RAM will generate good parity for the cache.
*/
li a0, K0BASE
move a2, t2 # icacheSize
move a3, t4 # icacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
/* To support Orion/R4600, we initialise the data cache in 3 passes.
*/
/* 1: initialise dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
/* 2: fill dcache.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,1lw,(dummy))
/* 3: clear dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
j ra
.end mips_cache_reset
/*
* dcache_status - get cache status
*
* RETURNS: 0 - cache disabled; 1 - cache enabled
*/
.globl dcache_status
.ent dcache_status
dcache_status:
mfc0 v0, CP0_CONFIG
andi v0, v0, 1
j ra
.end dcache_status
/*
* dcache_disable - disable cache
*
* RETURNS: N/A
*/
.globl dcache_disable
.ent dcache_disable
dcache_disable:
mfc0 t0, CP0_CONFIG
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
j ra
.end dcache_disable
/*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
* RETURNS: N/A
*/
#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
#else
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
li a1, K0BASE - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CONFIG_SYS_CACHELINE_SIZE
move a1, a2
icacheop(a0,a1,a2,a3,0x1d)
j ra
.end mips_cache_lock
#endif /* CONFIG_JzRISC */

27
package/uboot-xburst/files/nand_spl/board/nanonote/config.mk → package/uboot-xburst/files/arch/mips/cpu/xburst/config.mk
View File

@ -1,6 +1,6 @@
# #
# (C) Copyright 2006 # (C) Copyright 2003
# Stefan Roese, DENX Software Engineering, sr@denx.de. # Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
# #
# See file CREDITS for list of people who contributed to this # See file CREDITS for list of people who contributed to this
# project. # project.
@ -20,15 +20,16 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA # MA 02111-1307 USA
# #
# v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
# Ingenic JZ4740 Reference Platform MIPSFLAGS:=$(shell \
# if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc"; \
else \
echo "-march=4kc -mtune=4kc"; \
fi)
# ENDIANNESS = -EL
# TEXT_BASE for SPL:
# MIPSFLAGS += $(ENDIANNESS) -mabicalls -mips32 -O2
# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000,
# in the first 4kBytes of memory space in cache. So we set PLATFORM_CPPFLAGS += $(MIPSFLAGS)
# TEXT_BASE to starting address in internal cache here.
#
TEXT_BASE = 0x80000000

172
package/uboot-xburst/files/arch/mips/cpu/xburst/cpu.c Normal file
View File

@ -0,0 +1,172 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mipsregs.h>
#include <asm/cacheops.h>
#include <asm/reboot.h>
#include <asm/jz4740.h>
#if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL)
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
" .set noreorder \n" \
" .set mips3\n\t \n" \
" cache %0, %1 \n" \
" .set pop \n" \
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
void __attribute__((weak)) _machine_restart(void)
{
__wdt_select_extalclk();
__wdt_select_clk_div64();
__wdt_set_data(100);
__wdt_set_count(0);
__tcu_start_wdt_clock();
__wdt_start();
while(1);
#if defined(CONFIG_JzRISC)
void (*f)(void) = (void *) 0xbfc00000;
f();
#endif
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
_machine_restart();
fprintf(stderr, "*** reset failed ***\n");
return 0;
}
void flush_cache(ulong start_addr, ulong size)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Invalidate_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
write_c0_entrylo0(low0);
write_c0_pagemask(pagemask);
write_c0_entrylo1(low1);
write_c0_entryhi(hi);
write_c0_index(index);
tlb_write_indexed();
}
#endif /* !CONFIG_NAND_SPL !CONFIG_MSC_SPL */
void flush_icache_all(void)
{
u32 addr, t = 0;
asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile (
".set mips3\n\t"
" cache %0, 0(%1)\n\t"
".set mips2\n\t"
:
: "I" (Index_Store_Tag_I), "r"(addr));
}
/* invalicate btb */
asm volatile (
".set mips32\n\t"
"mfc0 %0, $16, 7\n\t"
"nop\n\t"
"ori %0,2\n\t"
"mtc0 %0, $16, 7\n\t"
".set mips2\n\t"
:
: "r" (t));
}
void flush_dcache_all(void)
{
u32 addr;
for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile (
".set mips3\n\t"
" cache %0, 0(%1)\n\t"
".set mips2\n\t"
:
: "I" (Index_Writeback_Inv_D), "r"(addr));
}
asm volatile ("sync");
}
void flush_cache_all(void)
{
flush_dcache_all();
flush_icache_all();
}

31
package/uboot-xburst/files/board/n516/flash.c → package/uboot-xburst/files/arch/mips/cpu/xburst/interrupts.c
View File

@ -1,6 +1,9 @@
/* /*
* (C) Copyright 2006 * (C) Copyright 2003
* Ingenic Semiconductor, <jlwei@ingenic.cn> * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
@ -20,31 +23,11 @@
#include <common.h> #include <common.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ void enable_interrupts(void)
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{ {
return (0);
} }
int flash_erase (flash_info_t * info, int s_first, int s_last) int disable_interrupts(void)
{ {
printf ("flash_erase not implemented\n");
return 0; return 0;
} }
void flash_print_info (flash_info_t * info)
{
printf ("flash_print_info not implemented\n");
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
printf ("write_buff not implemented\n");
return (-1);
}

0
package/uboot-xburst/files/cpu/mips/jz4740.c → package/uboot-xburst/files/arch/mips/cpu/xburst/jz4740.c
View File

81
package/uboot-xburst/files/cpu/mips/jz_mmc.c → package/uboot-xburst/files/arch/mips/cpu/xburst/jz_mmc.c
View File

@ -26,7 +26,7 @@
#include <part.h> #include <part.h>
#include <mmc.h> #include <mmc.h>
#include <asm-mips/jz4740.h> #include <asm/jz4740.h>
#include "jz_mmc.h" #include "jz_mmc.h"
#define CFG_MMC_BASE 0x80600000 #define CFG_MMC_BASE 0x80600000
@ -88,7 +88,7 @@ block_dev_desc_t * mmc_get_dev(int dev)
/* /*
* FIXME needs to read cid and csd info to determine block size * FIXME needs to read cid and csd info to determine block size
* and other parameters v * and other parameters
*/ */
static uchar mmc_buf[MMC_BLOCK_SIZE]; static uchar mmc_buf[MMC_BLOCK_SIZE];
static int mmc_ready = 0; static int mmc_ready = 0;
@ -602,7 +602,7 @@ int xburst_mmc_read(u64 src, uchar *dst, int size)
mmc_block_size = MMC_BLOCK_SIZE; mmc_block_size = MMC_BLOCK_SIZE;
mmc_block_address = ~(mmc_block_size - 1); mmc_block_address = ~(mmc_block_size - 1);
src -= CFG_MMC_BASE; //src -= CFG_MMC_BASE;
end = src + size; end = src + size;
part_start = ~mmc_block_address & src; part_start = ~mmc_block_address & src;
part_end = ~mmc_block_address & end; part_end = ~mmc_block_address & end;
@ -716,7 +716,7 @@ ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
ulong src; ulong src;
int mmc_block_size = MMC_BLOCK_SIZE; int mmc_block_size = MMC_BLOCK_SIZE;
src = blknr * mmc_block_size + CFG_MMC_BASE; src = blknr * mmc_block_size ;//+ CFG_MMC_BASE;
xburst_mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size); xburst_mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size);
return blkcnt; return blkcnt;
} }
@ -885,16 +885,6 @@ static int mmc_init_card_state(struct mmc_request *request)
case MMC_CMD_ALL_SEND_CID: case MMC_CMD_ALL_SEND_CID:
retval = mmc_unpack_cid( request, &mmcinfo.cid ); retval = mmc_unpack_cid( request, &mmcinfo.cid );
mmc_dev.if_type = IF_TYPE_MMC;
mmc_dev.part_type = PART_TYPE_DOS;
mmc_dev.dev = 0;
mmc_dev.lun = 0;
mmc_dev.type = 0;
/* FIXME fill in the correct size (is set to 32MByte) */
mmc_dev.blksz = 512;
mmc_dev.lba = 0x10000;
mmc_dev.removable = 0;
/*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */ /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
if ( retval && (retval != MMC_ERROR_CRC)) { if ( retval && (retval != MMC_ERROR_CRC)) {
debug("mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n", debug("mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n",
@ -1144,30 +1134,7 @@ int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0; csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0;
csd->file_format = (buf[15] & 0x0c) >> 2; csd->file_format = (buf[15] & 0x0c) >> 2;
csd->ecc = buf[15] & 0x03; csd->ecc = buf[15] & 0x03;
debug(" csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n"
" ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n"
" read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n"
" vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n"
" wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n"
" write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n"
" perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n",
csd->csd_structure, csd->spec_vers,
csd->taac, csd->nsac, csd->tran_speed,
csd->ccc, csd->read_bl_len,
csd->read_bl_partial, csd->write_blk_misalign,
csd->read_blk_misalign, csd->dsr_imp,
csd->c_size, csd->vdd_r_curr_min,
csd->vdd_r_curr_max, csd->vdd_w_curr_min,
csd->vdd_w_curr_max, csd->c_size_mult,
csd->wp_grp_size, csd->wp_grp_enable,
csd->default_ecc, csd->r2w_factor,
csd->write_bl_len, csd->write_bl_partial,
csd->file_format_grp, csd->copy,
csd->perm_write_protect, csd->tmp_write_protect,
csd->file_format, csd->ecc);
break; break;
case 1 : case 1 :
csd->taac = 0; csd->taac = 0;
csd->nsac = 0; csd->nsac = 0;
@ -1195,33 +1162,23 @@ int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0; csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0;
csd->file_format = 0; csd->file_format = 0;
csd->ecc = buf[15] & 0x03; csd->ecc = buf[15] & 0x03;
debug(" csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n"
" ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n"
" read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n"
" vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n"
" wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n"
" write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n"
" perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n",
csd->csd_structure, csd->spec_vers,
csd->taac, csd->nsac, csd->tran_speed,
csd->ccc, csd->read_bl_len,
csd->read_bl_partial, csd->write_blk_misalign,
csd->read_blk_misalign, csd->dsr_imp,
csd->c_size, csd->vdd_r_curr_min,
csd->vdd_r_curr_max, csd->vdd_w_curr_min,
csd->vdd_w_curr_max, csd->c_size_mult,
csd->wp_grp_size, csd->wp_grp_enable,
csd->default_ecc, csd->r2w_factor,
csd->write_bl_len, csd->write_bl_partial,
csd->file_format_grp, csd->copy,
csd->perm_write_protect, csd->tmp_write_protect,
csd->file_format, csd->ecc);
debug(" V22 sector_size=%d erase_grp_size=%d\n",
csd->sector_size,
csd->erase_grp_size);
} }
mmc_dev.if_type = IF_TYPE_SD;
mmc_dev.part_type = PART_TYPE_DOS;
mmc_dev.dev = 0;
mmc_dev.lun = 0;
mmc_dev.type = 0;
mmc_dev.blksz = 512;
mmc_dev.lba = (1 + csd->c_size) << 10;
mmc_dev.removable = 0;
printf("SD%s Detected: %lu blocks of %lu bytes (%luMB)\n",
sd2_0 == 1 ? "HC" : " ",
mmc_dev.lba,
mmc_dev.blksz,
mmc_dev.lba * mmc_dev.blksz / (1024 * 1024));
if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH; if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
return 0; return 0;

0
package/uboot-xburst/files/cpu/mips/jz_mmc.h → package/uboot-xburst/files/arch/mips/cpu/xburst/jz_mmc.h
View File

2
package/uboot-xburst/files/cpu/mips/jz_serial.c → package/uboot-xburst/files/arch/mips/cpu/xburst/jz_serial.c
View File

@ -30,7 +30,7 @@
#include <common.h> #include <common.h>
#include <asm/jz4740.h> #include <asm/jz4740.h>
#undef UART_BASE #undef UART_BASE
#ifndef CONFIG_SYS_UART_BASE #ifndef CONFIG_SYS_UART_BASE
#define UART_BASE UART0_BASE #define UART_BASE UART0_BASE

0
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c → package/uboot-xburst/files/arch/mips/cpu/xburst/nanonote_gpm940b0.c
View File

0
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h → package/uboot-xburst/files/arch/mips/cpu/xburst/nanonote_gpm940b0.h
View File

169
package/uboot-xburst/files/arch/mips/cpu/xburst/start.S Normal file
View File

@ -0,0 +1,169 @@
/*
* Startup Code for MIPS32 XBURST CPU-core
*
* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/jz4740.h>
.set noreorder
.globl _start
.text
_start:
/* Initialize GOT pointer.
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
move gp, ra
lw t1, 0(ra)
move gp, t1
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
la t9, board_init_f
j t9
nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, TEXT_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - TEXT_BASE) + Destination Address
*/
move t6, gp
sub gp, TEXT_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset*/
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
/* If caches were enabled, we would have to flush them here.
* flush d-cache */
.set mips32
li t0, KSEG0
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
2:
cache Index_Writeback_Inv_D, 0(t0)
bne t0, t1, 2b
addi t0, CONFIG_SYS_CACHELINE_SIZE
sync
/* flush i-cache */
li t0, KSEG0
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
3:
cache Index_Invalidate_I, 0(t0)
bne t0, t1, 3b
addi t0, CONFIG_SYS_CACHELINE_SIZE
/* Invalidate BTB */
mfc0 t0, CP0_CONFIG, 7
nop
ori t0, 2
mtc0 t0, CP0_CONFIG, 7
nop
.set mips0
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT */
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS */
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code

63
package/uboot-xburst/files/arch/mips/cpu/xburst/start_spl.S Normal file
View File

@ -0,0 +1,63 @@
/*
* Startup Code for MIPS32 XBURST CPU-core
*
* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/jz4740.h>
.set noreorder
.globl _start
.text
_start:
.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
reset:
/*
* STATUS register
* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
*/
li t0, 0x0040FC04
mtc0 t0, CP0_STATUS
/* CAUSE register
* IV=1, use the specical interrupt vector (0x200) */
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
move gp, ra
lw t1, 0(ra)
move gp, t1
la sp, 0x80004000
la t9, nand_boot
j t9
nop

2
package/uboot-xburst/files/cpu/mips/usb_boot.S → package/uboot-xburst/files/arch/mips/cpu/xburst/usbboot.S
View File

@ -1,7 +1,7 @@
/* /*
* for jz4740 usb boot * for jz4740 usb boot
* *
* Copyright (c) 2009 Xiangfu Liu <xiangfu.z@gmail.com> * Copyright (c) 2009 Author: <jlwei@ingenic.cn>
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.

109
package/uboot-xburst/files/include/asm-mips/jz4740.h → package/uboot-xburst/files/arch/mips/include/asm/jz4740.h
View File

@ -4,22 +4,10 @@
#ifndef __JZ4740_H__ #ifndef __JZ4740_H__
#define __JZ4740_H__ #define __JZ4740_H__
#ifndef __ASSEMBLY__
#define UCOS_CSP 0
#if UCOS_CSP
#define __KERNEL__
#include <bsp.h>
#include <types.h>
#include <sysdefs.h>
#include <cacheops.h>
#define KSEG0 KSEG0BASE
#else
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/cacheops.h> #include <asm/cacheops.h>
#endif
#ifndef __ASSEMBLY__
#define cache_unroll(base,op) \ #define cache_unroll(base,op) \
__asm__ __volatile__(" \ __asm__ __volatile__(" \
.set noreorder; \ .set noreorder; \
@ -57,52 +45,10 @@ static inline void jz_flush_icache(void)
} }
} }
/* cpu pipeline flush */
static inline void jz_sync(void)
{
__asm__ volatile ("sync");
}
static inline void jz_writeb(u32 address, u8 value)
{
*((volatile u8 *)address) = value;
}
static inline void jz_writew(u32 address, u16 value)
{
*((volatile u16 *)address) = value;
}
static inline void jz_writel(u32 address, u32 value)
{
*((volatile u32 *)address) = value;
}
static inline u8 jz_readb(u32 address)
{
return *((volatile u8 *)address);
}
static inline u16 jz_readw(u32 address)
{
return *((volatile u16 *)address);
}
static inline u32 jz_readl(u32 address)
{
return *((volatile u32 *)address);
}
#define REG8(addr) *((volatile u8 *)(addr)) #define REG8(addr) *((volatile u8 *)(addr))
#define REG16(addr) *((volatile u16 *)(addr)) #define REG16(addr) *((volatile u16 *)(addr))
#define REG32(addr) *((volatile u32 *)(addr)) #define REG32(addr) *((volatile u32 *)(addr))
#else
#define REG8(addr) (addr)
#define REG16(addr) (addr)
#define REG32(addr) (addr)
#endif /* !ASSEMBLY */ #endif /* !ASSEMBLY */
/* Boot ROM Specification */ /* Boot ROM Specification */
@ -1618,39 +1564,29 @@ static inline u32 jz_readl(u32 address)
/* MSC Command Sequence Control Register (MSC_CMDAT) */ /* MSC Command Sequence Control Register (MSC_CMDAT) */
#define MSC_CMDAT_IO_ABORT (1 << 11) #define MSC_CMDAT_IO_ABORT (1 << 11)
#define MSC_CMDAT_BUS_WIDTH_BIT 9 #define MSC_CMDAT_BUS_WIDTH_BIT 9
#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
#define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) #define MSC_CMDAT_DMA_EN (1 << 8)
#define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) #define MSC_CMDAT_INIT (1 << 7)
#define MSC_CMDAT_DMA_EN (1 << 8) #define MSC_CMDAT_BUSY (1 << 6)
#define MSC_CMDAT_INIT (1 << 7) #define MSC_CMDAT_STREAM_BLOCK (1 << 5)
#define MSC_CMDAT_BUSY (1 << 6) #define MSC_CMDAT_WRITE (1 << 4)
#define MSC_CMDAT_STREAM_BLOCK (1 << 5) #define MSC_CMDAT_READ (0 << 4)
#define MSC_CMDAT_WRITE (1 << 4) #define MSC_CMDAT_DATA_EN (1 << 3)
#define MSC_CMDAT_READ (0 << 4)
#define MSC_CMDAT_DATA_EN (1 << 3)
#define MSC_CMDAT_RESPONSE_BIT 0 #define MSC_CMDAT_RESPONSE_BIT 0
#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT)
#define CMDAT_DMA_EN (1 << 8)
#define CMDAT_INIT (1 << 7)
#define CMDAT_BUSY (1 << 6)
#define CMDAT_STREAM (1 << 5)
#define CMDAT_WRITE (1 << 4)
#define CMDAT_DATA_EN (1 << 3)
/* MSC Interrupts Mask Register (MSC_IMASK) */ /* MSC Interrupts Mask Register (MSC_IMASK) */
#define MSC_IMASK_SDIO (1 << 7) #define MSC_IMASK_SDIO (1 << 7)
#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
@ -1660,7 +1596,6 @@ static inline u32 jz_readl(u32 address)
/* MSC Interrupts Status Register (MSC_IREG) */ /* MSC Interrupts Status Register (MSC_IREG) */
#define MSC_IREG_SDIO (1 << 7) #define MSC_IREG_SDIO (1 << 7)
#define MSC_IREG_TXFIFO_WR_REQ (1 << 6) #define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
#define MSC_IREG_RXFIFO_RD_REQ (1 << 5) #define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
@ -1669,9 +1604,9 @@ static inline u32 jz_readl(u32 address)
#define MSC_IREG_DATA_TRAN_DONE (1 << 0) #define MSC_IREG_DATA_TRAN_DONE (1 << 0)
/************************************************************************* /*
* EMC (External Memory Controller) * EMC (External Memory Controller)
*************************************************************************/ */
#define EMC_BCR (EMC_BASE + 0x0) /* BCR */ #define EMC_BCR (EMC_BASE + 0x0) /* BCR */
#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */

33
package/uboot-xburst/files/board/n516/config.mk
View File

@ -1,33 +0,0 @@
#
# (C) Copyright 2006
# Ingenic Semiconductor, <jlwei@ingenic.cn>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Hanvon n516 e-book, MIPS32 core
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
# ROM version
TEXT_BASE = 0x88000000
# RAM version
#TEXT_BASE = 0x80100000
endif

126
package/uboot-xburst/files/board/n516/n516.c
View File

@ -1,126 +0,0 @@
/*
* (C) Copyright 2006
* Ingenic Semiconductor, <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
#include <asm/jz4740.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
void _machine_restart(void)
{
__wdt_select_extalclk();
__wdt_select_clk_div64();
__wdt_set_data(100);
__wdt_set_count(0);
__tcu_start_wdt_clock();
__wdt_start();
while(1);
}
static void gpio_init(void)
{
REG_GPIO_PXPES(0) = 0xffffffff;
REG_GPIO_PXPES(1) = 0xffffffff;
REG_GPIO_PXPES(2) = 0xffffffff;
REG_GPIO_PXPES(3) = 0xffffffff;
/*
* Initialize NAND Flash Pins
*/
__gpio_as_nand();
/*
* Initialize SDRAM pins
*/
__gpio_as_sdram_32bit();
/*
* Initialize UART0 pins
*/
__gpio_as_uart0();
/*
* Initialize MSC pins
*/
__gpio_as_msc();
/*
* Initialize LCD pins
*/
__gpio_as_lcd_16bit();
/*
* Initialize Other pins
*/
__gpio_as_output(GPIO_SD_VCC_EN_N);
__gpio_clear_pin(GPIO_SD_VCC_EN_N);
__gpio_as_input(GPIO_SD_CD_N);
__gpio_disable_pull(GPIO_SD_CD_N);
__gpio_as_output(GPIO_DISP_OFF_N);
__gpio_as_output(GPIO_LED_EN);
__gpio_set_pin(GPIO_LED_EN);
__gpio_as_input(127);
}
static void cpm_init(void)
{
__cpm_stop_ipu();
__cpm_stop_cim();
__cpm_stop_i2c();
__cpm_stop_ssi();
__cpm_stop_uart1();
__cpm_stop_sadc();
__cpm_stop_uhc();
__cpm_stop_udc();
__cpm_stop_aic1();
__cpm_stop_aic2();
__cpm_suspend_udcphy();
__cpm_suspend_usbphy();
}
//----------------------------------------------------------------------
// board early init routine
void board_early_init(void)
{
gpio_init();
cpm_init();
}
//----------------------------------------------------------------------
// U-Boot common routines
int checkboard (void)
{
DECLARE_GLOBAL_DATA_PTR;
printf("Board: Hanvon n516 e-book (CPU Speed %d MHz)\n",
gd->cpu_clk/1000000);
return 0; /* success */
}

63
package/uboot-xburst/files/board/nanonote/u-boot-nand.lds
View File

@ -1,63 +0,0 @@
/*
* (C) Copyright 2006
* Ingenic Semiconductor, <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

63
package/uboot-xburst/files/board/nanonote/u-boot.lds
View File

@ -1,63 +0,0 @@
/*
* (C) Copyright 2006
* Ingenic Semiconductor, <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

38
package/uboot-xburst/files/board/sakc/Makefile
View File

@ -1,38 +0,0 @@
#
# (C) Copyright 2006
# Ingenic Semiconductor, <jlwei@ingenic.cn>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
SOBJS =
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

31
package/uboot-xburst/files/board/sakc/config.mk
View File

@ -1,31 +0,0 @@
#
# (C) Copyright 2006 Qi Hardware, Inc.
# Author: Xiangfu Liu <xiangfu.z@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# SAKC Board
#
ifndef TEXT_BASE
# ROM version
# TEXT_BASE = 0x88000000
# RAM version
TEXT_BASE = 0x80100000
endif

94
package/uboot-xburst/files/board/sakc/sakc.c
View File

@ -1,94 +0,0 @@
/*
* Authors: Xiangfu Liu <xiangfu.z@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 3 of the License, or (at your option) any later version.
*/
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
#include <asm/jz4740.h>
DECLARE_GLOBAL_DATA_PTR;
static void gpio_init(void)
{
/*
* Initialize NAND Flash Pins
*/
__gpio_as_nand();
/*
* Initialize SDRAM pins
*/
__gpio_as_sdram_16bit_4725();
/*
* Initialize UART0 pins
*/
__gpio_as_uart0();
/*
* Initialize LCD pins
*/
__gpio_as_lcd_18bit();
/*
* Initialize MSC pins
*/
__gpio_as_msc();
/*
* Initialize SSI pins
*/
__gpio_as_ssi();
/*
* Initialize I2C pins
*/
__gpio_as_i2c();
/*
* Initialize MSC pins
*/
__gpio_as_msc();
/*
* Initialize Other pins
*/
__gpio_as_input(GPIO_SD_DETECT);
__gpio_disable_pull(GPIO_SD_DETECT);
}
/* TODO SAKC
static void cpm_init(void)
{
__cpm_stop_ipu();
__cpm_stop_cim();
__cpm_stop_i2c();
__cpm_stop_ssi();
__cpm_stop_uart1();
__cpm_stop_sadc();
__cpm_stop_uhc();
__cpm_stop_aic1();
__cpm_stop_aic2();
}*/
void board_early_init(void)
{
gpio_init();
//cpm_init(); //TODO SAKC
}
/* U-Boot common routines */
int checkboard (void)
{
printf("Board: SAKC (Ingenic XBurst Jz4725 SoC, Speed %d MHz)\n",
gd->cpu_clk/1000000);
return 0; /* success */
}

63
package/uboot-xburst/files/board/sakc/u-boot-nand.lds
View File

@ -1,63 +0,0 @@
/*
* (C) Copyright 2006
* Ingenic Semiconductor, <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

63
package/uboot-xburst/files/board/sakc/u-boot.lds
View File

@ -1,63 +0,0 @@
/*
* (C) Copyright 2006
* Ingenic Semiconductor, <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

43
package/uboot-xburst/files/board/xburst/nanonote/.depend Normal file
View File

@ -0,0 +1,43 @@
nanonote.o: nanonote.c \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/common.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config_defaults.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/qi_lb60.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/nanonote.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/byteorder.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/little_endian.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/swab.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/generic.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/sgidefs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/system.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/ptrace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/isadep.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/string.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/string.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stdarg.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/part.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/ide.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/flash.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/image.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/compiler.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/lmb.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/u-boot.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/command.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/global_data.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/regdef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/net.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/u-boot/crc.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/mipsregs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/jz4740.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/addrspace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/cacheops.h

17
package/uboot-xburst/files/board/n516/Makefile → package/uboot-xburst/files/board/xburst/nanonote/Makefile
View File

@ -22,18 +22,23 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o COBJS := $(BOARD).o
OBJS = $(addprefix $(obj),$(COBJS)) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SOBJS = OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
######################################################################### #########################################################################
$(obj).depend: Makefile $(SOBJS:.o=.S) $(COBJS:.o=.c) # defines $(obj).depend target
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(COBJS:.o=.c) > $@ include $(SRCTREE)/rules.mk
sinclude $(obj).depend sinclude $(obj).depend

0
package/uboot-xburst/files/board/nanonote/config.mk → package/uboot-xburst/files/board/xburst/nanonote/config.mk
View File

1
package/uboot-xburst/files/board/xburst/nanonote/config.tmp Normal file
View File

@ -0,0 +1 @@
TEXT_BASE = 0x80100000

0
package/uboot-xburst/files/board/nanonote/nanonote.c → package/uboot-xburst/files/board/xburst/nanonote/nanonote.c
View File

0
package/uboot-xburst/files/board/n516/u-boot-nand.lds → package/uboot-xburst/files/board/xburst/nanonote/u-boot-nand.lds
View File

0
package/uboot-xburst/files/board/n516/u-boot.lds → package/uboot-xburst/files/board/xburst/nanonote/u-boot.lds
View File

199
package/uboot-xburst/files/cpu/mips/jz4740_nand.c
View File

@ -1,199 +0,0 @@
/*
* Platform independend driver for JZ4740.
*
* Copyright (c) 2007 Ingenic Semiconductor Inc.
* Author: <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_JZ4740)
#include <nand.h>
#include <asm/jz4740.h>
#include <asm/io.h>
#define PAR_SIZE 9
#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS)
#define __nand_rs_ecc_encoding() (REG_EMC_NFECR |= EMC_NFECR_RS_ENCODING)
#define __nand_rs_ecc_decoding() (REG_EMC_NFECR |= EMC_NFECR_RS_DECODING)
#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
/* Change this to use I/O accessors. */
if (ctrl & NAND_NCE)
REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
else
REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
}
if (cmd == NAND_CMD_NONE)
return;
if (ctrl & NAND_CLE)
nandaddr |= 0x00008000;
else /* must be ALE */
nandaddr |= 0x00010000;
writeb(cmd, (uint8_t *)nandaddr);
}
static int jz_device_ready(struct mtd_info *mtd)
{
int ready;
udelay(20); /* FIXME: add 20us delay */
ready = (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
return ready;
}
/*
* EMC setup
*/
static void jz_device_setup(void)
{
/* Set NFE bit */
REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
REG_EMC_SMCR1 = 0x094c4400;
/* REG_EMC_SMCR3 = 0x04444400; */
}
void board_nand_select_device(struct nand_chip *nand, int chip)
{
/*
* Don't use "chip" to address the NAND device,
* generate the cs from the address where it is encoded.
*/
}
static int jzsoc_nand_calculate_rs_ecc(struct mtd_info* mtd, const u_char* dat,
u_char* ecc_code)
{
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
short i;
__nand_ecc_encode_sync()
__nand_ecc_disable();
for(i = 0; i < PAR_SIZE; i++)
ecc_code[i] = *paraddr++;
return 0;
}
static void jzsoc_nand_enable_rs_hwecc(struct mtd_info* mtd, int mode)
{
__nand_ecc_enable();
__nand_select_rs_ecc();
REG_EMC_NFINTS = 0x0;
if (NAND_ECC_READ == mode){
__nand_rs_ecc_decoding();
}
if (NAND_ECC_WRITE == mode){
__nand_rs_ecc_encoding();
}
}
/* Correct 1~9-bit errors in 512-bytes data */
static void jzsoc_rs_correct(unsigned char *dat, int idx, int mask)
{
int i;
idx--;
i = idx + (idx >> 3);
if (i >= 512)
return;
mask <<= (idx & 0x7);
dat[i] ^= mask & 0xff;
if (i < 511)
dat[i+1] ^= (mask >> 8) & 0xff;
}
static int jzsoc_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
short k;
u32 stat;
/* Set PAR values */
for (k = 0; k < PAR_SIZE; k++) {
*paraddr++ = read_ecc[k];
}
/* Set PRDY */
REG_EMC_NFECR |= EMC_NFECR_PRDY;
/* Wait for completion */
__nand_ecc_decode_sync();
__nand_ecc_disable();
/* Check decoding */
stat = REG_EMC_NFINTS;
if (stat & EMC_NFINTS_ERR) {
if (stat & EMC_NFINTS_UNCOR) {
printk("Uncorrectable error occurred\n");
return -1;
}
else {
u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
switch (errcnt) {
case 4:
jzsoc_rs_correct(dat, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 3:
jzsoc_rs_correct(dat, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 2:
jzsoc_rs_correct(dat, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 1:
jzsoc_rs_correct(dat, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
return 0;
default:
break;
}
}
}
/* no error need to be correct */
return 0;
}
/*
* Main initialization routine
*/
int board_nand_init(struct nand_chip *nand)
{
jz_device_setup();
nand->cmd_ctrl = jz_hwcontrol;
nand->dev_ready = jz_device_ready;
/* FIXME: should use NAND_ECC_SOFT */
nand->ecc.hwctl = jzsoc_nand_enable_rs_hwecc;
nand->ecc.correct = jzsoc_nand_rs_correct_data;
nand->ecc.calculate = jzsoc_nand_calculate_rs_ecc;
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = 512;
nand->ecc.bytes = 9;
/* 20 us command delay time */
nand->chip_delay = 20;
return 0;
}
#endif /* (CONFIG_SYS_CMD_NAND) */

484
package/uboot-xburst/files/cpu/mips/jz_lcd.c
View File

@ -1,484 +0,0 @@
/*
* JzRISC lcd controller
*
* xiangfu liu <xiangfu.z@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Fallowing macro may be used:
* CONFIG_LCD : LCD support
* LCD_BPP : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8
* CONFIG_LCD_LOGO : show logo
*/
#include <config.h>
#include <common.h>
#include <lcd.h>
#include <asm/io.h> /* virt_to_phys() */
#if defined(CONFIG_LCD) && !defined(CONFIG_SLCD)
#if defined(CONFIG_JZ4740)
#include <asm/jz4740.h>
#endif
#include "jz_lcd.h"
struct jzfb_info {
unsigned int cfg; /* panel mode and pin usage etc. */
unsigned int w;
unsigned int h;
unsigned int bpp; /* bit per pixel */
unsigned int fclk; /* frame clk */
unsigned int hsw; /* hsync width, in pclk */
unsigned int vsw; /* vsync width, in line count */
unsigned int elw; /* end of line, in pclk */
unsigned int blw; /* begin of line, in pclk */
unsigned int efw; /* end of frame, in line count */
unsigned int bfw; /* begin of frame, in line count */
};
static struct jzfb_info jzfb = {
#if defined(CONFIG_NANONOTE)
MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
320, 240, 32, 70, 1, 1, 273, 140, 1, 20
#endif
};
/************************************************************************/
vidinfo_t panel_info = {
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
320, 240, LCD_BPP,
#endif
};
/*----------------------------------------------------------------------*/
int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;
/*
* Frame buffer memory information
*/
void *lcd_base; /* Start of framebuffer memory */
void *lcd_console_address; /* Start of console buffer */
short console_col;
short console_row;
/*----------------------------------------------------------------------*/
void lcd_ctrl_init (void *lcdbase);
void lcd_enable (void);
void lcd_disable (void);
/*----------------------------------------------------------------------*/
static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
static void jz_lcd_desc_init(vidinfo_t *vid);
static int jz_lcd_hw_init( vidinfo_t *vid );
extern int flush_cache_all(void);
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
#endif
#if LCD_BPP == LCD_MONOCHROME
void lcd_initcolregs (void);
#endif
/*-----------------------------------------------------------------------*/
void lcd_ctrl_init (void *lcdbase)
{
__lcd_display_pin_init();
jz_lcd_init_mem(lcdbase, &panel_info);
jz_lcd_desc_init(&panel_info);
jz_lcd_hw_init(&panel_info);
__lcd_display_on() ;
}
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
}
#endif
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_MONOCHROME
static
void lcd_initcolregs (void)
{
}
#endif
/*
* Before enabled lcd controller, lcd registers should be configured correctly.
*/
void lcd_enable (void)
{
REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
}
void lcd_disable (void)
{
REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
/* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
}
static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
{
u_long palette_mem_size;
struct jz_fb_info *fbi = &vid->jz_fb;
int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
fbi->screen = (u_long)lcdbase;
fbi->palette_size = 256;
palette_mem_size = fbi->palette_size * sizeof(u16);
debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
/* locate palette and descs at end of page following fb */
fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
return 0;
}
static void jz_lcd_desc_init(vidinfo_t *vid)
{
struct jz_fb_info * fbi;
fbi = &vid->jz_fb;
fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
#define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
/* populate descriptors */
fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
fbi->dmadesc_fblow->fidr = 0;
fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
fbi->dmadesc_fbhigh->fidr = 0;
fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
fbi->dmadesc_palette->fidr = 0;
fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
if( NBITS(vid->vl_bpix) < 12)
{
/* assume any mode with <12 bpp is palette driven */
fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
/* flips back and forth between pal and fbhigh */
fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
} else {
/* palette shouldn't be loaded in true-color mode */
fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
}
flush_cache_all();
}
static int jz_lcd_hw_init(vidinfo_t *vid)
{
struct jz_fb_info *fbi = &vid->jz_fb;
unsigned int val = 0;
unsigned int pclk;
unsigned int stnH;
#if defined(CONFIG_MIPS_JZ4740)
int pll_div;
#endif
/* Setting Control register */
switch (jzfb.bpp) {
case 1:
val |= LCD_CTRL_BPP_1;
break;
case 2:
val |= LCD_CTRL_BPP_2;
break;
case 4:
val |= LCD_CTRL_BPP_4;
break;
case 8:
val |= LCD_CTRL_BPP_8;
break;
case 15:
val |= LCD_CTRL_RGB555;
case 16:
val |= LCD_CTRL_BPP_16;
break;
#if defined(CONFIG_MIPS_JZ4740)
case 17 ... 32:
val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
break;
#endif
default:
printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
val |= LCD_CTRL_BPP_16;
break;
}
switch (jzfb.cfg & MODE_MASK) {
case MODE_STN_MONO_DUAL:
case MODE_STN_COLOR_DUAL:
case MODE_STN_MONO_SINGLE:
case MODE_STN_COLOR_SINGLE:
switch (jzfb.bpp) {
case 1:
/* val |= LCD_CTRL_PEDN; */
case 2:
val |= LCD_CTRL_FRC_2;
break;
case 4:
val |= LCD_CTRL_FRC_4;
break;
case 8:
default:
val |= LCD_CTRL_FRC_16;
break;
}
break;
}
val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
switch (jzfb.cfg & MODE_MASK) {
case MODE_STN_MONO_DUAL:
case MODE_STN_COLOR_DUAL:
case MODE_STN_MONO_SINGLE:
case MODE_STN_COLOR_SINGLE:
switch (jzfb.cfg & STN_DAT_PINMASK) {
#define align2(n) (n)=((((n)+1)>>1)<<1)
#define align4(n) (n)=((((n)+3)>>2)<<2)
#define align8(n) (n)=((((n)+7)>>3)<<3)
case STN_DAT_PIN1:
/* Do not adjust the hori-param value. */
break;
case STN_DAT_PIN2:
align2(jzfb.hsw);
align2(jzfb.elw);
align2(jzfb.blw);
break;
case STN_DAT_PIN4:
align4(jzfb.hsw);
align4(jzfb.elw);
align4(jzfb.blw);
break;
case STN_DAT_PIN8:
align8(jzfb.hsw);
align8(jzfb.elw);
align8(jzfb.blw);
break;
}
break;
}
REG_LCD_CTRL = val;
switch (jzfb.cfg & MODE_MASK) {
case MODE_STN_MONO_DUAL:
case MODE_STN_COLOR_DUAL:
case MODE_STN_MONO_SINGLE:
case MODE_STN_COLOR_SINGLE:
if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
stnH = jzfb.h >> 1;
else
stnH = jzfb.h;
REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
/* Screen setting */
REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
REG_LCD_DAV = (0 << 16) | (stnH);
/* AC BIAs signal */
REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
break;
case MODE_TFT_GEN:
case MODE_TFT_SHARP:
case MODE_TFT_CASIO:
case MODE_TFT_SAMSUNG:
case MODE_8BIT_SERIAL_TFT:
case MODE_TFT_18BIT:
REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
REG_LCD_DAV = (0 << 16) | ( jzfb.h );
#else
REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
| (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
break;
}
switch (jzfb.cfg & MODE_MASK) {
case MODE_TFT_SAMSUNG:
{
unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
unsigned int rev_s, rev_e, inv_s, inv_e;
pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
tp_s = jzfb.blw + jzfb.w + 1;
tp_e = tp_s + 1;
/* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
ckv_s = tp_s - pclk/(1000000000/4100);
ckv_e = tp_s + total;
rev_s = tp_s - 11; /* -11.5 clk */
rev_e = rev_s + total;
inv_s = tp_s;
inv_e = inv_s + total;
REG_LCD_CLS = (tp_s << 16) | tp_e;
REG_LCD_PS = (ckv_s << 16) | ckv_e;
REG_LCD_SPL = (rev_s << 16) | rev_e;
REG_LCD_REV = (inv_s << 16) | inv_e;
jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
break;
}
case MODE_TFT_SHARP:
{
unsigned int total, cls_s, cls_e, ps_s, ps_e;
unsigned int spl_s, spl_e, rev_s, rev_e;
total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
#if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
spl_s = 1;
spl_e = spl_s + 1;
cls_s = 0;
cls_e = total - 60; /* > 4us (pclk = 80ns) */
ps_s = cls_s;
ps_e = cls_e;
rev_s = total - 40; /* > 3us (pclk = 80ns) */
rev_e = rev_s + total;
jzfb.cfg |= STFT_PSHI;
#else /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
spl_s = total - 5; /* LD */
spl_e = total -3;
cls_s = 32; /* CKV */
cls_e = 145;
ps_s = 0; /* OEV */
ps_e = 45;
rev_s = 0; /* POL */
rev_e = 0;
#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
REG_LCD_SPL = (spl_s << 16) | spl_e;
REG_LCD_CLS = (cls_s << 16) | cls_e;
REG_LCD_PS = (ps_s << 16) | ps_e;
REG_LCD_REV = (rev_s << 16) | rev_e;
break;
}
case MODE_TFT_CASIO:
break;
}
/* Configure the LCD panel */
REG_LCD_CFG = jzfb.cfg;
/* Timing setting */
__cpm_stop_lcd();
val = jzfb.fclk; /* frame clk */
if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
}
else {
/* serial mode: Hsync period = 3*Width_Pixel */
pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
}
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
pclk = (pclk * 3);
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
pclk >>= 1;
pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
pll_div = pll_div ? 1 : 2 ;
val = ( __cpm_get_pllout()/pll_div ) / pclk;
val--;
if ( val > 0x1ff ) {
printf("CPM_LPCDR too large, set it to 0x1ff\n");
val = 0x1ff;
}
__cpm_set_pixdiv(val);
val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
if ( val > 150000000 ) {
printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
printf("Change LCDClock to 150MHz\n");
val = 150000000;
}
val = ( __cpm_get_pllout()/pll_div ) / val;
val--;
if ( val > 0x1f ) {
printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
val = 0x1f;
}
__cpm_set_ldiv( val );
REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
__cpm_start_lcd();
udelay(1000);
REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
return 0;
}

260
package/uboot-xburst/files/cpu/mips/jz_lcd.h
View File

@ -1,260 +0,0 @@
/*
* JzRISC lcd controller
*
* xiangfu liu <xiangfu.z@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __JZLCD_H__
#define __JZLCD_H__
#include <asm/io.h>
/*
* change u-boot macro to celinux macro
*/
/* Chip type */
#if defined(CONFIG_JZ4740)
#define CONFIG_MIPS_JZ4740 1
#endif
/* board type */
#if defined(CONFIG_NANONOTE)
#define CONFIG_MIPS_JZ4740_PI 1
#endif
#define mdelay(n) udelay((n)*1000)
/*
* change u-boot macro to celinux macro
*/
#define NR_PALETTE 256
struct lcd_desc{
unsigned int next_desc; /* LCDDAx */
unsigned int databuf; /* LCDSAx */
unsigned int frame_id; /* LCDFIDx */
unsigned int cmd; /* LCDCMDx */
};
#define MODE_MASK 0x0f
#define MODE_TFT_GEN 0x00
#define MODE_TFT_SHARP 0x01
#define MODE_TFT_CASIO 0x02
#define MODE_TFT_SAMSUNG 0x03
#define MODE_CCIR656_NONINT 0x04
#define MODE_CCIR656_INT 0x05
#define MODE_STN_COLOR_SINGLE 0x08
#define MODE_STN_MONO_SINGLE 0x09
#define MODE_STN_COLOR_DUAL 0x0a
#define MODE_STN_MONO_DUAL 0x0b
#define MODE_8BIT_SERIAL_TFT 0x0c
#define MODE_TFT_18BIT (1<<7)
#define STN_DAT_PIN1 (0x00 << 4)
#define STN_DAT_PIN2 (0x01 << 4)
#define STN_DAT_PIN4 (0x02 << 4)
#define STN_DAT_PIN8 (0x03 << 4)
#define STN_DAT_PINMASK STN_DAT_PIN8
#define STFT_PSHI (1 << 15)
#define STFT_CLSHI (1 << 14)
#define STFT_SPLHI (1 << 13)
#define STFT_REVHI (1 << 12)
#define SYNC_MASTER (0 << 16)
#define SYNC_SLAVE (1 << 16)
#define DE_P (0 << 9)
#define DE_N (1 << 9)
#define PCLK_P (0 << 10)
#define PCLK_N (1 << 10)
#define HSYNC_P (0 << 11)
#define HSYNC_N (1 << 11)
#define VSYNC_P (0 << 8)
#define VSYNC_N (1 << 8)
#define DATA_NORMAL (0 << 17)
#define DATA_INVERSE (1 << 17)
/* Jz LCDFB supported I/O controls. */
#define FBIOSETBACKLIGHT 0x4688
#define FBIODISPON 0x4689
#define FBIODISPOFF 0x468a
#define FBIORESET 0x468b
#define FBIOPRINT_REG 0x468c
/*
* LCD panel specific definition
*/
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
#define MODE 0xcd /* 24bit parellel RGB */
#endif
#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
#define MODE 0xc9 /* 8bit serial RGB */
#endif
#if defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */
#define SPEN (32*2+21) /*LCD_SPL */
#define SPCK (32*2+23) /*LCD_CLS */
#define SPDA (32*2+22) /*LCD_D12 */
#define LCD_RET (32*3+27)
#else
#error "cpu/misp/Jzlcd.h, please define SPI pins on your board."
#endif
#define __spi_write_reg1(reg, val) \
do { \
unsigned char no;\
unsigned short value;\
unsigned char a=0;\
unsigned char b=0;\
a=reg;\
b=val;\
__gpio_set_pin(SPEN);\
__gpio_set_pin(SPCK);\
__gpio_clear_pin(SPDA);\
__gpio_clear_pin(SPEN);\
udelay(25);\
value=((a<<8)|(b&0xFF));\
for(no=0;no<16;no++)\
{\
__gpio_clear_pin(SPCK);\
if((value&0x8000)==0x8000)\
__gpio_set_pin(SPDA);\
else\
__gpio_clear_pin(SPDA);\
udelay(25);\
__gpio_set_pin(SPCK);\
value=(value<<1); \
udelay(25);\
}\
__gpio_set_pin(SPEN);\
udelay(100);\
} while (0)
#define __spi_write_reg(reg, val) \
do {\
__spi_write_reg1((reg<<2|2), val);\
udelay(100); \
}while(0)
#define __lcd_special_pin_init() \
do { \
__gpio_as_output(SPEN); /* use SPDA */\
__gpio_as_output(SPCK); /* use SPCK */\
__gpio_as_output(SPDA); /* use SPDA */\
__gpio_as_output(LCD_RET);\
} while (0)
#if defined(CONFIG_NANONOTE)
#define __lcd_special_on() \
do { \
udelay(50);\
__spi_write_reg1(0x05, 0x16); \
__spi_write_reg1(0x04, 0x0b); \
__spi_write_reg1(0x07, 0x8d); \
__spi_write_reg1(0x01, 0x95); \
__spi_write_reg1(0x08, 0xc0); \
__spi_write_reg1(0x03, 0x40); \
__spi_write_reg1(0x06, 0x15); \
__spi_write_reg1(0x05, 0xd7); \
} while (0) /* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */
#define __lcd_special_off() \
do { \
__spi_write_reg1(0x05, 0x5e); \
} while (0)
#endif /* CONFIG_NANONOTE */
#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */
#ifndef __lcd_special_pin_init
#define __lcd_special_pin_init()
#endif
#ifndef __lcd_special_on
#define __lcd_special_on()
#endif
#ifndef __lcd_special_off
#define __lcd_special_off()
#endif
/*
* Platform specific definition
*/
#if defined(CONFIG_MIPS_JZ4740_PI)
/* 100 level: 0,1,...,100 */
#define __lcd_set_backlight_level(n)\
do { \
__gpio_as_output(32*3+27); \
__gpio_set_pin(32*3+27); \
} while (0)
#define __lcd_close_backlight() \
do { \
__gpio_as_output(GPIO_PWM); \
__gpio_clear_pin(GPIO_PWM); \
} while (0)
#define __lcd_display_pin_init() \
do { \
__gpio_as_output(GPIO_DISP_OFF_N); \
__cpm_start_tcu(); \
__lcd_special_pin_init(); \
} while (0)
/* __lcd_set_backlight_level(100); \*/
#define __lcd_display_on() \
do { \
__gpio_set_pin(GPIO_DISP_OFF_N); \
__lcd_special_on(); \
} while (0)
#define __lcd_display_off() \
do { \
__lcd_special_off(); \
__gpio_clear_pin(GPIO_DISP_OFF_N); \
} while (0)
#endif /* CONFIG_MIPS_JZ4740_PI) */
/*****************************************************************************
* LCD display pin dummy macros
*****************************************************************************/
#ifndef __lcd_display_pin_init
#define __lcd_display_pin_init()
#endif
#ifndef __lcd_display_on
#define __lcd_display_on()
#endif
#ifndef __lcd_display_off
#define __lcd_display_off()
#endif
#ifndef __lcd_set_backlight_level
#define __lcd_set_backlight_level(n)
#endif

250
package/uboot-xburst/files/drivers/mtd/nand/jz4740_nand.c Normal file
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@ -0,0 +1,250 @@
/*
* Platform independend driver for JZ4740.
*
* Copyright (c) 2007 Ingenic Semiconductor Inc.
* Author: <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <asm/io.h>
#include <asm/jz4740.h>
#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
#define BIT(x) (1 << (x))
#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
#define JZ_NAND_ECC_CTRL_RS BIT(2)
#define JZ_NAND_ECC_CTRL_RESET BIT(1)
#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
.eccbytes = 72,
.eccpos = {
12, 13, 14, 15, 16, 17, 18, 19,
20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 30, 31, 32, 33, 34, 35,
36, 37, 38, 39, 40, 41, 42, 43,
44, 45, 46, 47, 48, 49, 50, 51,
52, 53, 54, 55, 56, 57, 58, 59,
60, 61, 62, 63, 64, 65, 66, 67,
68, 69, 70, 71, 72, 73, 74, 75,
76, 77, 78, 79, 80, 81, 82, 83},
.oobfree = {
{.offset = 2,
.length = 10},
{.offset = 84,
.length = 44}}
};
static int is_reading;
static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_ALE)
this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
else if (ctrl & NAND_CLE)
this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
else
this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
if (ctrl & NAND_NCE)
REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
else
REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int jz_nand_device_ready(struct mtd_info *mtd)
{
udelay(20);
return (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
}
void board_nand_select_device(struct nand_chip *nand, int chip)
{
/*
* Don't use "chip" to address the NAND device,
* generate the cs from the address where it is encoded.
*/
}
static int jz_nand_rs_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
u_char* ecc_code)
{
uint32_t reg, status;
int i;
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
if(is_reading)
return 0;
do {
status = REG_EMC_NFINTS;
} while(!(status & EMC_NFINTS_ENCF));
__nand_ecc_disable();
for(i = 0; i < 9; i++)
ecc_code[i] = *(paraddr + i);
return 0;
}
static void jz_nand_hwctl(struct mtd_info* mtd, int mode)
{
uint32_t reg;
REG_EMC_NFINTS = 0;
reg = REG_EMC_NFECR;
reg |= JZ_NAND_ECC_CTRL_RESET;
reg |= JZ_NAND_ECC_CTRL_ENABLE;
reg |= JZ_NAND_ECC_CTRL_RS;
switch(mode) {
case NAND_ECC_READ:
reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
is_reading = 1;
break;
case NAND_ECC_WRITE:
reg |= JZ_NAND_ECC_CTRL_ENCODING;
is_reading = 0;
break;
default:
break;
}
REG_EMC_NFECR = reg;
}
/* Correct 1~9-bit errors in 512-bytes data */
static void jz_rs_correct(unsigned char *dat, int idx, int mask)
{
int i;
idx--;
i = idx + (idx >> 3);
if (i >= 512)
return;
mask <<= (idx & 0x7);
dat[i] ^= mask & 0xff;
if (i < 511)
dat[i+1] ^= (mask >> 8) & 0xff;
}
static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
int k;
uint32_t reg, status;
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
/* Set PAR values */
static uint8_t all_ff_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f};
if (read_ecc[0] == 0xff &&
read_ecc[1] == 0xff &&
read_ecc[2] == 0xff &&
read_ecc[3] == 0xff &&
read_ecc[4] == 0xff &&
read_ecc[5] == 0xff &&
read_ecc[6] == 0xff &&
read_ecc[7] == 0xff &&
read_ecc[8] == 0xff) {
for (k = 0; k < 9; k++)
*(paraddr + k) = all_ff_ecc[k];
} else {
for (k = 0; k < 9; k++)
*(paraddr + k) = read_ecc[k];
}
/* Set PRDY */
REG_EMC_NFECR |= EMC_NFECR_PRDY;
/* Wait for completion */
do {
status = REG_EMC_NFINTS;
} while (!(status & EMC_NFINTS_DECF));
__nand_ecc_disable();
/* Check decoding */
if (status & EMC_NFINTS_ERR) {
if (status & EMC_NFINTS_UNCOR) {
printk("uncorrectable ecc\n");
while(1);
return -1;
}
uint32_t errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
switch (errcnt) {
case 4:
jz_rs_correct(dat,
(REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
(REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 3:
jz_rs_correct(dat,
(REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
(REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 2:
jz_rs_correct(dat,
(REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
(REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 1:
jz_rs_correct(dat,
(REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
(REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
return errcnt;
default:
break;
}
}
return 0;
}
/*
* Main initialization routine
*/
int board_nand_init(struct nand_chip *nand)
{
/* EMC setup, Set NFE bit */
REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
REG_EMC_SMCR1 = 0x094c4400;
/* REG_EMC_SMCR3 = 0x04444400; */
nand->IO_ADDR_R = JZ_NAND_DATA_ADDR;
nand->IO_ADDR_W = JZ_NAND_DATA_ADDR;
nand->cmd_ctrl = jz_nand_cmd_ctrl;
nand->dev_ready = jz_nand_device_ready;
nand->ecc.hwctl = jz_nand_hwctl;
nand->ecc.correct = jz_nand_rs_correct_data;
nand->ecc.calculate = jz_nand_rs_calculate_ecc;
nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
nand->ecc.layout = &qi_lb60_ecclayout_2gb;
nand->chip_delay = 50;
return 0;
}
#endif /* (CONFIG_CMD_NAND) */

26
package/uboot-xburst/files/include/configs/avt2.h
View File

@ -1,26 +0,0 @@
#ifndef __CONFIG_AVT2_H
#define __CONFIG_AVT2_H
#include <configs/nanonote.h>
#define CONFIG_AVT2 1
#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait avt2=1"
#define CONFIG_BOOTARGSFROMSD "mem=64M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait avt2=1"
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
/* SDRAM paramters */
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
#define SDRAM_COL 10 /* Column address: 8 to 12 */
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
/* SDRAM Timings, unit: ns */
#define SDRAM_TRAS 45 /* RAS# Active Time */
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
#define SDRAM_TPC 20 /* RAS# Precharge Time */
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
#endif /* __CONFIG_AVT_H */

309
package/uboot-xburst/files/include/configs/n516.h
View File

@ -1,309 +0,0 @@
/*
* (C) Copyright 2006
* Ingenic Semiconductor, <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file contains the configuration parameters for the pavo board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
//#define DEBUG
//#define DEBUG_SHELL
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_JzRISC 1 /* JzRISC core */
#define CONFIG_JZSOC 1 /* Jz SoC */
#define CONFIG_JZ4740 1 /* Jz4740 SoC */
#define CONFIG_PAVO 1 /* PAVO validation board */
#define CONFIG_BOARD_NAME "n516"
#define CONFIG_BOARD_HWREV "1.0"
#define CONFIG_FIRMWARE_EPOCH "0"
#define CONFIG_UPDATE_TMPBUF 0x80600000
#define CONFIG_UPDATE_CHUNKSIZE 0x800000
#define CONFIG_UPDATE_FILENAME "update.oifw"
#define CONFIG_UPDATE_FILEEXT ".oifw"
#define CONFIG_UBI_PARTITION "UBI"
#define CONFIG_SKIP_LOWLEVEL_INIT 1
#undef CONFIG_SKIP_RELOCATE_UBOOT
#if 0
#define CONFIG_LCD /* LCD support */
#define CONFIG_JZLCD_METRONOME_800x600
#define LCD_BPP LCD_COLOR8
#define WFM_DATA_SIZE ( 1 << 14 )
#define CONFIG_METRONOME_WF_LEN (64 * (1 << 10))
#define CONFIG_METRONOME_WF_NAND_OFFSET (0x100000)
#define BMP_LOGO_HEIGHT 0
#define CONFIG_UBI_WF_VOLUME "waveforms"
#define CONFIG_UBI_BOOTSPLASH_VOLUME "bootsplash"
#define CONFIG_METRONOME_BOOTSPLASH_LEN 480000
#endif
#if 0
#define CONFIG_JZSOC_I2C
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0
#define CONFIG_LPC_I2C_ADDR 0x54
#endif
#define JZ4740_NORBOOT_CFG JZ4740_NORBOOT_16BIT /* NOR Boot config code */
#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 /* NAND Boot config code */
#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL/256) /* incrementer freq */
#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
#define CONFIG_BAUDRATE 57600
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC 1
#define CONFIG_JZ_MMC 1
#define CONFIG_FAT 1
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 ">"
#define CONFIG_CMDLINE_EDITING
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI /* bdinfo */
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_ECHO /* echo arguments */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_ITEST /* Integer (and string) test */
#undef CONFIG_CMD_LOADB /* loadb */
#undef CONFIG_CMD_LOADS /* loads */
#undef CONFIG_CMD_NFS /* NFS support */
#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#undef CONFIG_CMD_SOURCE /* "source" command support */
#undef CONFIG_CMD_XIMG /* Load part of Multi Image */
#undef CONFIG_CMD_NET
//#define CONFIG_CMD_ASKENV
//#define CONFIG_CMD_DHCP
//#define CONFIG_CMD_PING
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
/*#define CONFIG_CMD_UBI*/
/*#define CONFIG_CMD_MTDPARTS*/
//#define CONFIG_CMD_JFFS2
//#define CONFIG_JFFS2_NAND
//#define CONFIG_JFFS2_CMDLINE
#define CONFIG_CMD_UPDATE
#define CONFIG_DOS_PARTITION
/*#define CONFIG_MTD_PARTITIONS*/
#define CONFIG_RBTREE
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#if 0
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTFILE uImage /* file to load */
#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ip=off rootfstype=ubifs root=ubi:rootfs ubi.mtd=UBI rw panic=5 " MTDPARTS_DEFAULT
#define CONFIG_BOOTCOMMAND "check_and_update; setenv bootargs $bootargs $batt_level_param; ubi read 0x80600000 bootsplash && show_image 0x80600000; ubi read 0x80600000 kernel; bootm 0x80600000; ubi read 0x80600000 errorsplash && show_image 0x80600000; while test 0 = 0; do check_and_update; done"
#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
#define CONFIG_IPADDR 192.168.111.1
#define CONFIG_SERVERIP 192.168.111.2
#define MTDIDS_DEFAULT "nand0=jz4740-nand"
#define MTDPARTS_DEFAULT "mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)"
#define CONFIG_EXTRA_ENV_SETTINGS "mtdids=nand0=jz4740-nand\0mtdparts=mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)\0" \
"stdout=serial\0stderr=lcd\0"
#endif
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTFILE "uImage" /* file to load */
#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
* Serial download configuration
*
*/
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "n516 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
#define CONFIG_SYS_MALLOC_LEN 1024*1024*2
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x80800000
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#endif
/*-----------------------------------------------------------------------
* NAND FLASH configuration
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xB8000000
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 8k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 8kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
*/
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 63 /* NAND bad block was marked at this page in a block, starting from 0 */
#define CONFIG_SYS_NAND_ECC_POS 6
#ifdef CONFIG_ENV_IS_IN_NAND
//#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_SIZE (128 * 1024)
//#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE) /* environment starts here */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
//#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* NOR FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
#define PHYS_FLASH_1 0xa8000000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* in pavo/config.mk TEXT_BASE=0x88000000*/
#define CONFIG_SYS_SYS_MONITOR_BASE TEXT_BASE /* in pavo/config.mk TEXT_BASE=0x88000000*/
#define CONFIG_SYS_MONITOR_LEN (256*1024) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_ADDR 0xa8040000
#define CONFIG_ENV_SIZE 0x20000
#endif
/*-----------------------------------------------------------------------
* SDRAM Info.
*/
#define CONFIG_NR_DRAM_BANKS 1
// SDRAM paramters
#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
#define SDRAM_COL 9 /* Column address: 8 to 12 */
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
// SDRAM Timings, unit: ns
#define SDRAM_TRAS 45 /* RAS# Active Time */
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
#define SDRAM_TPC 20 /* RAS# Precharge Time */
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
/*-----------------------------------------------------------------------
* GPIO definition
*/
#define GPIO_SD_VCC_EN_N 113 /* GPD17 */
#define GPIO_SD_CD_N 103 /* GPD7 */
#define GPIO_SD_WP 111 /* GPD15 */
#define GPIO_USB_DETE 115 /* GPD6 */
//#define GPIO_DC_DETE_N 103 /* GPD7 */
#define GPIO_CHARG_STAT_N 112 /* GPD15 */
#define GPIO_DISP_OFF_N 97 /* GPD1 */
#define GPIO_UDC_HOTPLUG 100 /* GPD4 */
#define GPIO_LED_EN 124 /* GPD28 */
#define GPIO_RST_L 50 /* GPB18 LCD_SPL */
#define GPIO_LCDRDY 49 /* GPB17 LCD_CLS */
#define GPIO_STBY 86 /* GPC22 LCD_PS */
#define GPIO_ERR 87 /* GPC23 LCD_REV */
#endif /* __CONFIG_H */

14
package/uboot-xburst/files/include/configs/nanonote.h
View File

@ -18,6 +18,7 @@
#define CONFIG_JZSOC 1 /* Jz SoC */ #define CONFIG_JZSOC 1 /* Jz SoC */
#define CONFIG_JZ4740 1 /* Jz4740 SoC */ #define CONFIG_JZ4740 1 /* Jz4740 SoC */
#define CONFIG_NANONOTE 1 #define CONFIG_NANONOTE 1
#define CONFIG_NAND_JZ4740
#define BOOT_FROM_SDCARD 1 #define BOOT_FROM_SDCARD 1
#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */ #define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
@ -116,12 +117,15 @@
/* nand bad block was marked at this page in a block, start from 0 */ /* nand bad block was marked at this page in a block, start from 0 */
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127 #define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
/* ECC offset position in oob area, default value is 6 if it isn't defined */ /* ECC offset position in oob area, default value is 6 if it isn't defined */
#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE) #define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ECCSIZE 512
#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_ECCBYTES 9
#define CONFIG_SYS_NAND_BASE 0xB8000000 #define CONFIG_SYS_NAND_BASE 0xB8000000
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
/* /*
* IPL (Initial Program Loader, integrated inside CPU) * IPL (Initial Program Loader, integrated inside CPU)
@ -148,7 +152,7 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */ #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_SIZE (4 << 10)
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
/* environment starts here */ /* environment starts here */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)

1
package/uboot-xburst/files/include/configs/qi_lb60.h
View File

@ -5,6 +5,7 @@
#define CONFIG_QI_LB60 1 #define CONFIG_QI_LB60 1
//#define DEBUG
#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" #define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
#define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait" #define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" #define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"

200
package/uboot-xburst/files/include/configs/sakc.h
View File

@ -1,200 +0,0 @@
/*
* Authors: Xiangfu Liu <xiangfu.z@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 3 of the License, or (at your option) any later version.
*/
/*
* This file contains the configuration parameters for SAKC.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define DEBUG
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_JzRISC 1 /* JzRISC core */
#define CONFIG_JZSOC 1 /* Jz SoC */
#define CONFIG_JZ4725 1 /* Jz4725 SoC */
#define CONFIG_JZ4740 1 /* Jz4740 SoC */
#define CONFIG_SAKC 1 /* SAKC board */
#define MMC_BUS_WIDTH_1BIT 1 /* 1 for MMC 1Bit Bus Width */
//#define CONFIG_LCD 1 /* LCD support */
//#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
//#define CONFIG_SYS_WHITE_ON_BLACK 1
#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
#define CONFIG_BAUDRATE 57600
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_MMC 1
#define CONFIG_FAT 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SKIP_LOWLEVEL_INIT 1
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage" /* file to load */
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
#define CONFIG_EXTRA_ENV_SETTINGS 1
#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
/*
* Command line configuration.
*/
#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SOURCE /* "source" command support */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
/*
* Serial download configuration
*/
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "SAKC# " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
#define CONFIG_SYS_MALLOC_LEN 128 * 1024
#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x80800000
/*
* Environment
*/
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
/*
* NAND FLASH configuration
*/
/* NAND Boot config code */
#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
#define SAKC_NAND_SIZE 1 /* if board nand flash is 1GB, set to 1
* if board nand flash is 2GB, set to 2
* for change the PAGE_SIZE and BLOCK_SIZE
* will delete when there is no 1GB flash
*/
#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * SAKC_NAND_SIZE)
/* nand chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * SAKC_NAND_SIZE << 10)
/* nand bad block was marked at this page in a block, start from 0 */
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
/* ECC offset position in oob area, default value is 6 if it isn't defined */
#define CONFIG_SYS_NAND_ECC_POS (6 * SAKC_NAND_SIZE)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xB8000000
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 8k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 8kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
*/
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
/* Start NUB from this addr*/
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
/* environment starts here */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
/*
* SDRAM Info.
*/
#define CONFIG_NR_DRAM_BANKS 1
/* SDRAM paramters */
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
#define SDRAM_COL 9 /* Column address: 8 to 12 */
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
/* SDRAM Timings, unit: ns */
#define SDRAM_TRAS 45 /* RAS# Active Time */
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
#define SDRAM_TPC 20 /* RAS# Precharge Time */
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
/*
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* GPIO definition
*/
#define GPIO_SD_DETECT (2 * 32 + 27)
#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
#endif /* __CONFIG_H */

104
package/uboot-xburst/files/nand_spl/board/nanonote/Makefile
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@ -1,104 +0,0 @@
#
# (C) Copyright 2006
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o usb_boot.o
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
nandobj := $(OBJTREE)/nand_spl/
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
cat $< $(nandobj)junk1 > $(nandobj)junk2
dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
rm -f $(nandobj)junk*
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS)
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
# create symbolic links for common files
# from cpu directory
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
$(obj)usb_boot.S:
@rm -f $(obj)usb_boot.S
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
$(obj)cpu.c:
@rm -f $(obj)cpu.c
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
$(obj)jz4740.c:
@rm -f $(obj)jz4740.c
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
$(obj)jz_serial.c:
@rm -f $(obj)jz_serial.c
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
# from nand_spl directory
$(obj)nand_boot_jz4740.c:
@rm -f $(obj)nand_boot_jz4740.c
ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

63
package/uboot-xburst/files/nand_spl/board/nanonote/u-boot.lds
View File

@ -1,63 +0,0 @@
/*
* (C) Copyright 2005
* Ingenic Semiconductor, <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

104
package/uboot-xburst/files/nand_spl/board/sakc/Makefile
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@ -1,104 +0,0 @@
#
# (C) Copyright 2006
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o usb_boot.o
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
nandobj := $(OBJTREE)/nand_spl/
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
cat $< $(nandobj)junk1 > $(nandobj)junk2
dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
rm -f $(nandobj)junk*
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS)
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
# create symbolic links for common files
# from cpu directory
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
$(obj)usb_boot.S:
@rm -f $(obj)usb_boot.S
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
$(obj)cpu.c:
@rm -f $(obj)cpu.c
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
$(obj)jz4740.c:
@rm -f $(obj)jz4740.c
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
$(obj)jz_serial.c:
@rm -f $(obj)jz_serial.c
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
# from nand_spl directory
$(obj)nand_boot_jz4740.c:
@rm -f $(obj)nand_boot_jz4740.c
ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

34
package/uboot-xburst/files/nand_spl/board/sakc/config.mk
View File

@ -1,34 +0,0 @@
#
# (C) Copyright 2006
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Ingenic JZ4740 Reference Platform
#
#
# TEXT_BASE for SPL:
#
# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000,
# in the first 4kBytes of memory space in cache. So we set
# TEXT_BASE to starting address in internal cache here.
#
TEXT_BASE = 0x80000000

63
package/uboot-xburst/files/nand_spl/board/sakc/u-boot.lds
View File

@ -1,63 +0,0 @@
/*
* (C) Copyright 2005
* Ingenic Semiconductor, <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

194
package/uboot-xburst/files/nand_spl/board/xburst/nanonote/.depend Normal file
View File

@ -0,0 +1,194 @@
start.o: start.S \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config_defaults.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/qi_lb60.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/nanonote.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/version.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/version_autogenerated.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/regdef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/sgidefs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/mipsregs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/addrspace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/cacheops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/jz4740.h
usbboot.o: usbboot.S
nand_boot_jz4740.o: nand_boot_jz4740.c \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/common.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config_defaults.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/qi_lb60.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/nanonote.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/byteorder.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/little_endian.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/swab.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/generic.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/sgidefs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/system.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/ptrace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/isadep.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/string.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/string.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stdarg.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/part.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/ide.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/flash.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/image.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/compiler.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/lmb.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/u-boot.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/command.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/global_data.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/regdef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/net.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/u-boot/crc.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/nand.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/mtd/compat.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/mtd/mtd.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/div64.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/mtd/mtd-abi.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/mtd/nand.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/mtd/bbm.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/io.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/addrspace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/jz4740.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/cacheops.h
cpu.o: cpu.c \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/common.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config_defaults.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/qi_lb60.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/nanonote.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/byteorder.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/little_endian.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/swab.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/generic.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/sgidefs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/system.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/ptrace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/isadep.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/string.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/string.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stdarg.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/part.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/ide.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/flash.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/image.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/compiler.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/lmb.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/u-boot.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/command.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/global_data.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/regdef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/net.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/u-boot/crc.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/netdev.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/mipsregs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/cacheops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/reboot.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/jz4740.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/addrspace.h
jz4740.o: jz4740.c \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config_defaults.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/qi_lb60.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/nanonote.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/common.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/byteorder.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/little_endian.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/swab.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/generic.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/sgidefs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/system.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/ptrace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/isadep.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/string.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/string.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stdarg.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/part.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/ide.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/flash.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/image.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/compiler.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/lmb.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/u-boot.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/command.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/global_data.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/regdef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/net.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/u-boot/crc.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/jz4740.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/addrspace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/cacheops.h
jz_serial.o: jz_serial.c \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/config_defaults.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/qi_lb60.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/configs/nanonote.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/common.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/bitops.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/config.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/posix_types.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/byteorder.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/little_endian.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/swab.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/byteorder/generic.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/sgidefs.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/system.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/ptrace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/isadep.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/linux/string.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/string.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stdarg.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/part.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/ide.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/flash.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/image.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/compiler.h \
/home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include/stddef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/lmb.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/u-boot.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/command.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/global_data.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/regdef.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/net.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/u-boot/crc.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/jz4740.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/addrspace.h \
/home/xiangfu/workspace/PanGu/u-boot-2010.03/include/asm/cacheops.h

18
package/uboot-xburst/files/nand_spl/board/n516/Makefile → package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile
View File

@ -22,14 +22,14 @@
# #
include $(TOPDIR)/config.mk include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk TEXT_BASE = 0x80000000
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
AFLAGS += -DCONFIG_NAND_SPL AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o usb_boot.o SOBJS = start.o usbboot.o
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@ -65,23 +65,23 @@ $(nandobj)u-boot-spl: $(OBJS)
# from cpu directory # from cpu directory
$(obj)start.S: $(obj)start.S:
@rm -f $(obj)start.S @rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S
$(obj)usb_boot.S: $(obj)usbboot.S:
@rm -f $(obj)usb_boot.S @rm -f $(obj)usbboot.S
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S
$(obj)cpu.c: $(obj)cpu.c:
@rm -f $(obj)cpu.c @rm -f $(obj)cpu.c
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c
$(obj)jz4740.c: $(obj)jz4740.c:
@rm -f $(obj)jz4740.c @rm -f $(obj)jz4740.c
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c
$(obj)jz_serial.c: $(obj)jz_serial.c:
@rm -f $(obj)jz_serial.c @rm -f $(obj)jz_serial.c
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c
# from nand_spl directory # from nand_spl directory
$(obj)nand_boot_jz4740.c: $(obj)nand_boot_jz4740.c:

0
package/uboot-xburst/files/nand_spl/board/n516/config.mk → package/uboot-xburst/files/nand_spl/board/xburst/nanonote/config.mk
View File

0
package/uboot-xburst/files/nand_spl/board/n516/u-boot.lds → package/uboot-xburst/files/nand_spl/board/xburst/nanonote/u-boot.lds
View File

1
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c
View File

@ -372,6 +372,7 @@ void nand_boot(void)
*/ */
gpio_init(); gpio_init();
pll_init(); pll_init();
REG_GPIO_PXSELS(2) = 0x80000000;
serial_init(); serial_init();
sdram_init(); sdram_init();
serial_puts("\n\nNAND Secondary Program Loader\n\n"); serial_puts("\n\nNAND Secondary Program Loader\n\n");

1568
package/uboot-xburst/patches/001-xburst.patch
View File

File diff suppressed because it is too large Load Diff

13
package/uboot-xburst/patches/002-disable-examples.patch
View File

@ -1,13 +0,0 @@
--- a/Makefile 2010-05-13 16:43:21.000000000 +0200
+++ b/Makefile 2010-05-13 16:43:29.000000000 +0200
@@ -139,9 +139,7 @@
# The "tools" are needed early, so put this first
# Don't include stuff already done in $(LIBS)
-SUBDIRS = tools \
- examples/standalone \
- examples/api
+SUBDIRS = tools
.PHONY : $(SUBDIRS)

12
package/uboot-xburst/patches/005-i2c.patch
View File

@ -1,12 +0,0 @@
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 29bda85..a529eb7 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
+COBJS-$(CONFIG_JZSOC_I2C) += jz_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)

24
package/uboot-xburst/patches/009-n516.patch
View File

@ -1,24 +0,0 @@
diff --git a/Makefile b/Makefile
index 1703fad..9b88cab 100644
--- a/Makefile
+++ b/Makefile
@@ -3470,6 +3470,19 @@ avt2_config : unconfig
@$(MKCONFIG) -a avt2 mips mips nanonote
@echo "TEXT_BASE = 0x80100000" > $(obj)board/nanonote/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
+n516_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_N516 1" >>include/config.h
+ @./mkconfig -a n516 mips mips n516
+
+n516_nand_config : unconfig
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for n516"
+ @./mkconfig -a n516 mips mips n516
+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/n516/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#########################################################################
## MIPS64 5Kc
#########################################################################

31
package/uboot-xburst/patches/010-sakc.patch
View File

@ -1,31 +0,0 @@
diff --git a/Makefile b/Makefile
index 9b88cab..40cf312 100644
--- a/Makefile
+++ b/Makefile
@@ -3483,6 +3483,13 @@ n516_nand_config : unconfig
@echo "TEXT_BASE = 0x80100000" > $(obj)board/n516/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+sakc_config : unconfig
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for SAKC"
+ @$(MKCONFIG) -a sakc mips mips sakc
+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/sakc/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#########################################################################
## MIPS64 5Kc
#########################################################################
diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
index afeb909..25dd71b 100644
--- a/cpu/mips/Makefile
+++ b/cpu/mips/Makefile
@@ -35,7 +35,7 @@ COBJS-$(CONFIG_PURPLE) += asc_serial.o
COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
COBJS-$(CONFIG_JZSOC) += jz4740.o jz_serial.o jz_mmc.o jz4740_nand.o
COBJS-$(CONFIG_NANONOTE) += nanonote_gpm940b0.o
-
+COBJS-$(CONFIG_SAKC) += nanonote_gpm940b0.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))