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ramips: rt305x: fix CPU clock detection on RT3352

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31401 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2012-04-21 12:30:47 +00:00
parent feaef768b3
commit 3ff5d8da9a
2 changed files with 35 additions and 11 deletions
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5
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
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@@ -80,6 +80,11 @@
#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1
#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2
#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
#define RT305X_GPIO_MODE_I2C BIT(0)
#define RT305X_GPIO_MODE_SPI BIT(1)
#define RT305X_GPIO_MODE_UART0_SHIFT 2