mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 15:06:47 +02:00
kernel: bring ssb in sync with upstream (as of current wireless-testing)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21269 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
5df1ac31da
commit
40ccc298ba
@ -345,7 +345,7 @@
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}
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}
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--- a/arch/mips/mm/tlbex.c
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -739,6 +739,9 @@ static void __cpuinit build_r4000_tlb_re
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@@ -733,6 +733,9 @@ static void __cpuinit build_r4000_tlb_re
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/* No need for uasm_i_nop */
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/* No need for uasm_i_nop */
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}
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}
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@ -355,7 +355,7 @@
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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#else
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#else
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@@ -1193,6 +1196,9 @@ build_r4000_tlbchange_handler_head(u32 *
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@@ -1185,6 +1188,9 @@ build_r4000_tlbchange_handler_head(u32 *
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struct uasm_reloc **r, unsigned int pte,
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struct uasm_reloc **r, unsigned int pte,
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unsigned int ptr)
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unsigned int ptr)
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{
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{
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@ -1,36 +0,0 @@
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From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
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From: Jochen Friedrich <jochen@scram.de>
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Date: Wed, 3 Feb 2010 21:28:11 +0100
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Subject: [PATCH 1/1] ssb: fix interrupt assignment
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Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
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anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
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Also remove a bogus comment.
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Signed-off-by: Jochen Friedrich <jochen@scram.de>
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Signed-off-by: John W. Linville <linville@tuxdriver.com>
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---
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drivers/ssb/driver_mipscore.c | 5 ++++-
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1 files changed, 4 insertions(+), 1 deletions(-)
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
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set_irq(dev, irq++);
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}
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break;
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- /* fallthrough */
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case SSB_DEV_PCI:
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case SSB_DEV_ETHERNET:
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case SSB_DEV_ETHERNET_GBIT:
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@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
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set_irq(dev, irq++);
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break;
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}
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+ /* fallthrough */
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+ case SSB_DEV_EXTIF:
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+ set_irq(dev, 0);
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+ break;
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}
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}
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ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
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@ -1,6 +1,6 @@
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--- a/drivers/ssb/driver_chipcommon.c
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--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
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@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
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void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
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void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m)
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u32 *plltype, u32 *n, u32 *m)
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{
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{
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@ -9,7 +9,7 @@
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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switch (*plltype) {
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switch (*plltype) {
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@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
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@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
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void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
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void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m)
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u32 *plltype, u32 *n, u32 *m)
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{
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{
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@ -31,7 +31,7 @@
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}
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}
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--- a/drivers/ssb/main.c
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -1066,6 +1066,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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if (bus->chip_id == 0x5365) {
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if (bus->chip_id == 0x5365) {
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rate = 100000000;
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rate = 100000000;
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@ -102,7 +102,7 @@
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tg3_readphy(tp, MII_BMSR, &tmp);
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tg3_readphy(tp, MII_BMSR, &tmp);
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if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
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if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
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(tmp & BMSR_LSTATUS))
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(tmp & BMSR_LSTATUS))
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@@ -6264,6 +6289,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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@@ -6273,6 +6298,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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int i;
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int i;
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u32 val;
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u32 val;
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@ -114,7 +114,7 @@
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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for (i = 0; i < 200; i++) {
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@@ -6541,6 +6571,14 @@ static int tg3_chip_reset(struct tg3 *tp
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@@ -6550,6 +6580,14 @@ static int tg3_chip_reset(struct tg3 *tp
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tw32(0x5000, 0x400);
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tw32(0x5000, 0x400);
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}
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}
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@ -129,7 +129,7 @@
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tw32(GRC_MODE, tp->grc_mode);
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tw32(GRC_MODE, tp->grc_mode);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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@@ -6695,9 +6733,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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@@ -6704,9 +6742,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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return -ENODEV;
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return -ENODEV;
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}
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}
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@ -145,7 +145,7 @@
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return 0;
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return 0;
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}
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}
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@@ -6760,6 +6801,11 @@ static int tg3_load_5701_a0_firmware_fix
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@@ -6769,6 +6810,11 @@ static int tg3_load_5701_a0_firmware_fix
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const __be32 *fw_data;
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const __be32 *fw_data;
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int err, i;
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int err, i;
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@ -157,7 +157,7 @@
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fw_data = (void *)tp->fw->data;
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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/* Firmware blob starts with version numbers, followed by
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@@ -6819,6 +6865,11 @@ static int tg3_load_tso_firmware(struct
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@@ -6828,6 +6874,11 @@ static int tg3_load_tso_firmware(struct
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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int err, i;
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int err, i;
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@ -169,7 +169,7 @@
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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return 0;
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return 0;
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@@ -7906,6 +7957,11 @@ static void tg3_timer(unsigned long __op
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@@ -7915,6 +7966,11 @@ static void tg3_timer(unsigned long __op
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spin_lock(&tp->lock);
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spin_lock(&tp->lock);
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@ -181,7 +181,7 @@
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if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
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if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
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/* All of this garbage is because when using non-tagged
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/* All of this garbage is because when using non-tagged
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* IRQ status the mailbox/status_block protocol the chip
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* IRQ status the mailbox/status_block protocol the chip
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@@ -9791,6 +9847,11 @@ static int tg3_test_nvram(struct tg3 *tp
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@@ -9800,6 +9856,11 @@ static int tg3_test_nvram(struct tg3 *tp
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if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
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if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
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return 0;
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return 0;
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@ -193,7 +193,7 @@
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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return -EIO;
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return -EIO;
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@@ -10585,7 +10646,7 @@ static int tg3_ioctl(struct net_device *
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@@ -10594,7 +10655,7 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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spin_lock_bh(&tp->lock);
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@ -202,7 +202,7 @@
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spin_unlock_bh(&tp->lock);
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spin_unlock_bh(&tp->lock);
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data->val_out = mii_regval;
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data->val_out = mii_regval;
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@@ -10601,7 +10662,7 @@ static int tg3_ioctl(struct net_device *
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@@ -10610,7 +10671,7 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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spin_lock_bh(&tp->lock);
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@ -211,7 +211,7 @@
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spin_unlock_bh(&tp->lock);
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spin_unlock_bh(&tp->lock);
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return err;
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return err;
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@@ -11246,6 +11307,12 @@ static void __devinit tg3_get_5717_nvram
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@@ -11255,6 +11316,12 @@ static void __devinit tg3_get_5717_nvram
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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{
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@ -224,7 +224,7 @@
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tw32_f(GRC_EEPROM_ADDR,
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@@ -11506,6 +11573,9 @@ static int tg3_nvram_write_block(struct
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@@ -11515,6 +11582,9 @@ static int tg3_nvram_write_block(struct
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{
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{
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int ret;
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int ret;
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@ -234,7 +234,7 @@
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@@ -12788,6 +12858,11 @@ static int __devinit tg3_get_invariants(
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@@ -12800,6 +12870,11 @@ static int __devinit tg3_get_invariants(
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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@ -246,7 +246,7 @@
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/* Get eeprom hw config before calling tg3_set_power_state().
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLG2_IS_NIC flag must be
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* In particular, the TG3_FLG2_IS_NIC flag must be
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* determined before calling tg3_set_power_state() so that
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* determined before calling tg3_set_power_state() so that
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@@ -13177,6 +13252,10 @@ static int __devinit tg3_get_device_addr
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@@ -13189,6 +13264,10 @@ static int __devinit tg3_get_device_addr
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}
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}
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if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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@ -257,7 +257,7 @@
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#ifdef CONFIG_SPARC
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#ifdef CONFIG_SPARC
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if (!tg3_get_default_macaddr_sparc(tp))
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if (!tg3_get_default_macaddr_sparc(tp))
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return 0;
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return 0;
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@@ -13669,6 +13748,7 @@ static char * __devinit tg3_phy_string(s
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@@ -13681,6 +13760,7 @@ static char * __devinit tg3_phy_string(s
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case PHY_ID_BCM5704: return "5704";
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case PHY_ID_BCM5704: return "5704";
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case PHY_ID_BCM5705: return "5705";
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case PHY_ID_BCM5705: return "5705";
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case PHY_ID_BCM5750: return "5750";
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case PHY_ID_BCM5750: return "5750";
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@ -265,7 +265,7 @@
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case PHY_ID_BCM5752: return "5752";
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case PHY_ID_BCM5752: return "5752";
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case PHY_ID_BCM5714: return "5714";
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case PHY_ID_BCM5714: return "5714";
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case PHY_ID_BCM5780: return "5780";
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case PHY_ID_BCM5780: return "5780";
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@@ -13880,6 +13960,13 @@ static int __devinit tg3_init_one(struct
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@@ -13892,6 +13972,13 @@ static int __devinit tg3_init_one(struct
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tp->msg_enable = tg3_debug;
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tp->msg_enable = tg3_debug;
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else
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else
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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@ -291,7 +291,7 @@
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|
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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@@ -2821,6 +2824,7 @@ struct tg3 {
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@@ -2824,6 +2827,7 @@ struct tg3 {
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#define PHY_ID_BCM5714 0x60008340
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#define PHY_ID_BCM5714 0x60008340
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#define PHY_ID_BCM5780 0x60008350
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#define PHY_ID_BCM5780 0x60008350
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#define PHY_ID_BCM5755 0xbc050cc0
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#define PHY_ID_BCM5755 0xbc050cc0
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@ -299,7 +299,7 @@
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#define PHY_ID_BCM5787 0xbc050ce0
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#define PHY_ID_BCM5787 0xbc050ce0
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#define PHY_ID_BCM5756 0xbc050ed0
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#define PHY_ID_BCM5756 0xbc050ed0
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#define PHY_ID_BCM5784 0xbc050fa0
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#define PHY_ID_BCM5784 0xbc050fa0
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@@ -2865,7 +2869,7 @@ struct tg3 {
|
@@ -2868,7 +2872,7 @@ struct tg3 {
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(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
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(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
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(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
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(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
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(X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
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(X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
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|
@ -1,6 +1,6 @@
|
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--- a/drivers/net/b44.c
|
--- a/drivers/net/b44.c
|
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+++ b/drivers/net/b44.c
|
+++ b/drivers/net/b44.c
|
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@@ -815,7 +815,7 @@ static int b44_rx(struct b44 *bp, int bu
|
@@ -848,7 +848,7 @@ static int b44_rx(struct b44 *bp, int bu
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struct sk_buff *copy_skb;
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struct sk_buff *copy_skb;
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|
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b44_recycle_rx(bp, cons, bp->rx_prod);
|
b44_recycle_rx(bp, cons, bp->rx_prod);
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@ -31,7 +31,7 @@
|
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|
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--- a/arch/mips/mm/tlbex.c
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--- a/arch/mips/mm/tlbex.c
|
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+++ b/arch/mips/mm/tlbex.c
|
+++ b/arch/mips/mm/tlbex.c
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@@ -601,6 +601,9 @@ build_get_pgde32(u32 **p, unsigned int t
|
@@ -595,6 +595,9 @@ build_get_pgde32(u32 **p, unsigned int t
|
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#endif
|
#endif
|
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uasm_i_addu(p, ptr, tmp, ptr);
|
uasm_i_addu(p, ptr, tmp, ptr);
|
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#else
|
#else
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@ -41,7 +41,7 @@
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UASM_i_LA_mostly(p, ptr, pgdc);
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UASM_i_LA_mostly(p, ptr, pgdc);
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#endif
|
#endif
|
||||||
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
|
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
|
||||||
@@ -739,12 +742,12 @@ static void __cpuinit build_r4000_tlb_re
|
@@ -733,12 +736,12 @@ static void __cpuinit build_r4000_tlb_re
|
||||||
/* No need for uasm_i_nop */
|
/* No need for uasm_i_nop */
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -57,7 +57,7 @@
|
|||||||
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
|
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@@ -756,6 +759,9 @@ static void __cpuinit build_r4000_tlb_re
|
@@ -750,6 +753,9 @@ static void __cpuinit build_r4000_tlb_re
|
||||||
build_update_entries(&p, K0, K1);
|
build_update_entries(&p, K0, K1);
|
||||||
build_tlb_write_entry(&p, &l, &r, tlb_random);
|
build_tlb_write_entry(&p, &l, &r, tlb_random);
|
||||||
uasm_l_leave(&l, p);
|
uasm_l_leave(&l, p);
|
||||||
@ -67,7 +67,7 @@
|
|||||||
uasm_i_eret(&p); /* return from trap */
|
uasm_i_eret(&p); /* return from trap */
|
||||||
|
|
||||||
#ifdef CONFIG_HUGETLB_PAGE
|
#ifdef CONFIG_HUGETLB_PAGE
|
||||||
@@ -1196,12 +1202,12 @@ build_r4000_tlbchange_handler_head(u32 *
|
@@ -1188,12 +1194,12 @@ build_r4000_tlbchange_handler_head(u32 *
|
||||||
struct uasm_reloc **r, unsigned int pte,
|
struct uasm_reloc **r, unsigned int pte,
|
||||||
unsigned int ptr)
|
unsigned int ptr)
|
||||||
{
|
{
|
||||||
@ -83,7 +83,7 @@
|
|||||||
build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
|
build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@@ -1238,6 +1244,9 @@ build_r4000_tlbchange_handler_tail(u32 *
|
@@ -1230,6 +1236,9 @@ build_r4000_tlbchange_handler_tail(u32 *
|
||||||
build_update_entries(p, tmp, ptr);
|
build_update_entries(p, tmp, ptr);
|
||||||
build_tlb_write_entry(p, l, r, tlb_indexed);
|
build_tlb_write_entry(p, l, r, tlb_indexed);
|
||||||
uasm_l_leave(l, *p);
|
uasm_l_leave(l, *p);
|
||||||
|
@ -1,51 +0,0 @@
|
|||||||
--- a/drivers/ssb/driver_pcicore.c
|
|
||||||
+++ b/drivers/ssb/driver_pcicore.c
|
|
||||||
@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
|
|
||||||
.pci_ops = &ssb_pcicore_pciops,
|
|
||||||
.io_resource = &ssb_pcicore_io_resource,
|
|
||||||
.mem_resource = &ssb_pcicore_mem_resource,
|
|
||||||
- .mem_offset = 0x24000000,
|
|
||||||
};
|
|
||||||
|
|
||||||
-static u32 ssb_pcicore_pcibus_iobase = 0x100;
|
|
||||||
-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
|
|
||||||
-
|
|
||||||
/* This function is called when doing a pci_enable_device().
|
|
||||||
* We must first check if the device is a device on the PCI-core bridge. */
|
|
||||||
int ssb_pcicore_plat_dev_init(struct pci_dev *d)
|
|
||||||
{
|
|
||||||
- struct resource *res;
|
|
||||||
- int pos, size;
|
|
||||||
- u32 *base;
|
|
||||||
-
|
|
||||||
if (d->bus->ops != &ssb_pcicore_pciops) {
|
|
||||||
/* This is not a device on the PCI-core bridge. */
|
|
||||||
return -ENODEV;
|
|
||||||
@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
|
|
||||||
ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
|
|
||||||
pci_name(d));
|
|
||||||
|
|
||||||
- /* Fix up resource bases */
|
|
||||||
- for (pos = 0; pos < 6; pos++) {
|
|
||||||
- res = &d->resource[pos];
|
|
||||||
- if (res->flags & IORESOURCE_IO)
|
|
||||||
- base = &ssb_pcicore_pcibus_iobase;
|
|
||||||
- else
|
|
||||||
- base = &ssb_pcicore_pcibus_membase;
|
|
||||||
- res->flags |= IORESOURCE_PCI_FIXED;
|
|
||||||
- if (res->end) {
|
|
||||||
- size = res->end - res->start + 1;
|
|
||||||
- if (*base & (size - 1))
|
|
||||||
- *base = (*base + size) & ~(size - 1);
|
|
||||||
- res->start = *base;
|
|
||||||
- res->end = res->start + size - 1;
|
|
||||||
- *base += size;
|
|
||||||
- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
|
|
||||||
- }
|
|
||||||
- /* Fix up PCI bridge BAR0 only */
|
|
||||||
- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
|
|
||||||
- break;
|
|
||||||
- }
|
|
||||||
/* Fix up interrupt lines */
|
|
||||||
d->irq = ssb_mips_irq(extpci_core->dev) + 2;
|
|
||||||
pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
|
|
@ -60,7 +60,7 @@
|
|||||||
|
|
||||||
/* Enumeration space constants */
|
/* Enumeration space constants */
|
||||||
#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
|
#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
|
||||||
@@ -452,5 +454,41 @@ enum {
|
@@ -453,5 +455,41 @@ enum {
|
||||||
#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
|
#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
|
||||||
#define SSB_ADM_BASE2_SHIFT 16
|
#define SSB_ADM_BASE2_SHIFT 16
|
||||||
|
|
||||||
|
@ -1,36 +0,0 @@
|
|||||||
From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
|
|
||||||
From: Jochen Friedrich <jochen@scram.de>
|
|
||||||
Date: Wed, 3 Feb 2010 21:28:11 +0100
|
|
||||||
Subject: [PATCH 1/1] ssb: fix interrupt assignment
|
|
||||||
|
|
||||||
Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
|
|
||||||
anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
|
|
||||||
Also remove a bogus comment.
|
|
||||||
|
|
||||||
Signed-off-by: Jochen Friedrich <jochen@scram.de>
|
|
||||||
Signed-off-by: John W. Linville <linville@tuxdriver.com>
|
|
||||||
---
|
|
||||||
drivers/ssb/driver_mipscore.c | 5 ++++-
|
|
||||||
1 files changed, 4 insertions(+), 1 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/ssb/driver_mipscore.c
|
|
||||||
+++ b/drivers/ssb/driver_mipscore.c
|
|
||||||
@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
|
|
||||||
set_irq(dev, irq++);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
- /* fallthrough */
|
|
||||||
case SSB_DEV_PCI:
|
|
||||||
case SSB_DEV_ETHERNET:
|
|
||||||
case SSB_DEV_ETHERNET_GBIT:
|
|
||||||
@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
|
|
||||||
set_irq(dev, irq++);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
+ /* fallthrough */
|
|
||||||
+ case SSB_DEV_EXTIF:
|
|
||||||
+ set_irq(dev, 0);
|
|
||||||
+ break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
|
|
@ -1,6 +1,6 @@
|
|||||||
--- a/drivers/ssb/driver_chipcommon.c
|
--- a/drivers/ssb/driver_chipcommon.c
|
||||||
+++ b/drivers/ssb/driver_chipcommon.c
|
+++ b/drivers/ssb/driver_chipcommon.c
|
||||||
@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
|
@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
|
||||||
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
|
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
|
||||||
u32 *plltype, u32 *n, u32 *m)
|
u32 *plltype, u32 *n, u32 *m)
|
||||||
{
|
{
|
||||||
@ -9,7 +9,7 @@
|
|||||||
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
||||||
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
||||||
switch (*plltype) {
|
switch (*plltype) {
|
||||||
@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
|
@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
|
||||||
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
|
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
|
||||||
u32 *plltype, u32 *n, u32 *m)
|
u32 *plltype, u32 *n, u32 *m)
|
||||||
{
|
{
|
||||||
@ -31,7 +31,7 @@
|
|||||||
}
|
}
|
||||||
--- a/drivers/ssb/main.c
|
--- a/drivers/ssb/main.c
|
||||||
+++ b/drivers/ssb/main.c
|
+++ b/drivers/ssb/main.c
|
||||||
@@ -1069,6 +1069,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
|
@@ -1072,6 +1072,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
|
||||||
|
|
||||||
if (bus->chip_id == 0x5365) {
|
if (bus->chip_id == 0x5365) {
|
||||||
rate = 100000000;
|
rate = 100000000;
|
||||||
|
@ -1,51 +0,0 @@
|
|||||||
--- a/drivers/ssb/driver_pcicore.c
|
|
||||||
+++ b/drivers/ssb/driver_pcicore.c
|
|
||||||
@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
|
|
||||||
.pci_ops = &ssb_pcicore_pciops,
|
|
||||||
.io_resource = &ssb_pcicore_io_resource,
|
|
||||||
.mem_resource = &ssb_pcicore_mem_resource,
|
|
||||||
- .mem_offset = 0x24000000,
|
|
||||||
};
|
|
||||||
|
|
||||||
-static u32 ssb_pcicore_pcibus_iobase = 0x100;
|
|
||||||
-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
|
|
||||||
-
|
|
||||||
/* This function is called when doing a pci_enable_device().
|
|
||||||
* We must first check if the device is a device on the PCI-core bridge. */
|
|
||||||
int ssb_pcicore_plat_dev_init(struct pci_dev *d)
|
|
||||||
{
|
|
||||||
- struct resource *res;
|
|
||||||
- int pos, size;
|
|
||||||
- u32 *base;
|
|
||||||
-
|
|
||||||
if (d->bus->ops != &ssb_pcicore_pciops) {
|
|
||||||
/* This is not a device on the PCI-core bridge. */
|
|
||||||
return -ENODEV;
|
|
||||||
@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
|
|
||||||
ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
|
|
||||||
pci_name(d));
|
|
||||||
|
|
||||||
- /* Fix up resource bases */
|
|
||||||
- for (pos = 0; pos < 6; pos++) {
|
|
||||||
- res = &d->resource[pos];
|
|
||||||
- if (res->flags & IORESOURCE_IO)
|
|
||||||
- base = &ssb_pcicore_pcibus_iobase;
|
|
||||||
- else
|
|
||||||
- base = &ssb_pcicore_pcibus_membase;
|
|
||||||
- res->flags |= IORESOURCE_PCI_FIXED;
|
|
||||||
- if (res->end) {
|
|
||||||
- size = res->end - res->start + 1;
|
|
||||||
- if (*base & (size - 1))
|
|
||||||
- *base = (*base + size) & ~(size - 1);
|
|
||||||
- res->start = *base;
|
|
||||||
- res->end = res->start + size - 1;
|
|
||||||
- *base += size;
|
|
||||||
- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
|
|
||||||
- }
|
|
||||||
- /* Fix up PCI bridge BAR0 only */
|
|
||||||
- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
|
|
||||||
- break;
|
|
||||||
- }
|
|
||||||
/* Fix up interrupt lines */
|
|
||||||
d->irq = ssb_mips_irq(extpci_core->dev) + 2;
|
|
||||||
pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
|
|
@ -60,7 +60,7 @@
|
|||||||
|
|
||||||
/* Enumeration space constants */
|
/* Enumeration space constants */
|
||||||
#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
|
#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
|
||||||
@@ -452,5 +454,41 @@ enum {
|
@@ -453,5 +455,41 @@ enum {
|
||||||
#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
|
#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
|
||||||
#define SSB_ADM_BASE2_SHIFT 16
|
#define SSB_ADM_BASE2_SHIFT 16
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
--- a/drivers/ssb/driver_chipcommon.c
|
--- a/drivers/ssb/driver_chipcommon.c
|
||||||
+++ b/drivers/ssb/driver_chipcommon.c
|
+++ b/drivers/ssb/driver_chipcommon.c
|
||||||
@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
|
@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
|
||||||
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
|
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
|
||||||
u32 *plltype, u32 *n, u32 *m)
|
u32 *plltype, u32 *n, u32 *m)
|
||||||
{
|
{
|
||||||
@ -9,7 +9,7 @@
|
|||||||
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
||||||
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
||||||
switch (*plltype) {
|
switch (*plltype) {
|
||||||
@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
|
@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
|
||||||
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
|
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
|
||||||
u32 *plltype, u32 *n, u32 *m)
|
u32 *plltype, u32 *n, u32 *m)
|
||||||
{
|
{
|
||||||
@ -31,7 +31,7 @@
|
|||||||
}
|
}
|
||||||
--- a/drivers/ssb/main.c
|
--- a/drivers/ssb/main.c
|
||||||
+++ b/drivers/ssb/main.c
|
+++ b/drivers/ssb/main.c
|
||||||
@@ -1070,6 +1070,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
|
@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
|
||||||
|
|
||||||
if (bus->chip_id == 0x5365) {
|
if (bus->chip_id == 0x5365) {
|
||||||
rate = 100000000;
|
rate = 100000000;
|
||||||
|
@ -60,7 +60,7 @@
|
|||||||
|
|
||||||
/* Enumeration space constants */
|
/* Enumeration space constants */
|
||||||
#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
|
#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
|
||||||
@@ -452,5 +454,41 @@ enum {
|
@@ -453,5 +455,41 @@ enum {
|
||||||
#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
|
#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
|
||||||
#define SSB_ADM_BASE2_SHIFT 16
|
#define SSB_ADM_BASE2_SHIFT 16
|
||||||
|
|
||||||
|
File diff suppressed because it is too large
Load Diff
1231
target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch
Normal file
1231
target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch
Normal file
File diff suppressed because it is too large
Load Diff
644
target/linux/generic-2.6/patches-2.6.33/975-ssb_update.patch
Normal file
644
target/linux/generic-2.6/patches-2.6.33/975-ssb_update.patch
Normal file
@ -0,0 +1,644 @@
|
|||||||
|
--- a/drivers/ssb/driver_chipcommon.c
|
||||||
|
+++ b/drivers/ssb/driver_chipcommon.c
|
||||||
|
@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
|
||||||
|
{
|
||||||
|
if (!cc->dev)
|
||||||
|
return; /* We don't have a ChipCommon */
|
||||||
|
+ if (cc->dev->id.revision >= 11)
|
||||||
|
+ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
|
||||||
|
ssb_pmu_init(cc);
|
||||||
|
chipco_powercontrol_init(cc);
|
||||||
|
ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
|
||||||
|
@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
|
||||||
|
{
|
||||||
|
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
|
||||||
|
}
|
||||||
|
+EXPORT_SYMBOL(ssb_chipco_gpio_control);
|
||||||
|
|
||||||
|
u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
||||||
|
{
|
||||||
|
--- a/drivers/ssb/driver_chipcommon_pmu.c
|
||||||
|
+++ b/drivers/ssb/driver_chipcommon_pmu.c
|
||||||
|
@@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
|
||||||
|
case 0x5354:
|
||||||
|
ssb_pmu0_pllinit_r0(cc, crystalfreq);
|
||||||
|
break;
|
||||||
|
+ case 0x4322:
|
||||||
|
+ if (cc->pmu.rev == 2) {
|
||||||
|
+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
|
||||||
|
+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
|
||||||
|
+ }
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
ssb_printk(KERN_ERR PFX
|
||||||
|
"ERROR: PLL init unknown for device %04X\n",
|
||||||
|
@@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
|
||||||
|
|
||||||
|
switch (bus->chip_id) {
|
||||||
|
case 0x4312:
|
||||||
|
+ case 0x4322:
|
||||||
|
/* We keep the default settings:
|
||||||
|
* min_msk = 0xCBB
|
||||||
|
* max_msk = 0x7FFFF
|
||||||
|
--- a/drivers/ssb/driver_mipscore.c
|
||||||
|
+++ b/drivers/ssb/driver_mipscore.c
|
||||||
|
@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
|
||||||
|
set_irq(dev, irq++);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
- /* fallthrough */
|
||||||
|
case SSB_DEV_PCI:
|
||||||
|
case SSB_DEV_ETHERNET:
|
||||||
|
case SSB_DEV_ETHERNET_GBIT:
|
||||||
|
@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
|
||||||
|
set_irq(dev, irq++);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
+ /* fallthrough */
|
||||||
|
+ case SSB_DEV_EXTIF:
|
||||||
|
+ set_irq(dev, 0);
|
||||||
|
+ break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
|
||||||
|
--- a/drivers/ssb/driver_pcicore.c
|
||||||
|
+++ b/drivers/ssb/driver_pcicore.c
|
||||||
|
@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
|
||||||
|
.pci_ops = &ssb_pcicore_pciops,
|
||||||
|
.io_resource = &ssb_pcicore_io_resource,
|
||||||
|
.mem_resource = &ssb_pcicore_mem_resource,
|
||||||
|
- .mem_offset = 0x24000000,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static u32 ssb_pcicore_pcibus_iobase = 0x100;
|
||||||
|
-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
|
||||||
|
-
|
||||||
|
/* This function is called when doing a pci_enable_device().
|
||||||
|
* We must first check if the device is a device on the PCI-core bridge. */
|
||||||
|
int ssb_pcicore_plat_dev_init(struct pci_dev *d)
|
||||||
|
{
|
||||||
|
- struct resource *res;
|
||||||
|
- int pos, size;
|
||||||
|
- u32 *base;
|
||||||
|
-
|
||||||
|
if (d->bus->ops != &ssb_pcicore_pciops) {
|
||||||
|
/* This is not a device on the PCI-core bridge. */
|
||||||
|
return -ENODEV;
|
||||||
|
@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
|
||||||
|
ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
|
||||||
|
pci_name(d));
|
||||||
|
|
||||||
|
- /* Fix up resource bases */
|
||||||
|
- for (pos = 0; pos < 6; pos++) {
|
||||||
|
- res = &d->resource[pos];
|
||||||
|
- if (res->flags & IORESOURCE_IO)
|
||||||
|
- base = &ssb_pcicore_pcibus_iobase;
|
||||||
|
- else
|
||||||
|
- base = &ssb_pcicore_pcibus_membase;
|
||||||
|
- res->flags |= IORESOURCE_PCI_FIXED;
|
||||||
|
- if (res->end) {
|
||||||
|
- size = res->end - res->start + 1;
|
||||||
|
- if (*base & (size - 1))
|
||||||
|
- *base = (*base + size) & ~(size - 1);
|
||||||
|
- res->start = *base;
|
||||||
|
- res->end = res->start + size - 1;
|
||||||
|
- *base += size;
|
||||||
|
- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
|
||||||
|
- }
|
||||||
|
- /* Fix up PCI bridge BAR0 only */
|
||||||
|
- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
|
||||||
|
- break;
|
||||||
|
- }
|
||||||
|
/* Fix up interrupt lines */
|
||||||
|
d->irq = ssb_mips_irq(extpci_core->dev) + 2;
|
||||||
|
pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
|
||||||
|
--- a/drivers/ssb/main.c
|
||||||
|
+++ b/drivers/ssb/main.c
|
||||||
|
@@ -833,6 +833,9 @@ int ssb_bus_pcibus_register(struct ssb_b
|
||||||
|
if (!err) {
|
||||||
|
ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
|
||||||
|
"PCI device %s\n", dev_name(&host_pci->dev));
|
||||||
|
+ } else {
|
||||||
|
+ ssb_printk(KERN_ERR PFX "Failed to register PCI version"
|
||||||
|
+ " of SSB with error %d\n", err);
|
||||||
|
}
|
||||||
|
|
||||||
|
return err;
|
||||||
|
--- a/drivers/ssb/pci.c
|
||||||
|
+++ b/drivers/ssb/pci.c
|
||||||
|
@@ -167,7 +167,7 @@ err_pci:
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get the word-offset for a SSB_SPROM_XXX define. */
|
||||||
|
-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
|
||||||
|
+#define SPOFF(offset) ((offset) / sizeof(u16))
|
||||||
|
/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
|
||||||
|
#define SPEX16(_outvar, _offset, _mask, _shift) \
|
||||||
|
out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
|
||||||
|
@@ -253,7 +253,7 @@ static int sprom_do_read(struct ssb_bus
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < bus->sprom_size; i++)
|
||||||
|
- sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
|
||||||
|
+ sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
@@ -284,7 +284,7 @@ static int sprom_do_write(struct ssb_bus
|
||||||
|
ssb_printk("75%%");
|
||||||
|
else if (i % 2)
|
||||||
|
ssb_printk(".");
|
||||||
|
- writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
|
||||||
|
+ writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
|
||||||
|
mmiowb();
|
||||||
|
msleep(20);
|
||||||
|
}
|
||||||
|
@@ -620,6 +620,14 @@ static int ssb_pci_sprom_get(struct ssb_
|
||||||
|
int err = -ENOMEM;
|
||||||
|
u16 *buf;
|
||||||
|
|
||||||
|
+ if (!ssb_is_sprom_available(bus)) {
|
||||||
|
+ ssb_printk(KERN_ERR PFX "No SPROM available!\n");
|
||||||
|
+ return -ENODEV;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
|
||||||
|
+ SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
|
||||||
|
+
|
||||||
|
buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
|
||||||
|
if (!buf)
|
||||||
|
goto out;
|
||||||
|
--- a/drivers/ssb/sprom.c
|
||||||
|
+++ b/drivers/ssb/sprom.c
|
||||||
|
@@ -175,3 +175,17 @@ const struct ssb_sprom *ssb_get_fallback
|
||||||
|
{
|
||||||
|
return fallback_sprom;
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
|
||||||
|
+bool ssb_is_sprom_available(struct ssb_bus *bus)
|
||||||
|
+{
|
||||||
|
+ /* status register only exists on chipcomon rev >= 11 and we need check
|
||||||
|
+ for >= 31 only */
|
||||||
|
+ /* this routine differs from specs as we do not access SPROM directly
|
||||||
|
+ on PCMCIA */
|
||||||
|
+ if (bus->bustype == SSB_BUSTYPE_PCI &&
|
||||||
|
+ bus->chipco.dev->id.revision >= 31)
|
||||||
|
+ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
|
||||||
|
+
|
||||||
|
+ return true;
|
||||||
|
+}
|
||||||
|
--- a/drivers/ssb/ssb_private.h
|
||||||
|
+++ b/drivers/ssb/ssb_private.h
|
||||||
|
@@ -196,7 +196,7 @@ extern int ssb_devices_thaw(struct ssb_f
|
||||||
|
#ifdef CONFIG_SSB_B43_PCI_BRIDGE
|
||||||
|
extern int __init b43_pci_ssb_bridge_init(void);
|
||||||
|
extern void __exit b43_pci_ssb_bridge_exit(void);
|
||||||
|
-#else /* CONFIG_SSB_B43_PCI_BRIDGR */
|
||||||
|
+#else /* CONFIG_SSB_B43_PCI_BRIDGE */
|
||||||
|
static inline int b43_pci_ssb_bridge_init(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
@@ -204,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
|
||||||
|
static inline void b43_pci_ssb_bridge_exit(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
-#endif /* CONFIG_SSB_PCIHOST */
|
||||||
|
+#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
|
||||||
|
|
||||||
|
#endif /* LINUX_SSB_PRIVATE_H_ */
|
||||||
|
--- a/include/linux/ssb/ssb.h
|
||||||
|
+++ b/include/linux/ssb/ssb.h
|
||||||
|
@@ -305,6 +305,7 @@ struct ssb_bus {
|
||||||
|
/* ID information about the Chip. */
|
||||||
|
u16 chip_id;
|
||||||
|
u16 chip_rev;
|
||||||
|
+ u16 sprom_offset;
|
||||||
|
u16 sprom_size; /* number of words in sprom */
|
||||||
|
u8 chip_package;
|
||||||
|
|
||||||
|
@@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
|
||||||
|
|
||||||
|
extern void ssb_bus_unregister(struct ssb_bus *bus);
|
||||||
|
|
||||||
|
+/* Does the device have an SPROM? */
|
||||||
|
+extern bool ssb_is_sprom_available(struct ssb_bus *bus);
|
||||||
|
+
|
||||||
|
/* Set a fallback SPROM.
|
||||||
|
* See kdoc at the function definition for complete documentation. */
|
||||||
|
extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
|
||||||
|
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
||||||
|
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
||||||
|
@@ -53,6 +53,7 @@
|
||||||
|
#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
|
||||||
|
#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
|
||||||
|
#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
|
||||||
|
+#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
|
||||||
|
#define SSB_CHIPCO_CORECTL 0x0008
|
||||||
|
#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
|
||||||
|
#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
|
||||||
|
@@ -385,6 +386,7 @@
|
||||||
|
|
||||||
|
|
||||||
|
/** Chip specific Chip-Status register contents. */
|
||||||
|
+#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
|
||||||
|
#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
|
||||||
|
#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
|
||||||
|
#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
|
||||||
|
@@ -398,6 +400,18 @@
|
||||||
|
#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
|
||||||
|
#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
|
||||||
|
|
||||||
|
+/** Macros to determine SPROM presence based on Chip-Status register. */
|
||||||
|
+#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
|
||||||
|
+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
|
||||||
|
+ SSB_CHIPCO_CHST_4325_OTP_SEL)
|
||||||
|
+#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
|
||||||
|
+ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
|
||||||
|
+#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
|
||||||
|
+ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
|
||||||
|
+ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
|
||||||
|
+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
|
||||||
|
+ SSB_CHIPCO_CHST_4325_OTP_SEL))
|
||||||
|
+
|
||||||
|
|
||||||
|
|
||||||
|
/** Clockcontrol masks and values **/
|
||||||
|
@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
|
||||||
|
struct ssb_chipcommon {
|
||||||
|
struct ssb_device *dev;
|
||||||
|
u32 capabilities;
|
||||||
|
+ u32 status;
|
||||||
|
/* Fast Powerup Delay constant */
|
||||||
|
u16 fast_pwrup_delay;
|
||||||
|
struct ssb_chipcommon_pmu pmu;
|
||||||
|
--- a/include/linux/ssb/ssb_regs.h
|
||||||
|
+++ b/include/linux/ssb/ssb_regs.h
|
||||||
|
@@ -170,26 +170,27 @@
|
||||||
|
#define SSB_SPROMSIZE_WORDS_R4 220
|
||||||
|
#define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
|
||||||
|
#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
|
||||||
|
-#define SSB_SPROM_BASE 0x1000
|
||||||
|
-#define SSB_SPROM_REVISION 0x107E
|
||||||
|
+#define SSB_SPROM_BASE1 0x1000
|
||||||
|
+#define SSB_SPROM_BASE31 0x0800
|
||||||
|
+#define SSB_SPROM_REVISION 0x007E
|
||||||
|
#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
|
||||||
|
#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
|
||||||
|
#define SSB_SPROM_REVISION_CRC_SHIFT 8
|
||||||
|
|
||||||
|
/* SPROM Revision 1 */
|
||||||
|
-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
|
||||||
|
-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
|
||||||
|
-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
|
||||||
|
-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
|
||||||
|
-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
|
||||||
|
-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
|
||||||
|
-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
|
||||||
|
+#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
|
||||||
|
+#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
|
||||||
|
+#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
|
||||||
|
+#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
|
||||||
|
+#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
|
||||||
|
+#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
|
||||||
|
+#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
|
||||||
|
-#define SSB_SPROM1_BINF 0x105C /* Board info */
|
||||||
|
+#define SSB_SPROM1_BINF 0x005C /* Board info */
|
||||||
|
#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
|
||||||
|
#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
|
||||||
|
#define SSB_SPROM1_BINF_CCODE_SHIFT 8
|
||||||
|
@@ -197,63 +198,63 @@
|
||||||
|
#define SSB_SPROM1_BINF_ANTBG_SHIFT 12
|
||||||
|
#define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
|
||||||
|
#define SSB_SPROM1_BINF_ANTA_SHIFT 14
|
||||||
|
-#define SSB_SPROM1_PA0B0 0x105E
|
||||||
|
-#define SSB_SPROM1_PA0B1 0x1060
|
||||||
|
-#define SSB_SPROM1_PA0B2 0x1062
|
||||||
|
-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
|
||||||
|
+#define SSB_SPROM1_PA0B0 0x005E
|
||||||
|
+#define SSB_SPROM1_PA0B1 0x0060
|
||||||
|
+#define SSB_SPROM1_PA0B2 0x0062
|
||||||
|
+#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
|
||||||
|
#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
#define SSB_SPROM1_GPIOA_P1_SHIFT 8
|
||||||
|
-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
|
||||||
|
+#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
|
||||||
|
#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
#define SSB_SPROM1_GPIOB_P3_SHIFT 8
|
||||||
|
-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
|
||||||
|
+#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
|
||||||
|
#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM1_MAXPWR_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM1_PA1B0 0x106A
|
||||||
|
-#define SSB_SPROM1_PA1B1 0x106C
|
||||||
|
-#define SSB_SPROM1_PA1B2 0x106E
|
||||||
|
-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
|
||||||
|
+#define SSB_SPROM1_PA1B0 0x006A
|
||||||
|
+#define SSB_SPROM1_PA1B1 0x006C
|
||||||
|
+#define SSB_SPROM1_PA1B2 0x006E
|
||||||
|
+#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
|
||||||
|
#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
|
||||||
|
#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
|
||||||
|
#define SSB_SPROM1_ITSSI_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
|
||||||
|
-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
+#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
|
||||||
|
+#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
|
||||||
|
#define SSB_SPROM1_AGAIN_BG_SHIFT 0
|
||||||
|
#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
|
||||||
|
#define SSB_SPROM1_AGAIN_A_SHIFT 8
|
||||||
|
|
||||||
|
/* SPROM Revision 2 (inherits from rev 1) */
|
||||||
|
-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
|
||||||
|
-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
|
||||||
|
+#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
|
||||||
|
+#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
|
||||||
|
#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
|
||||||
|
#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
|
||||||
|
#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
|
||||||
|
-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
|
||||||
|
+#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
+#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
+#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
+#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
+#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
+#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
+#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
|
||||||
|
#define SSB_SPROM2_OPO_VALUE 0x00FF
|
||||||
|
#define SSB_SPROM2_OPO_UNUSED 0xFF00
|
||||||
|
-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
|
||||||
|
+#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
|
||||||
|
|
||||||
|
/* SPROM Revision 3 (inherits most data from rev 2) */
|
||||||
|
-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
|
||||||
|
-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
|
||||||
|
-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
|
||||||
|
-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
|
||||||
|
-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
|
||||||
|
+#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
|
||||||
|
+#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
|
||||||
|
+#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
|
||||||
|
+#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
|
||||||
|
#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
|
||||||
|
#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
|
||||||
|
#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
|
||||||
|
#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
|
||||||
|
-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
|
||||||
|
+#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
|
||||||
|
+#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
|
||||||
|
#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
|
||||||
|
#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
|
||||||
|
#define SSB_SPROM3_CCKPO_2M_SHIFT 4
|
||||||
|
@@ -264,100 +265,100 @@
|
||||||
|
#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
|
||||||
|
|
||||||
|
/* SPROM Revision 4 */
|
||||||
|
-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
|
||||||
|
-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
|
||||||
|
+#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
|
||||||
|
+#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
|
||||||
|
+#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
|
||||||
|
+#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
|
||||||
|
+#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
|
||||||
|
+#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
+#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
+#define SSB_SPROM4_GPIOA_P1_SHIFT 8
|
||||||
|
+#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
+#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
+#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
+#define SSB_SPROM4_GPIOB_P3_SHIFT 8
|
||||||
|
+#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
|
||||||
|
-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
|
||||||
|
-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
|
||||||
|
+#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
|
||||||
|
#define SSB_SPROM4_AGAIN0_SHIFT 0
|
||||||
|
#define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
|
||||||
|
#define SSB_SPROM4_AGAIN1_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_AGAIN23 0x1060
|
||||||
|
+#define SSB_SPROM4_AGAIN23 0x0060
|
||||||
|
#define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
|
||||||
|
#define SSB_SPROM4_AGAIN2_SHIFT 0
|
||||||
|
#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
|
||||||
|
#define SSB_SPROM4_AGAIN3_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
|
||||||
|
-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
|
||||||
|
+#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
|
||||||
|
#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
|
||||||
|
#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
|
||||||
|
#define SSB_SPROM4_ITSSI_BG_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
|
||||||
|
+#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
|
||||||
|
#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
|
||||||
|
#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
|
||||||
|
#define SSB_SPROM4_ITSSI_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
|
||||||
|
-#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
-#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
-#define SSB_SPROM4_GPIOA_P1_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
-#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
-#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
-#define SSB_SPROM4_GPIOB_P3_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
|
||||||
|
-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
|
||||||
|
-#define SSB_SPROM4_PA0B2 0x1086
|
||||||
|
-#define SSB_SPROM4_PA1B0 0x108E
|
||||||
|
-#define SSB_SPROM4_PA1B1 0x1090
|
||||||
|
-#define SSB_SPROM4_PA1B2 0x1092
|
||||||
|
+#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
|
||||||
|
+#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
|
||||||
|
+#define SSB_SPROM4_PA0B2 0x0086
|
||||||
|
+#define SSB_SPROM4_PA1B0 0x008E
|
||||||
|
+#define SSB_SPROM4_PA1B1 0x0090
|
||||||
|
+#define SSB_SPROM4_PA1B2 0x0092
|
||||||
|
|
||||||
|
/* SPROM Revision 5 (inherits most data from rev 4) */
|
||||||
|
-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
|
||||||
|
-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
|
||||||
|
-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
|
||||||
|
-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
|
||||||
|
-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
|
||||||
|
+#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
|
||||||
|
+#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
|
||||||
|
+#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
|
||||||
|
+#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
|
||||||
|
+#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
|
||||||
|
#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
#define SSB_SPROM5_GPIOA_P1_SHIFT 8
|
||||||
|
-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
+#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
#define SSB_SPROM5_GPIOB_P3_SHIFT 8
|
||||||
|
|
||||||
|
/* SPROM Revision 8 */
|
||||||
|
-#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
|
||||||
|
-#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
|
||||||
|
-#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
|
||||||
|
-#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
|
||||||
|
-#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
|
||||||
|
-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
|
||||||
|
-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
|
||||||
|
-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
+#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
|
||||||
|
+#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
|
||||||
|
+#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
|
||||||
|
+#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
|
||||||
|
+#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
|
||||||
|
+#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
|
||||||
|
+#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
|
||||||
|
+#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
|
||||||
|
+#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
+#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
+#define SSB_SPROM8_GPIOA_P1_SHIFT 8
|
||||||
|
+#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
+#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
+#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
+#define SSB_SPROM8_GPIOB_P3_SHIFT 8
|
||||||
|
+#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
|
||||||
|
+#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
|
||||||
|
+#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
|
||||||
|
+#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
|
||||||
|
+#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
|
||||||
|
+#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
|
||||||
|
#define SSB_SPROM8_AGAIN0_SHIFT 0
|
||||||
|
#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
|
||||||
|
#define SSB_SPROM8_AGAIN1_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_AGAIN23 0x10A0
|
||||||
|
+#define SSB_SPROM8_AGAIN23 0x00A0
|
||||||
|
#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
|
||||||
|
#define SSB_SPROM8_AGAIN2_SHIFT 0
|
||||||
|
#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
|
||||||
|
#define SSB_SPROM8_AGAIN3_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
|
||||||
|
-#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
-#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
-#define SSB_SPROM8_GPIOA_P1_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
-#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
-#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
-#define SSB_SPROM8_GPIOB_P3_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
|
||||||
|
+#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
|
||||||
|
#define SSB_SPROM8_RSSISMF2G 0x000F
|
||||||
|
#define SSB_SPROM8_RSSISMC2G 0x00F0
|
||||||
|
#define SSB_SPROM8_RSSISMC2G_SHIFT 4
|
||||||
|
@@ -365,7 +366,7 @@
|
||||||
|
#define SSB_SPROM8_RSSISAV2G_SHIFT 8
|
||||||
|
#define SSB_SPROM8_BXA2G 0x1800
|
||||||
|
#define SSB_SPROM8_BXA2G_SHIFT 11
|
||||||
|
-#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
|
||||||
|
+#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
|
||||||
|
#define SSB_SPROM8_RSSISMF5G 0x000F
|
||||||
|
#define SSB_SPROM8_RSSISMC5G 0x00F0
|
||||||
|
#define SSB_SPROM8_RSSISMC5G_SHIFT 4
|
||||||
|
@@ -373,47 +374,47 @@
|
||||||
|
#define SSB_SPROM8_RSSISAV5G_SHIFT 8
|
||||||
|
#define SSB_SPROM8_BXA5G 0x1800
|
||||||
|
#define SSB_SPROM8_BXA5G_SHIFT 11
|
||||||
|
-#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
|
||||||
|
+#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
|
||||||
|
#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
|
||||||
|
#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
|
||||||
|
#define SSB_SPROM8_TRI5G_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
|
||||||
|
+#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
|
||||||
|
#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
|
||||||
|
#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
|
||||||
|
#define SSB_SPROM8_TRI5GH_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
|
||||||
|
+#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
|
||||||
|
#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
|
||||||
|
#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
|
||||||
|
#define SSB_SPROM8_RXPO5G_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
|
||||||
|
+#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
|
||||||
|
#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
|
||||||
|
#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
|
||||||
|
#define SSB_SPROM8_ITSSI_BG_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
|
||||||
|
-#define SSB_SPROM8_PA0B1 0x10C4
|
||||||
|
-#define SSB_SPROM8_PA0B2 0x10C6
|
||||||
|
-#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
|
||||||
|
+#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
|
||||||
|
+#define SSB_SPROM8_PA0B1 0x00C4
|
||||||
|
+#define SSB_SPROM8_PA0B2 0x00C6
|
||||||
|
+#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
|
||||||
|
#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
|
||||||
|
#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
|
||||||
|
#define SSB_SPROM8_ITSSI_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
|
||||||
|
+#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
|
||||||
|
#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
|
||||||
|
#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
|
||||||
|
#define SSB_SPROM8_MAXP_AL_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
|
||||||
|
-#define SSB_SPROM8_PA1B1 0x10CE
|
||||||
|
-#define SSB_SPROM8_PA1B2 0x10D0
|
||||||
|
-#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
|
||||||
|
-#define SSB_SPROM8_PA1LOB1 0x10D4
|
||||||
|
-#define SSB_SPROM8_PA1LOB2 0x10D6
|
||||||
|
-#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
|
||||||
|
-#define SSB_SPROM8_PA1HIB1 0x10DA
|
||||||
|
-#define SSB_SPROM8_PA1HIB2 0x10DC
|
||||||
|
-#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
|
||||||
|
-#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
|
||||||
|
-#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
|
||||||
|
-#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
|
||||||
|
-#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
|
||||||
|
+#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
|
||||||
|
+#define SSB_SPROM8_PA1B1 0x00CE
|
||||||
|
+#define SSB_SPROM8_PA1B2 0x00D0
|
||||||
|
+#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
|
||||||
|
+#define SSB_SPROM8_PA1LOB1 0x00D4
|
||||||
|
+#define SSB_SPROM8_PA1LOB2 0x00D6
|
||||||
|
+#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
|
||||||
|
+#define SSB_SPROM8_PA1HIB1 0x00DA
|
||||||
|
+#define SSB_SPROM8_PA1HIB2 0x00DC
|
||||||
|
+#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
|
||||||
|
+#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
|
||||||
|
+#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
|
||||||
|
+#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
|
||||||
|
+#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
|
||||||
|
|
||||||
|
/* Values for SSB_SPROM1_BINF_CCODE */
|
||||||
|
enum {
|
530
target/linux/generic-2.6/patches-2.6.34/975-ssb_update.patch
Normal file
530
target/linux/generic-2.6/patches-2.6.34/975-ssb_update.patch
Normal file
@ -0,0 +1,530 @@
|
|||||||
|
--- a/drivers/ssb/driver_chipcommon.c
|
||||||
|
+++ b/drivers/ssb/driver_chipcommon.c
|
||||||
|
@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
|
||||||
|
{
|
||||||
|
if (!cc->dev)
|
||||||
|
return; /* We don't have a ChipCommon */
|
||||||
|
+ if (cc->dev->id.revision >= 11)
|
||||||
|
+ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
|
||||||
|
ssb_pmu_init(cc);
|
||||||
|
chipco_powercontrol_init(cc);
|
||||||
|
ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
|
||||||
|
@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
|
||||||
|
{
|
||||||
|
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
|
||||||
|
}
|
||||||
|
+EXPORT_SYMBOL(ssb_chipco_gpio_control);
|
||||||
|
|
||||||
|
u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
||||||
|
{
|
||||||
|
--- a/drivers/ssb/main.c
|
||||||
|
+++ b/drivers/ssb/main.c
|
||||||
|
@@ -834,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
|
||||||
|
if (!err) {
|
||||||
|
ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
|
||||||
|
"PCI device %s\n", dev_name(&host_pci->dev));
|
||||||
|
+ } else {
|
||||||
|
+ ssb_printk(KERN_ERR PFX "Failed to register PCI version"
|
||||||
|
+ " of SSB with error %d\n", err);
|
||||||
|
}
|
||||||
|
|
||||||
|
return err;
|
||||||
|
--- a/drivers/ssb/pci.c
|
||||||
|
+++ b/drivers/ssb/pci.c
|
||||||
|
@@ -168,7 +168,7 @@ err_pci:
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get the word-offset for a SSB_SPROM_XXX define. */
|
||||||
|
-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
|
||||||
|
+#define SPOFF(offset) ((offset) / sizeof(u16))
|
||||||
|
/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
|
||||||
|
#define SPEX16(_outvar, _offset, _mask, _shift) \
|
||||||
|
out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
|
||||||
|
@@ -254,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < bus->sprom_size; i++)
|
||||||
|
- sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
|
||||||
|
+ sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
@@ -285,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
|
||||||
|
ssb_printk("75%%");
|
||||||
|
else if (i % 2)
|
||||||
|
ssb_printk(".");
|
||||||
|
- writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
|
||||||
|
+ writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
|
||||||
|
mmiowb();
|
||||||
|
msleep(20);
|
||||||
|
}
|
||||||
|
@@ -621,6 +621,14 @@ static int ssb_pci_sprom_get(struct ssb_
|
||||||
|
int err = -ENOMEM;
|
||||||
|
u16 *buf;
|
||||||
|
|
||||||
|
+ if (!ssb_is_sprom_available(bus)) {
|
||||||
|
+ ssb_printk(KERN_ERR PFX "No SPROM available!\n");
|
||||||
|
+ return -ENODEV;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
|
||||||
|
+ SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
|
||||||
|
+
|
||||||
|
buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
|
||||||
|
if (!buf)
|
||||||
|
goto out;
|
||||||
|
--- a/drivers/ssb/sprom.c
|
||||||
|
+++ b/drivers/ssb/sprom.c
|
||||||
|
@@ -176,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
|
||||||
|
{
|
||||||
|
return fallback_sprom;
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
|
||||||
|
+bool ssb_is_sprom_available(struct ssb_bus *bus)
|
||||||
|
+{
|
||||||
|
+ /* status register only exists on chipcomon rev >= 11 and we need check
|
||||||
|
+ for >= 31 only */
|
||||||
|
+ /* this routine differs from specs as we do not access SPROM directly
|
||||||
|
+ on PCMCIA */
|
||||||
|
+ if (bus->bustype == SSB_BUSTYPE_PCI &&
|
||||||
|
+ bus->chipco.dev->id.revision >= 31)
|
||||||
|
+ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
|
||||||
|
+
|
||||||
|
+ return true;
|
||||||
|
+}
|
||||||
|
--- a/include/linux/ssb/ssb.h
|
||||||
|
+++ b/include/linux/ssb/ssb.h
|
||||||
|
@@ -305,6 +305,7 @@ struct ssb_bus {
|
||||||
|
/* ID information about the Chip. */
|
||||||
|
u16 chip_id;
|
||||||
|
u16 chip_rev;
|
||||||
|
+ u16 sprom_offset;
|
||||||
|
u16 sprom_size; /* number of words in sprom */
|
||||||
|
u8 chip_package;
|
||||||
|
|
||||||
|
@@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
|
||||||
|
|
||||||
|
extern void ssb_bus_unregister(struct ssb_bus *bus);
|
||||||
|
|
||||||
|
+/* Does the device have an SPROM? */
|
||||||
|
+extern bool ssb_is_sprom_available(struct ssb_bus *bus);
|
||||||
|
+
|
||||||
|
/* Set a fallback SPROM.
|
||||||
|
* See kdoc at the function definition for complete documentation. */
|
||||||
|
extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
|
||||||
|
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
||||||
|
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
||||||
|
@@ -53,6 +53,7 @@
|
||||||
|
#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
|
||||||
|
#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
|
||||||
|
#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
|
||||||
|
+#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
|
||||||
|
#define SSB_CHIPCO_CORECTL 0x0008
|
||||||
|
#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
|
||||||
|
#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
|
||||||
|
@@ -385,6 +386,7 @@
|
||||||
|
|
||||||
|
|
||||||
|
/** Chip specific Chip-Status register contents. */
|
||||||
|
+#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
|
||||||
|
#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
|
||||||
|
#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
|
||||||
|
#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
|
||||||
|
@@ -398,6 +400,18 @@
|
||||||
|
#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
|
||||||
|
#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
|
||||||
|
|
||||||
|
+/** Macros to determine SPROM presence based on Chip-Status register. */
|
||||||
|
+#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
|
||||||
|
+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
|
||||||
|
+ SSB_CHIPCO_CHST_4325_OTP_SEL)
|
||||||
|
+#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
|
||||||
|
+ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
|
||||||
|
+#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
|
||||||
|
+ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
|
||||||
|
+ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
|
||||||
|
+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
|
||||||
|
+ SSB_CHIPCO_CHST_4325_OTP_SEL))
|
||||||
|
+
|
||||||
|
|
||||||
|
|
||||||
|
/** Clockcontrol masks and values **/
|
||||||
|
@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
|
||||||
|
struct ssb_chipcommon {
|
||||||
|
struct ssb_device *dev;
|
||||||
|
u32 capabilities;
|
||||||
|
+ u32 status;
|
||||||
|
/* Fast Powerup Delay constant */
|
||||||
|
u16 fast_pwrup_delay;
|
||||||
|
struct ssb_chipcommon_pmu pmu;
|
||||||
|
--- a/include/linux/ssb/ssb_regs.h
|
||||||
|
+++ b/include/linux/ssb/ssb_regs.h
|
||||||
|
@@ -170,26 +170,27 @@
|
||||||
|
#define SSB_SPROMSIZE_WORDS_R4 220
|
||||||
|
#define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
|
||||||
|
#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
|
||||||
|
-#define SSB_SPROM_BASE 0x1000
|
||||||
|
-#define SSB_SPROM_REVISION 0x107E
|
||||||
|
+#define SSB_SPROM_BASE1 0x1000
|
||||||
|
+#define SSB_SPROM_BASE31 0x0800
|
||||||
|
+#define SSB_SPROM_REVISION 0x007E
|
||||||
|
#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
|
||||||
|
#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
|
||||||
|
#define SSB_SPROM_REVISION_CRC_SHIFT 8
|
||||||
|
|
||||||
|
/* SPROM Revision 1 */
|
||||||
|
-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
|
||||||
|
-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
|
||||||
|
-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
|
||||||
|
-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
|
||||||
|
-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
|
||||||
|
-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
|
||||||
|
-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
|
||||||
|
+#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
|
||||||
|
+#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
|
||||||
|
+#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
|
||||||
|
+#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
|
||||||
|
+#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
|
||||||
|
+#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
|
||||||
|
+#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
|
||||||
|
#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
|
||||||
|
-#define SSB_SPROM1_BINF 0x105C /* Board info */
|
||||||
|
+#define SSB_SPROM1_BINF 0x005C /* Board info */
|
||||||
|
#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
|
||||||
|
#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
|
||||||
|
#define SSB_SPROM1_BINF_CCODE_SHIFT 8
|
||||||
|
@@ -197,63 +198,63 @@
|
||||||
|
#define SSB_SPROM1_BINF_ANTBG_SHIFT 12
|
||||||
|
#define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
|
||||||
|
#define SSB_SPROM1_BINF_ANTA_SHIFT 14
|
||||||
|
-#define SSB_SPROM1_PA0B0 0x105E
|
||||||
|
-#define SSB_SPROM1_PA0B1 0x1060
|
||||||
|
-#define SSB_SPROM1_PA0B2 0x1062
|
||||||
|
-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
|
||||||
|
+#define SSB_SPROM1_PA0B0 0x005E
|
||||||
|
+#define SSB_SPROM1_PA0B1 0x0060
|
||||||
|
+#define SSB_SPROM1_PA0B2 0x0062
|
||||||
|
+#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
|
||||||
|
#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
#define SSB_SPROM1_GPIOA_P1_SHIFT 8
|
||||||
|
-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
|
||||||
|
+#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
|
||||||
|
#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
#define SSB_SPROM1_GPIOB_P3_SHIFT 8
|
||||||
|
-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
|
||||||
|
+#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
|
||||||
|
#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM1_MAXPWR_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM1_PA1B0 0x106A
|
||||||
|
-#define SSB_SPROM1_PA1B1 0x106C
|
||||||
|
-#define SSB_SPROM1_PA1B2 0x106E
|
||||||
|
-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
|
||||||
|
+#define SSB_SPROM1_PA1B0 0x006A
|
||||||
|
+#define SSB_SPROM1_PA1B1 0x006C
|
||||||
|
+#define SSB_SPROM1_PA1B2 0x006E
|
||||||
|
+#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
|
||||||
|
#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
|
||||||
|
#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
|
||||||
|
#define SSB_SPROM1_ITSSI_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
|
||||||
|
-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
+#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
|
||||||
|
+#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
|
||||||
|
#define SSB_SPROM1_AGAIN_BG_SHIFT 0
|
||||||
|
#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
|
||||||
|
#define SSB_SPROM1_AGAIN_A_SHIFT 8
|
||||||
|
|
||||||
|
/* SPROM Revision 2 (inherits from rev 1) */
|
||||||
|
-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
|
||||||
|
-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
|
||||||
|
+#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
|
||||||
|
+#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
|
||||||
|
#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
|
||||||
|
#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
|
||||||
|
#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
|
||||||
|
-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
|
||||||
|
+#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
+#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
+#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
|
||||||
|
+#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
+#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
+#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
|
||||||
|
+#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
|
||||||
|
#define SSB_SPROM2_OPO_VALUE 0x00FF
|
||||||
|
#define SSB_SPROM2_OPO_UNUSED 0xFF00
|
||||||
|
-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
|
||||||
|
+#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
|
||||||
|
|
||||||
|
/* SPROM Revision 3 (inherits most data from rev 2) */
|
||||||
|
-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
|
||||||
|
-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
|
||||||
|
-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
|
||||||
|
-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
|
||||||
|
-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
|
||||||
|
+#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
|
||||||
|
+#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
|
||||||
|
+#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
|
||||||
|
+#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
|
||||||
|
#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
|
||||||
|
#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
|
||||||
|
#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
|
||||||
|
#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
|
||||||
|
-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
|
||||||
|
+#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
|
||||||
|
+#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
|
||||||
|
#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
|
||||||
|
#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
|
||||||
|
#define SSB_SPROM3_CCKPO_2M_SHIFT 4
|
||||||
|
@@ -264,100 +265,100 @@
|
||||||
|
#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
|
||||||
|
|
||||||
|
/* SPROM Revision 4 */
|
||||||
|
-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
|
||||||
|
-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
|
||||||
|
+#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
|
||||||
|
+#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
|
||||||
|
+#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
|
||||||
|
+#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
|
||||||
|
+#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
|
||||||
|
+#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
+#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
+#define SSB_SPROM4_GPIOA_P1_SHIFT 8
|
||||||
|
+#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
+#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
+#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
+#define SSB_SPROM4_GPIOB_P3_SHIFT 8
|
||||||
|
+#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
|
||||||
|
#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
|
||||||
|
-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
|
||||||
|
-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
|
||||||
|
-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
|
||||||
|
+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
|
||||||
|
+#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
|
||||||
|
#define SSB_SPROM4_AGAIN0_SHIFT 0
|
||||||
|
#define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
|
||||||
|
#define SSB_SPROM4_AGAIN1_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_AGAIN23 0x1060
|
||||||
|
+#define SSB_SPROM4_AGAIN23 0x0060
|
||||||
|
#define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
|
||||||
|
#define SSB_SPROM4_AGAIN2_SHIFT 0
|
||||||
|
#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
|
||||||
|
#define SSB_SPROM4_AGAIN3_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
|
||||||
|
-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
|
||||||
|
+#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
|
||||||
|
#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
|
||||||
|
#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
|
||||||
|
#define SSB_SPROM4_ITSSI_BG_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
|
||||||
|
+#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
|
||||||
|
#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
|
||||||
|
#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
|
||||||
|
#define SSB_SPROM4_ITSSI_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
|
||||||
|
-#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
-#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
-#define SSB_SPROM4_GPIOA_P1_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
-#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
-#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
-#define SSB_SPROM4_GPIOB_P3_SHIFT 8
|
||||||
|
-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
|
||||||
|
-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
|
||||||
|
-#define SSB_SPROM4_PA0B2 0x1086
|
||||||
|
-#define SSB_SPROM4_PA1B0 0x108E
|
||||||
|
-#define SSB_SPROM4_PA1B1 0x1090
|
||||||
|
-#define SSB_SPROM4_PA1B2 0x1092
|
||||||
|
+#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
|
||||||
|
+#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
|
||||||
|
+#define SSB_SPROM4_PA0B2 0x0086
|
||||||
|
+#define SSB_SPROM4_PA1B0 0x008E
|
||||||
|
+#define SSB_SPROM4_PA1B1 0x0090
|
||||||
|
+#define SSB_SPROM4_PA1B2 0x0092
|
||||||
|
|
||||||
|
/* SPROM Revision 5 (inherits most data from rev 4) */
|
||||||
|
-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
|
||||||
|
-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
|
||||||
|
-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
|
||||||
|
-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
|
||||||
|
-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
|
||||||
|
+#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
|
||||||
|
+#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
|
||||||
|
+#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
|
||||||
|
+#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
|
||||||
|
+#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
|
||||||
|
#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
#define SSB_SPROM5_GPIOA_P1_SHIFT 8
|
||||||
|
-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
+#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
#define SSB_SPROM5_GPIOB_P3_SHIFT 8
|
||||||
|
|
||||||
|
/* SPROM Revision 8 */
|
||||||
|
-#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
|
||||||
|
-#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
|
||||||
|
-#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
|
||||||
|
-#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
|
||||||
|
-#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
|
||||||
|
-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
|
||||||
|
-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
|
||||||
|
-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
|
||||||
|
-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
|
||||||
|
+#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
|
||||||
|
+#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
|
||||||
|
+#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
|
||||||
|
+#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
|
||||||
|
+#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
|
||||||
|
+#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
|
||||||
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+#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
|
||||||
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+#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
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||||||
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+#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
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||||||
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+#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
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||||||
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+#define SSB_SPROM8_GPIOA_P1_SHIFT 8
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||||||
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+#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
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||||||
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+#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
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||||||
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+#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
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||||||
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+#define SSB_SPROM8_GPIOB_P3_SHIFT 8
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||||||
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+#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
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||||||
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+#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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||||||
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+#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
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||||||
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+#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
|
||||||
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+#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
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||||||
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+#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
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||||||
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#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
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||||||
|
#define SSB_SPROM8_AGAIN0_SHIFT 0
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||||||
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#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
|
||||||
|
#define SSB_SPROM8_AGAIN1_SHIFT 8
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||||||
|
-#define SSB_SPROM8_AGAIN23 0x10A0
|
||||||
|
+#define SSB_SPROM8_AGAIN23 0x00A0
|
||||||
|
#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
|
||||||
|
#define SSB_SPROM8_AGAIN2_SHIFT 0
|
||||||
|
#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
|
||||||
|
#define SSB_SPROM8_AGAIN3_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
|
||||||
|
-#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
|
||||||
|
-#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
|
||||||
|
-#define SSB_SPROM8_GPIOA_P1_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
|
||||||
|
-#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
|
||||||
|
-#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
|
||||||
|
-#define SSB_SPROM8_GPIOB_P3_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
|
||||||
|
+#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
|
||||||
|
#define SSB_SPROM8_RSSISMF2G 0x000F
|
||||||
|
#define SSB_SPROM8_RSSISMC2G 0x00F0
|
||||||
|
#define SSB_SPROM8_RSSISMC2G_SHIFT 4
|
||||||
|
@@ -365,7 +366,7 @@
|
||||||
|
#define SSB_SPROM8_RSSISAV2G_SHIFT 8
|
||||||
|
#define SSB_SPROM8_BXA2G 0x1800
|
||||||
|
#define SSB_SPROM8_BXA2G_SHIFT 11
|
||||||
|
-#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
|
||||||
|
+#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
|
||||||
|
#define SSB_SPROM8_RSSISMF5G 0x000F
|
||||||
|
#define SSB_SPROM8_RSSISMC5G 0x00F0
|
||||||
|
#define SSB_SPROM8_RSSISMC5G_SHIFT 4
|
||||||
|
@@ -373,47 +374,47 @@
|
||||||
|
#define SSB_SPROM8_RSSISAV5G_SHIFT 8
|
||||||
|
#define SSB_SPROM8_BXA5G 0x1800
|
||||||
|
#define SSB_SPROM8_BXA5G_SHIFT 11
|
||||||
|
-#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
|
||||||
|
+#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
|
||||||
|
#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
|
||||||
|
#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
|
||||||
|
#define SSB_SPROM8_TRI5G_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
|
||||||
|
+#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
|
||||||
|
#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
|
||||||
|
#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
|
||||||
|
#define SSB_SPROM8_TRI5GH_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
|
||||||
|
+#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
|
||||||
|
#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
|
||||||
|
#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
|
||||||
|
#define SSB_SPROM8_RXPO5G_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
|
||||||
|
+#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
|
||||||
|
#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
|
||||||
|
#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
|
||||||
|
#define SSB_SPROM8_ITSSI_BG_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
|
||||||
|
-#define SSB_SPROM8_PA0B1 0x10C4
|
||||||
|
-#define SSB_SPROM8_PA0B2 0x10C6
|
||||||
|
-#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
|
||||||
|
+#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
|
||||||
|
+#define SSB_SPROM8_PA0B1 0x00C4
|
||||||
|
+#define SSB_SPROM8_PA0B2 0x00C6
|
||||||
|
+#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
|
||||||
|
#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
|
||||||
|
#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
|
||||||
|
#define SSB_SPROM8_ITSSI_A_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
|
||||||
|
+#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
|
||||||
|
#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
|
||||||
|
#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
|
||||||
|
#define SSB_SPROM8_MAXP_AL_SHIFT 8
|
||||||
|
-#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
|
||||||
|
-#define SSB_SPROM8_PA1B1 0x10CE
|
||||||
|
-#define SSB_SPROM8_PA1B2 0x10D0
|
||||||
|
-#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
|
||||||
|
-#define SSB_SPROM8_PA1LOB1 0x10D4
|
||||||
|
-#define SSB_SPROM8_PA1LOB2 0x10D6
|
||||||
|
-#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
|
||||||
|
-#define SSB_SPROM8_PA1HIB1 0x10DA
|
||||||
|
-#define SSB_SPROM8_PA1HIB2 0x10DC
|
||||||
|
-#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
|
||||||
|
-#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
|
||||||
|
-#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
|
||||||
|
-#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
|
||||||
|
-#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
|
||||||
|
+#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
|
||||||
|
+#define SSB_SPROM8_PA1B1 0x00CE
|
||||||
|
+#define SSB_SPROM8_PA1B2 0x00D0
|
||||||
|
+#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
|
||||||
|
+#define SSB_SPROM8_PA1LOB1 0x00D4
|
||||||
|
+#define SSB_SPROM8_PA1LOB2 0x00D6
|
||||||
|
+#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
|
||||||
|
+#define SSB_SPROM8_PA1HIB1 0x00DA
|
||||||
|
+#define SSB_SPROM8_PA1HIB2 0x00DC
|
||||||
|
+#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
|
||||||
|
+#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
|
||||||
|
+#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
|
||||||
|
+#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
|
||||||
|
+#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
|
||||||
|
|
||||||
|
/* Values for SSB_SPROM1_BINF_CCODE */
|
||||||
|
enum {
|
Loading…
Reference in New Issue
Block a user