mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
update work in progress rewritten bcm947xx code. wifi and usb seem to be working, flash access still has problems
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6276 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
549
target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c
Normal file
549
target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c
Normal file
@@ -0,0 +1,549 @@
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/*
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* Sonics Silicon Backplane
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* Broadcom PCI-core driver
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <linux/ssb/ssb.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include "../ssb_private.h"
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static inline
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u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
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{
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return ssb_read32(pc->dev, offset);
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}
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static inline
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void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
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{
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ssb_write32(pc->dev, offset, value);
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}
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/**************************************************
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* Code for hostmode operation.
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**************************************************/
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#ifdef CONFIG_SSB_PCICORE_HOSTMODE
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#include <asm/paccess.h>
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/* Read the bus and catch bus exceptions. This is MIPS specific. */
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#define mips_busprobe(val, addr) get_dbe((val), (addr))
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/* Assume one-hot slot wiring */
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#define SSB_PCI_SLOT_MAX 16
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/* Global lock is OK, as we won't have more than one extpci anyway. */
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static DEFINE_SPINLOCK(cfgspace_lock);
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/* Core to access the external PCI config space. Can only have one. */
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static struct ssb_pcicore *extpci_core;
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u32 pci_iobase = 0x100;
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u32 pci_membase = SSB_PCI_DMA;
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int pcibios_plat_dev_init(struct pci_dev *d)
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{
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struct resource *res;
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int pos, size;
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u32 *base;
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printk("PCI: Fixing up device %s\n", pci_name(d));
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/* Fix up resource bases */
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for (pos = 0; pos < 6; pos++) {
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res = &d->resource[pos];
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base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
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if (res->end) {
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size = res->end - res->start + 1;
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if (*base & (size - 1))
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*base = (*base + size) & ~(size - 1);
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res->start = *base;
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res->end = res->start + size - 1;
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*base += size;
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pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
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}
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/* Fix up PCI bridge BAR0 only */
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if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
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break;
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}
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/* Fix up interrupt lines */
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d->irq = ssb_mips_irq(extpci_core->dev) + 2;
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pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
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return 0;
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}
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static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
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{
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if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
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return;
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printk("PCI: fixing up bridge\n");
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/* Enable PCI bridge bus mastering and memory space */
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pci_set_master(dev);
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pcibios_enable_device(dev, ~0);
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/* Enable PCI bridge BAR1 prefetch and burst */
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pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
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int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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return ssb_mips_irq(extpci_core->dev) + 2;
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}
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static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
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unsigned int bus, unsigned int dev,
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unsigned int func, unsigned int off)
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{
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u32 addr = 0;
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u32 tmp;
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if (unlikely(pc->cardbusmode && dev > 1))
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goto out;
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if (bus == 0) {//FIXME busnumber ok?
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/* Type 0 transaction */
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if (unlikely(dev >= SSB_PCI_SLOT_MAX))
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goto out;
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/* Slide the window */
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tmp = SSB_PCICORE_SBTOPCI_CFG0;
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tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
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/* Calculate the address */
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addr = SSB_PCI_CFG;
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addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
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addr |= (func << 8);
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addr |= (off & ~3);
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} else {
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/* Type 1 transaction */
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
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SSB_PCICORE_SBTOPCI_CFG1);
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/* Calculate the address */
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addr = SSB_PCI_CFG;
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addr |= (bus << 16);
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addr |= (dev << 11);
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addr |= (func << 8);
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addr |= (off & ~3);
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}
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out:
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return addr;
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}
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static int ssb_extpci_read_config(struct ssb_pcicore *pc,
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unsigned int bus, unsigned int dev,
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unsigned int func, unsigned int off,
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void *buf, int len)
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{
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int err = -EINVAL;
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u32 addr, val;
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void __iomem *mmio;
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assert(pc->hostmode);
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if (unlikely(len != 1 && len != 2 && len != 4))
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goto out;
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addr = get_cfgspace_addr(pc, bus, dev, func, off);
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if (unlikely(!addr))
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goto out;
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err = -ENOMEM;
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mmio = ioremap_nocache(addr, len);
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if (!mmio)
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goto out;
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if (mips_busprobe(val, (u32 *) mmio)) {
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val = 0xffffffff;
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goto unmap;
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}
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val = readl(mmio);
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val >>= (8 * (off & 3));
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switch (len) {
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case 1:
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*((u8 *)buf) = (u8)val;
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break;
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case 2:
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*((u16 *)buf) = (u16)val;
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break;
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case 4:
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*((u32 *)buf) = (u32)val;
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break;
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}
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err = 0;
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unmap:
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iounmap(mmio);
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out:
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return err;
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}
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static int ssb_extpci_write_config(struct ssb_pcicore *pc,
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unsigned int bus, unsigned int dev,
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unsigned int func, unsigned int off,
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const void *buf, int len)
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{
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int err = -EINVAL;
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u32 addr, val = 0;
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void __iomem *mmio;
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assert(pc->hostmode);
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if (unlikely(len != 1 && len != 2 && len != 4))
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goto out;
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addr = get_cfgspace_addr(pc, bus, dev, func, off);
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if (unlikely(!addr))
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goto out;
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err = -ENOMEM;
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mmio = ioremap_nocache(addr, len);
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if (!mmio)
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goto out;
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if (mips_busprobe(val, (u32 *) mmio)) {
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val = 0xffffffff;
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goto unmap;
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}
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switch (len) {
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case 1:
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val = readl(mmio);
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val &= ~(0xFF << (8 * (off & 3)));
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val |= *((const u8 *)buf) << (8 * (off & 3));
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break;
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case 2:
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val = readl(mmio);
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val &= ~(0xFFFF << (8 * (off & 3)));
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val |= *((const u16 *)buf) << (8 * (off & 3));
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break;
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case 4:
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val = *((const u32 *)buf);
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break;
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}
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writel(*((const u32 *)buf), mmio);
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err = 0;
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unmap:
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iounmap(mmio);
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out:
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return err;
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}
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static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
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int reg, int size, u32 *val)
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{
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unsigned long flags;
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int err;
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spin_lock_irqsave(&cfgspace_lock, flags);
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err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), reg, val, size);
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spin_unlock_irqrestore(&cfgspace_lock, flags);
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return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
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int reg, int size, u32 val)
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{
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unsigned long flags;
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int err;
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spin_lock_irqsave(&cfgspace_lock, flags);
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err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), reg, &val, size);
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spin_unlock_irqrestore(&cfgspace_lock, flags);
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return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops ssb_pcicore_pciops = {
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.read = ssb_pcicore_read_config,
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.write = ssb_pcicore_write_config,
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};
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static struct resource ssb_pcicore_mem_resource = {
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.name = "SSB PCIcore external memory",
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.start = SSB_PCI_DMA,
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.end = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource ssb_pcicore_io_resource = {
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.name = "SSB PCIcore external I/O",
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.start = 0x100,
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.end = 0x7FF,
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.flags = IORESOURCE_IO,
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};
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static struct pci_controller ssb_pcicore_controller = {
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.pci_ops = &ssb_pcicore_pciops,
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.io_resource = &ssb_pcicore_io_resource,
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.mem_resource = &ssb_pcicore_mem_resource,
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.mem_offset = 0x24000000,
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};
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static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
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{
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u32 val;
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assert(!extpci_core);
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extpci_core = pc;
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ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
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/* Reset devices on the external PCI bus */
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val = SSB_PCICORE_CTL_RST_OE;
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val |= SSB_PCICORE_CTL_CLK_OE;
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pcicore_write32(pc, SSB_PCICORE_CTL, val);
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val |= SSB_PCICORE_CTL_CLK; /* Clock on */
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||||
pcicore_write32(pc, SSB_PCICORE_CTL, val);
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||||
udelay(150);
|
||||
val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
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pcicore_write32(pc, SSB_PCICORE_CTL, val);
|
||||
udelay(1);
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||||
|
||||
//TODO cardbus mode
|
||||
|
||||
/* 64MB I/O window */
|
||||
pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
|
||||
SSB_PCICORE_SBTOPCI_IO);
|
||||
/* 64MB config space */
|
||||
pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
|
||||
SSB_PCICORE_SBTOPCI_CFG0);
|
||||
/* 1GB memory window */
|
||||
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
|
||||
SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
|
||||
|
||||
/* Enable PCI bridge BAR0 prefetch and burst */
|
||||
val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 4);
|
||||
|
||||
/* Enable PCI interrupts */
|
||||
pcicore_write32(pc, SSB_PCICORE_IMASK,
|
||||
SSB_PCICORE_IMASK_INTA);
|
||||
|
||||
/* Ok, ready to run, register it to the system.
|
||||
* The following needs change, if we want to port hostmode
|
||||
* to non-MIPS platform. */
|
||||
set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
|
||||
register_pci_controller(&ssb_pcicore_controller);
|
||||
}
|
||||
|
||||
static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
|
||||
{
|
||||
struct ssb_bus *bus = pc->dev->bus;
|
||||
u16 chipid_top;
|
||||
u32 tmp;
|
||||
|
||||
chipid_top = (bus->chip_id & 0xFF00);
|
||||
if (chipid_top != 0x4700 &&
|
||||
chipid_top != 0x5300)
|
||||
return 0;
|
||||
|
||||
if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
|
||||
return 0;
|
||||
|
||||
/* The 200-pin BCM4712 package does not bond out PCI. Even when
|
||||
* PCI is bonded out, some boards may leave the pins floating. */
|
||||
if (bus->chip_id == 0x4712) {
|
||||
if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
|
||||
return 0;
|
||||
if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
|
||||
return 0;
|
||||
}
|
||||
if (bus->chip_id == 0x5350)
|
||||
return 0;
|
||||
|
||||
return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
|
||||
}
|
||||
#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
|
||||
|
||||
|
||||
/**************************************************
|
||||
* Generic and Clientmode operation code.
|
||||
**************************************************/
|
||||
|
||||
static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
|
||||
{
|
||||
/* Disable PCI interrupts. */
|
||||
ssb_write32(pc->dev, SSB_INTVEC, 0);
|
||||
}
|
||||
|
||||
void ssb_pcicore_init(struct ssb_pcicore *pc)
|
||||
{
|
||||
struct ssb_device *dev = pc->dev;
|
||||
struct ssb_bus *bus;
|
||||
|
||||
if (!dev)
|
||||
return;
|
||||
bus = dev->bus;
|
||||
if (!ssb_device_is_enabled(dev))
|
||||
ssb_device_enable(dev, 0);
|
||||
|
||||
#ifdef CONFIG_SSB_PCICORE_HOSTMODE
|
||||
pc->hostmode = pcicore_is_in_hostmode(pc);
|
||||
if (pc->hostmode)
|
||||
ssb_pcicore_init_hostmode(pc);
|
||||
#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
|
||||
if (!pc->hostmode)
|
||||
ssb_pcicore_init_clientmode(pc);
|
||||
}
|
||||
|
||||
static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
|
||||
{
|
||||
pcicore_write32(pc, 0x130, address);
|
||||
return pcicore_read32(pc, 0x134);
|
||||
}
|
||||
|
||||
static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
|
||||
{
|
||||
pcicore_write32(pc, 0x130, address);
|
||||
pcicore_write32(pc, 0x134, data);
|
||||
}
|
||||
|
||||
static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
|
||||
u8 address, u16 data)
|
||||
{
|
||||
const u16 mdio_control = 0x128;
|
||||
const u16 mdio_data = 0x12C;
|
||||
u32 v;
|
||||
int i;
|
||||
|
||||
v = 0x80; /* Enable Preamble Sequence */
|
||||
v |= 0x2; /* MDIO Clock Divisor */
|
||||
pcicore_write32(pc, mdio_control, v);
|
||||
|
||||
v = (1 << 30); /* Start of Transaction */
|
||||
v |= (1 << 28); /* Write Transaction */
|
||||
v |= (1 << 17); /* Turnaround */
|
||||
v |= (u32)device << 22;
|
||||
v |= (u32)address << 18;
|
||||
v |= data;
|
||||
pcicore_write32(pc, mdio_data, v);
|
||||
udelay(10);
|
||||
for (i = 0; i < 10; i++) {
|
||||
v = pcicore_read32(pc, mdio_control);
|
||||
if (v & 0x100 /* Trans complete */)
|
||||
break;
|
||||
msleep(1);
|
||||
}
|
||||
pcicore_write32(pc, mdio_control, 0);
|
||||
}
|
||||
|
||||
static void ssb_broadcast_value(struct ssb_device *dev,
|
||||
u32 address, u32 data)
|
||||
{
|
||||
/* This is used for both, PCI and ChipCommon core, so be careful. */
|
||||
BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
|
||||
BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
|
||||
|
||||
ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
|
||||
ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
|
||||
ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
|
||||
ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
|
||||
}
|
||||
|
||||
static void ssb_commit_settings(struct ssb_bus *bus)
|
||||
{
|
||||
struct ssb_device *dev;
|
||||
|
||||
dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
|
||||
assert(dev);
|
||||
/* This forces an update of the cached registers. */
|
||||
ssb_broadcast_value(dev, 0xFD8, 0);
|
||||
}
|
||||
|
||||
int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
|
||||
struct ssb_device *dev)
|
||||
{
|
||||
struct ssb_device *pdev = pc->dev;
|
||||
struct ssb_bus *bus;
|
||||
int err = 0;
|
||||
u32 tmp;
|
||||
|
||||
might_sleep();
|
||||
|
||||
if (!pdev)
|
||||
goto out;
|
||||
bus = pdev->bus;
|
||||
|
||||
/* Enable interrupts for this device. */
|
||||
if (bus->host_pci &&
|
||||
((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
|
||||
u32 coremask;
|
||||
|
||||
/* Calculate the "coremask" for the device. */
|
||||
coremask = (1 << dev->core_index);
|
||||
|
||||
err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
|
||||
if (err)
|
||||
goto out;
|
||||
tmp |= coremask << 8;
|
||||
err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
|
||||
if (err)
|
||||
goto out;
|
||||
} else {
|
||||
u32 intvec;
|
||||
|
||||
intvec = ssb_read32(pdev, SSB_INTVEC);
|
||||
tmp = ssb_read32(dev, SSB_TPSFLAG);
|
||||
tmp &= SSB_TPSFLAG_BPFLAG;
|
||||
intvec |= tmp;
|
||||
ssb_write32(pdev, SSB_INTVEC, intvec);
|
||||
}
|
||||
|
||||
/* Setup PCIcore operation. */
|
||||
if (pc->setup_done)
|
||||
goto out;
|
||||
if (pdev->id.coreid == SSB_DEV_PCI) {
|
||||
tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
|
||||
tmp |= SSB_PCICORE_SBTOPCI_PREF;
|
||||
tmp |= SSB_PCICORE_SBTOPCI_BURST;
|
||||
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
|
||||
|
||||
if (pdev->id.revision < 5) {
|
||||
tmp = ssb_read32(pdev, SSB_IMCFGLO);
|
||||
tmp &= ~SSB_IMCFGLO_SERTO;
|
||||
tmp |= 2;
|
||||
tmp &= ~SSB_IMCFGLO_REQTO;
|
||||
tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
|
||||
ssb_write32(pdev, SSB_IMCFGLO, tmp);
|
||||
ssb_commit_settings(bus);
|
||||
} else if (pdev->id.revision >= 11) {
|
||||
tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
|
||||
tmp |= SSB_PCICORE_SBTOPCI_MRM;
|
||||
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
|
||||
}
|
||||
} else {
|
||||
assert(pdev->id.coreid == SSB_DEV_PCIE);
|
||||
//TODO: Better make defines for all these magic PCIE values.
|
||||
if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
|
||||
/* TLP Workaround register. */
|
||||
tmp = ssb_pcie_read(pc, 0x4);
|
||||
tmp |= 0x8;
|
||||
ssb_pcie_write(pc, 0x4, tmp);
|
||||
}
|
||||
if (pdev->id.revision == 0) {
|
||||
const u8 serdes_rx_device = 0x1F;
|
||||
|
||||
ssb_pcie_mdio_write(pc, serdes_rx_device,
|
||||
2 /* Timer */, 0x8128);
|
||||
ssb_pcie_mdio_write(pc, serdes_rx_device,
|
||||
6 /* CDR */, 0x0100);
|
||||
ssb_pcie_mdio_write(pc, serdes_rx_device,
|
||||
7 /* CDR BW */, 0x1466);
|
||||
} else if (pdev->id.revision == 1) {
|
||||
/* DLLP Link Control register. */
|
||||
tmp = ssb_pcie_read(pc, 0x100);
|
||||
tmp |= 0x40;
|
||||
ssb_pcie_write(pc, 0x100, tmp);
|
||||
}
|
||||
}
|
||||
pc->setup_done = 1;
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
|
||||
Reference in New Issue
Block a user