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cns3xxx: clean up pcie patches
Combine two pcie patches (2nd patch undid the 1st patch) together and refresh the other affected patches Signed-off-by: Tim Harvey <tharvey@gateworks.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34132 3c298f89-4303-0410-b956-a3cf2f4a3e73
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42fc31c396
@ -1,76 +0,0 @@
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -32,6 +32,7 @@
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#include <asm/mach/time.h>
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#include <mach/cns3xxx.h>
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#include <mach/irqs.h>
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+#include <mach/platform.h>
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#include "core.h"
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#include "devices.h"
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@@ -199,6 +200,8 @@ static void __init cns3420_init(void)
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cns3xxx_ahci_init();
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cns3xxx_sdhci_init();
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+ cns3xxx_pcie_init(0x3);
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+
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pm_power_off = cns3xxx_power_off;
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}
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -12,6 +12,8 @@
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#define __CNS3XXX_CORE_H
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extern struct sys_timer cns3xxx_timer;
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+extern int cns3xxx_pcie_init(u8 bitmap);
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+extern void cns3xxx_pcie_iotable_init(u8 bitmap);
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#ifdef CONFIG_CACHE_L2X0
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void __init cns3xxx_l2x0_init(void);
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--- a/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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@@ -365,7 +365,23 @@ static int cns3xxx_pcie_abort_handler(un
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return 0;
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}
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-static int __init cns3xxx_pcie_init(void)
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+void __init cns3xxx_pcie_iotable_init(u8 bitmap)
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+{
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+ static int _iotable_init = 0;
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+ int i;
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+
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+ bitmap &= ~_iotable_init;
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+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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+ if (!(bitmap & (1 << i)))
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+ continue;
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+
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+ iotable_init(cns3xxx_pcie[i].cfg_bases,
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+ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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+ }
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+ _iotable_init |= bitmap;
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+}
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+
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+int __init cns3xxx_pcie_init(u8 bitmap)
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{
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int i;
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@@ -375,9 +391,11 @@ static int __init cns3xxx_pcie_init(void
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hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
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"imprecise external abort");
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+ cns3xxx_pcie_iotable_init(bitmap);
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for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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- iotable_init(cns3xxx_pcie[i].cfg_bases,
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- ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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+ if (!(bitmap & (1 << i)))
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+ continue;
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+
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cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
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cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
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pci_common_init(&cns3xxx_pcie[i].hw_pci);
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@@ -387,4 +405,3 @@ static int __init cns3xxx_pcie_init(void
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return 0;
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}
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-device_initcall(cns3xxx_pcie_init);
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@ -1,6 +1,6 @@
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -216,7 +216,7 @@ static struct map_desc cns3420_io_desc[]
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@@ -213,7 +213,7 @@ static struct map_desc cns3420_io_desc[]
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static void __init cns3420_map_io(void)
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static void __init cns3420_map_io(void)
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{
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{
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@ -96,7 +96,7 @@
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/* used by entry-macro.S */
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/* used by entry-macro.S */
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--- a/arch/arm/mach-cns3xxx/core.h
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -21,7 +21,7 @@ void __init cns3xxx_l2x0_init(void);
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@@ -19,7 +19,7 @@ void __init cns3xxx_l2x0_init(void);
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static inline void cns3xxx_l2x0_init(void) {}
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static inline void cns3xxx_l2x0_init(void) {}
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#endif /* CONFIG_CACHE_L2X0 */
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#endif /* CONFIG_CACHE_L2X0 */
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@ -8,18 +8,17 @@
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obj-$(CONFIG_MACH_GW2388) += laguna.o
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obj-$(CONFIG_MACH_GW2388) += laguna.o
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -199,7 +199,10 @@ static void __init cns3420_init(void)
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@@ -198,6 +198,10 @@ static void __init cns3420_init(void)
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cns3xxx_ahci_init();
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cns3xxx_ahci_init();
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cns3xxx_sdhci_init();
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cns3xxx_sdhci_init();
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-
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+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
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+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
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+ NR_IRQS_CNS3XXX);
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+ NR_IRQS_CNS3XXX);
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+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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+ NR_IRQS_CNS3XXX + 32);
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+ NR_IRQS_CNS3XXX + 32);
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cns3xxx_pcie_init(0x3);
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pm_power_off = cns3xxx_power_off;
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pm_power_off = cns3xxx_power_off;
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}
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--- a/arch/arm/mach-cns3xxx/core.c
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -21,7 +21,6 @@
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@@ -21,7 +21,6 @@
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@ -1,14 +1,6 @@
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -203,7 +203,6 @@ static void __init cns3420_init(void)
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@@ -218,11 +218,21 @@ static struct map_desc cns3420_io_desc[]
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NR_IRQS_CNS3XXX);
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cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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NR_IRQS_CNS3XXX + 32);
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- cns3xxx_pcie_init(0x3);
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pm_power_off = cns3xxx_power_off;
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}
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@@ -220,11 +219,21 @@ static struct map_desc cns3420_io_desc[]
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static void __init cns3420_map_io(void)
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static void __init cns3420_map_io(void)
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{
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{
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cns3xxx_common_init();
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cns3xxx_common_init();
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@ -32,18 +24,16 @@
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.map_io = cns3420_map_io,
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.map_io = cns3420_map_io,
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--- a/arch/arm/mach-cns3xxx/core.h
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -12,8 +12,8 @@
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@@ -12,6 +12,8 @@
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#define __CNS3XXX_CORE_H
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#define __CNS3XXX_CORE_H
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extern struct sys_timer cns3xxx_timer;
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extern struct sys_timer cns3xxx_timer;
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-extern int cns3xxx_pcie_init(u8 bitmap);
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-extern void cns3xxx_pcie_iotable_init(u8 bitmap);
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+extern void cns3xxx_pcie_iotable_init(void);
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+extern void cns3xxx_pcie_iotable_init(void);
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+
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+
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#ifdef CONFIG_CACHE_L2X0
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#ifdef CONFIG_CACHE_L2X0
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void __init cns3xxx_l2x0_init(void);
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void __init cns3xxx_l2x0_init(void);
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@@ -23,6 +23,7 @@ static inline void cns3xxx_l2x0_init(voi
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@@ -21,6 +23,7 @@ static inline void cns3xxx_l2x0_init(voi
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void __init cns3xxx_common_init(void);
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void __init cns3xxx_common_init(void);
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void __init cns3xxx_init_irq(void);
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void __init cns3xxx_init_irq(void);
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@ -53,42 +43,32 @@
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--- a/arch/arm/mach-cns3xxx/pcie.c
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--- a/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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@@ -456,23 +456,18 @@ static int cns3xxx_pcie_abort_handler(un
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@@ -456,7 +456,18 @@ static int cns3xxx_pcie_abort_handler(un
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return 0;
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return 0;
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}
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}
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-void __init cns3xxx_pcie_iotable_init(u8 bitmap)
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-static int __init cns3xxx_pcie_init(void)
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+
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+
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+void __init cns3xxx_pcie_iotable_init()
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+void __init cns3xxx_pcie_iotable_init()
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{
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+{
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- static int _iotable_init = 0;
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+ int i;
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int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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- bitmap &= ~_iotable_init;
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+ iotable_init(cns3xxx_pcie[i].cfg_bases,
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for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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+ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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- if (!(bitmap & (1 << i)))
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+ }
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- continue;
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+}
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-
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+
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iotable_init(cns3xxx_pcie[i].cfg_bases,
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ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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}
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- _iotable_init |= bitmap;
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}
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-int __init cns3xxx_pcie_init(u8 bitmap)
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+int __init cns3xxx_pcie_init(void)
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+int __init cns3xxx_pcie_init(void)
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{
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{
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int i;
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int i;
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@@ -482,14 +477,12 @@ int __init cns3xxx_pcie_init(u8 bitmap)
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@@ -467,15 +478,14 @@ static int __init cns3xxx_pcie_init(void
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hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
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"imprecise external abort");
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"imprecise external abort");
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- cns3xxx_pcie_iotable_init(bitmap);
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for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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- if (!(bitmap & (1 << i)))
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- iotable_init(cns3xxx_pcie[i].cfg_bases,
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- continue;
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- ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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-
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cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
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cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
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- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
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- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
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- pci_common_init(&cns3xxx_pcie[i].hw_pci);
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- pci_common_init(&cns3xxx_pcie[i].hw_pci);
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@ -99,3 +79,7 @@
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}
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}
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pci_assign_unassigned_resources();
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pci_assign_unassigned_resources();
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return 0;
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}
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-device_initcall(cns3xxx_pcie_init);
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