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lots of code cleanup for ifxmips

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11570 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2008-06-23 20:31:34 +00:00
parent 9f4462d801
commit 43ba67e0d5
17 changed files with 375 additions and 468 deletions
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52
target/linux/ifxmips/files/arch/mips/ifxmips/board.c
View File

@@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/board.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -16,7 +14,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/autoconf.h>
@@ -43,13 +40,11 @@
#define BOARD_TWINPASS "Twinpass"
#define BOARD_TWINPASS_CHIPID 0x3012D083
#define BOARD_DANUBE "Danube"
static unsigned int chiprev;
static struct platform_device *ifxmips_devs[MAX_IFXMIPS_DEVS];
static struct platform_device ifxmips_led[] =
static struct platform_device
ifxmips_led[] =
{
{
.id = 0,
@@ -57,7 +52,8 @@ static struct platform_device ifxmips_led[] =
},
};
static struct platform_device ifxmips_gpio[] =
static struct platform_device
ifxmips_gpio[] =
{
{
.id = 0,
@@ -65,7 +61,8 @@ static struct platform_device ifxmips_gpio[] =
},
};
static struct platform_device ifxmips_mii[] =
static struct platform_device
ifxmips_mii[] =
{
{
.id = 0,
@@ -73,7 +70,8 @@ static struct platform_device ifxmips_mii[] =
},
};
static struct platform_device ifxmips_wdt[] =
static struct platform_device
ifxmips_wdt[] =
{
{
.id = 0,
@@ -81,17 +79,20 @@ static struct platform_device ifxmips_wdt[] =
},
};
static struct physmap_flash_data ifxmips_mtd_data = {
static struct physmap_flash_data
ifxmips_mtd_data = {
.width = 2,
};
static struct resource ifxmips_mtd_resource = {
static struct resource
ifxmips_mtd_resource = {
.start = IFXMIPS_FLASH_START,
.end = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device ifxmips_mtd[] =
static struct platform_device
ifxmips_mtd[] =
{
{
.id = 0,
@@ -105,16 +106,20 @@ static struct platform_device ifxmips_mtd[] =
};
#ifdef CONFIG_GPIO_DEVICE
static struct resource ifxmips_gpio_dev_resources[] = {
static struct resource
ifxmips_gpio_dev_resources[] = {
{
.name = "gpio",
.flags = 0,
.start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12),
.end = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12),
.start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
(1 << 4) | (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12),
.end = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
(1 << 4) | (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12),
},
};
static struct platform_device ifxmips_gpio_dev[] = {
static struct platform_device
ifxmips_gpio_dev[] = {
{
.name = "GPIODEV",
.id = -1,
@@ -125,7 +130,7 @@ static struct platform_device ifxmips_gpio_dev[] = {
#endif
const char*
get_system_type (void)
get_system_type(void)
{
chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID);
switch(chiprev)
@@ -140,18 +145,11 @@ get_system_type (void)
return BOARD_SYSTEM_TYPE;
}
int __init ifxmips_init_devices(void)
int __init
ifxmips_init_devices(void)
{
/*
* This is where we detect what chip we are running on
* Currently we support 3 chips
* 1.) Danube
* 2.) Twinpass (Danube without dsl phy)
*/
int dev = 0;
/* the following devices are generic for all targets */
ifxmips_devs[dev++] = ifxmips_led;
ifxmips_devs[dev++] = ifxmips_gpio;
ifxmips_devs[dev++] = ifxmips_mii;

145
target/linux/ifxmips/files/arch/mips/ifxmips/cgu.c
View File

@@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/cgu.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -16,10 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 Xu Liang, infineon
*
* Rewrite of Infineon IFXMips code
* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/kernel.h>
@@ -75,9 +70,10 @@
#define CGU_IF_CLK_USBSEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
#define CGU_IF_CLK_MIISEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
static u32 cgu_get_pll0_fdiv(void);
static unsigned int cgu_get_pll0_fdiv(void);
static inline u32 get_input_clock(int pll)
static inline unsigned int
get_input_clock(int pll)
{
switch(pll)
{
@@ -110,8 +106,8 @@ static inline u32 get_input_clock(int pll)
}
}
static inline u32
cal_dsm(int pll, u32 num, u32 den)
static inline unsigned int
cal_dsm(int pll, unsigned int num, unsigned int den)
{
u64 res, clock = get_input_clock(pll);
@@ -120,56 +116,65 @@ cal_dsm(int pll, u32 num, u32 den)
return res;
}
static inline u32
mash_dsm(int pll, u32 M, u32 N, u32 K)
static inline unsigned int
mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
{
u32 num = ((N + 1) << 10) + K;
u32 den = (M + 1) << 10;
unsigned int num = ((N + 1) << 10) + K;
unsigned int den = (M + 1) << 10;
return cal_dsm(pll, num, den);
}
static inline u32 ssff_dsm_1(int pll, u32 M, u32 N, u32 K)
static inline unsigned int
ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
{
u32 num = ((N + 1) << 11) + K + 512;
u32 den = (M + 1) << 11;
unsigned int num = ((N + 1) << 11) + K + 512;
unsigned int den = (M + 1) << 11;
return cal_dsm(pll, num, den);
}
static inline u32 ssff_dsm_2(int pll, u32 M, u32 N, u32 K)
static inline unsigned int
ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
{
u32 num = K >= 512 ? ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
u32 den = (M + 1) << 12;
unsigned int num = K >= 512 ?
((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
unsigned int den = (M + 1) << 12;
return cal_dsm(pll, num, den);
}
static inline u32 dsm(int pll, u32 M, u32 N, u32 K, u32 dsmsel, u32 phase_div_en)
static inline unsigned int
dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
unsigned int dsmsel, unsigned int phase_div_en)
{
if ( !dsmsel )
if(!dsmsel)
return mash_dsm(pll, M, N, K);
else if ( !phase_div_en )
else if(!phase_div_en)
return mash_dsm(pll, M, N, K);
else
return ssff_dsm_2(pll, M, N, K);
}
static inline u32 cgu_get_pll0_fosc(void)
static inline unsigned int
cgu_get_pll0_fosc(void)
{
if(CGU_PLL0_BYPASS)
return get_input_clock(0);
else
return !CGU_PLL0_CFG_FRAC_EN
? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE)
: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
CGU_PLL0_PHASE_DIVIDER_ENABLE)
: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
}
static inline u32 cgu_get_pll0_fps(int phase)
static inline unsigned int
cgu_get_pll0_fps(int phase)
{
register u32 fps = cgu_get_pll0_fosc();
register unsigned int fps = cgu_get_pll0_fosc();
switch ( phase )
switch(phase)
{
case 1:
/* 1.25 */
@@ -183,14 +188,16 @@ static inline u32 cgu_get_pll0_fps(int phase)
return fps;
}
static u32 cgu_get_pll0_fdiv(void)
static unsigned int
cgu_get_pll0_fdiv(void)
{
register u32 div = CGU_PLL2_CFG_INPUT_DIV + 1;
register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
return (cgu_get_pll0_fosc() + (div >> 1)) / div;
}
static inline u32 cgu_get_pll1_fosc(void)
static inline unsigned int
cgu_get_pll1_fosc(void)
{
if(CGU_PLL1_BYPASS)
return get_input_clock(1);
@@ -200,19 +207,22 @@ static inline u32 cgu_get_pll1_fosc(void)
: dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
}
static inline u32 cgu_get_pll1_fps(void)
static inline unsigned int
cgu_get_pll1_fps(void)
{
register u32 fps = cgu_get_pll1_fosc();
register unsigned int fps = cgu_get_pll1_fosc();
return ((fps << 1) + 1) / 3;
}
static inline u32 cgu_get_pll1_fdiv(void)
static inline unsigned int
cgu_get_pll1_fdiv(void)
{
return cgu_get_pll1_fosc();
}
static inline u32 cgu_get_pll2_fosc(void)
static inline unsigned int
cgu_get_pll2_fosc(void)
{
u64 res, clock = get_input_clock(2);
@@ -225,9 +235,10 @@ static inline u32 cgu_get_pll2_fosc(void)
return res;
}
static inline u32 cgu_get_pll2_fps(int phase)
static inline unsigned int
cgu_get_pll2_fps(int phase)
{
register u32 fps = cgu_get_pll2_fosc();
register unsigned int fps = cgu_get_pll2_fosc();
switch ( phase )
{
@@ -242,23 +253,25 @@ static inline u32 cgu_get_pll2_fps(int phase)
return fps;
}
static inline u32 cgu_get_pll2_fdiv(void)
static inline unsigned int
cgu_get_pll2_fdiv(void)
{
register u32 div = CGU_IF_CLK_PCI_CLK + 1;
register unsigned int div = CGU_IF_CLK_PCI_CLK + 1;
return (cgu_get_pll2_fosc() + (div >> 1)) / div;
}
u32 cgu_get_mips_clock(int cpu)
unsigned int
cgu_get_mips_clock(int cpu)
{
register u32 ret = cgu_get_pll0_fosc();
register u32 cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
register unsigned int ret = cgu_get_pll0_fosc();
register unsigned int cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
if ( cpusel == 0 )
if(cpusel == 0)
return ret;
else if ( cpusel == 2 )
else if(cpusel == 2)
ret <<= 1;
switch ( CGU_SYS_DDR_SEL )
switch(CGU_SYS_DDR_SEL)
{
default:
case 0:
@@ -272,16 +285,18 @@ u32 cgu_get_mips_clock(int cpu)
}
}
u32 cgu_get_cpu_clock(void)
unsigned int
cgu_get_cpu_clock(void)
{
return cgu_get_mips_clock(0);
}
u32 cgu_get_io_region_clock(void)
unsigned int
cgu_get_io_region_clock(void)
{
register u32 ret = cgu_get_pll0_fosc();
register unsigned int ret = cgu_get_pll0_fosc();
switch ( CGU_SYS_DDR_SEL )
switch(CGU_SYS_DDR_SEL)
{
default:
case 0:
@@ -295,9 +310,10 @@ u32 cgu_get_io_region_clock(void)
}
}
u32 cgu_get_fpi_bus_clock(int fpi)
unsigned int
cgu_get_fpi_bus_clock(int fpi)
{
register u32 ret = cgu_get_io_region_clock();
register unsigned int ret = cgu_get_io_region_clock();
if((fpi == 2) && (CGU_SYS_FPI_SEL))
ret >>= 1;
@@ -305,9 +321,10 @@ u32 cgu_get_fpi_bus_clock(int fpi)
return ret;
}
u32 cgu_get_pp32_clock(void)
unsigned int
cgu_get_pp32_clock(void)
{
switch ( CGU_SYS_PPESEL )
switch(CGU_SYS_PPESEL)
{
default:
case 0:
@@ -321,9 +338,10 @@ u32 cgu_get_pp32_clock(void)
}
}
u32 cgu_get_ethernet_clock(int mii)
unsigned int
cgu_get_ethernet_clock(int mii)
{
switch ( CGU_IF_CLK_MIISEL )
switch(CGU_IF_CLK_MIISEL)
{
case 0:
return (cgu_get_pll2_fosc() + 3) / 12;
@@ -337,9 +355,10 @@ u32 cgu_get_ethernet_clock(int mii)
return 0;
}
u32 cgu_get_usb_clock(void)
unsigned int
cgu_get_usb_clock(void)
{
switch ( CGU_IF_CLK_USBSEL )
switch(CGU_IF_CLK_USBSEL)
{
case 0:
return (cgu_get_pll2_fosc() + 12) / 25;
@@ -353,15 +372,16 @@ u32 cgu_get_usb_clock(void)
return 0;
}
u32 cgu_get_clockout(int clkout)
unsigned int
cgu_get_clockout(int clkout)
{
u32 fosc1 = cgu_get_pll1_fosc();
u32 fosc2 = cgu_get_pll2_fosc();
unsigned int fosc1 = cgu_get_pll1_fosc();
unsigned int fosc2 = cgu_get_pll2_fosc();
if ( clkout > 3 || clkout < 0 )
if(clkout > 3 || clkout < 0)
return 0;
switch ( ((u32)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2) )
switch(((unsigned int)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2))
{
case 0: /* 32.768KHz */
case 15:
@@ -391,6 +411,5 @@ u32 cgu_get_clockout(int clkout)
case 11:/* 60MHz */
return (fosc2 + 2) / 5;
}
return 0;
}

18
target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
View File

@@ -32,9 +32,9 @@
#define DMA_INT_BUDGET 100 /*budget for interrupt handling */
#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */
extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
extern void enable_ifxmips_irq (unsigned int irq_nr);
extern void disable_ifxmips_irq (unsigned int irq_nr);
extern void ifxmips_mask_and_ack_irq (unsigned int irq_nr);
extern void ifxmips_enable_irq (unsigned int irq_nr);
extern void ifxmips_disable_irq (unsigned int irq_nr);
u64 *g_desc_list;
_dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
@@ -101,7 +101,7 @@ enable_ch_irq (_dma_channel_info *pCh)
ifxmips_w32(0x4a, IFXMIPS_DMA_CIE);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
enable_ifxmips_irq(pCh->irq);
ifxmips_enable_irq(pCh->irq);
}
void
@@ -116,7 +116,7 @@ disable_ch_irq (_dma_channel_info *pCh)
ifxmips_w32(0, IFXMIPS_DMA_CIE);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
mask_and_ack_ifxmips_irq(pCh->irq);
ifxmips_mask_and_ack_irq(pCh->irq);
}
void
@@ -182,7 +182,7 @@ rx_chan_intr_handler (int chan_no)
ifxmips_w32(tmp, IFXMIPS_DMA_CS);
g_ifxmips_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
enable_ifxmips_irq(dma_chan[chan_no].irq);
ifxmips_enable_irq(dma_chan[chan_no].irq);
}
}
@@ -276,7 +276,7 @@ dma_interrupt (int irq, void *dev_id)
ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
g_ifxmips_dma_int_status |= 1 << chan_no;
ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN);
mask_and_ack_ifxmips_irq(irq);
ifxmips_mask_and_ack_irq(irq);
if (!g_ifxmips_dma_in_process)
{
@@ -387,7 +387,7 @@ dma_device_register(_dma_device_info *dev)
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL);
local_irq_restore(flag);
enable_ifxmips_irq(dma_chan[chan_no].irq);
ifxmips_enable_irq(dma_chan[chan_no].irq);
}
}
}
@@ -438,7 +438,7 @@ dma_device_unregister (_dma_device_info *dev)
{
pCh = dev->rx_chan[i];
chan_no = (int)(dev->rx_chan[i] - dma_chan);
disable_ifxmips_irq(pCh->irq);
ifxmips_disable_irq(pCh->irq);
local_irq_save(flag);
g_ifxmips_dma_int_status &= ~(1 << chan_no);

158
target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
View File

@@ -13,9 +13,10 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2004 btxu Generate from INCA-IP project
* Copyright (C) 2005 Jin-Sze.Sow Comments edited
* Copyright (C) 2006 Huang Xiaogang Modification & verification on Danube chip
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/module.h>
@@ -43,10 +44,6 @@
#define MAX_PORTS 2
#define PINS_PER_PORT 16
#define DRVNAME "ifxmips_gpio"
static unsigned int ifxmips_gpio_major = 0;
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
#define IFXMIPS_RST_PIN 15
#define IFXMIPS_RST_PORT 1
@@ -65,58 +62,51 @@ struct event_t {
};
#endif
/* TODO do we need this ? */
static struct semaphore port_sem;
/* TODO do we really need this ? return in a define is forbidden by coding style */
#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
int
ifxmips_port_reserve_pin (unsigned int port, unsigned int pin)
ifxmips_port_reserve_pin(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
}
EXPORT_SYMBOL(ifxmips_port_reserve_pin);
int
ifxmips_port_free_pin (unsigned int port, unsigned int pin)
ifxmips_port_free_pin(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
}
EXPORT_SYMBOL(ifxmips_port_free_pin);
int
ifxmips_port_set_open_drain (unsigned int port, unsigned int pin)
ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_OD + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_open_drain);
int
ifxmips_port_clear_open_drain (unsigned int port, unsigned int pin)
ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_OD + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_open_drain);
int
ifxmips_port_set_pudsel (unsigned int port, unsigned int pin)
ifxmips_port_set_pudsel(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_pudsel);
@@ -125,97 +115,96 @@ int
ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_pudsel);
int
ifxmips_port_set_puden (unsigned int port, unsigned int pin)
ifxmips_port_set_puden(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_puden);
int
ifxmips_port_clear_puden (unsigned int port, unsigned int pin)
ifxmips_port_clear_puden(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_puden);
int
ifxmips_port_set_stoff (unsigned int port, unsigned int pin)
ifxmips_port_set_stoff(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_stoff);
int
ifxmips_port_clear_stoff (unsigned int port, unsigned int pin)
ifxmips_port_clear_stoff(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_stoff);
int
ifxmips_port_set_dir_out (unsigned int port, unsigned int pin)
ifxmips_port_set_dir_out(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_dir_out);
int
ifxmips_port_set_dir_in (unsigned int port, unsigned int pin)
ifxmips_port_set_dir_in(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_dir_in);
int
ifxmips_port_set_output (unsigned int port, unsigned int pin)
ifxmips_port_set_output(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_output);
int
ifxmips_port_clear_output (unsigned int port, unsigned int pin)
ifxmips_port_clear_output(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_output);
int
ifxmips_port_get_input (unsigned int port, unsigned int pin)
ifxmips_port_get_input(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
return 0;
else
@@ -224,54 +213,56 @@ ifxmips_port_get_input (unsigned int port, unsigned int pin)
EXPORT_SYMBOL(ifxmips_port_get_input);
int
ifxmips_port_set_altsel0 (unsigned int port, unsigned int pin)
ifxmips_port_set_altsel0(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_altsel0);
int
ifxmips_port_clear_altsel0 (unsigned int port, unsigned int pin)
ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_altsel0);
int
ifxmips_port_set_altsel1 (unsigned int port, unsigned int pin)
ifxmips_port_set_altsel1(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_altsel1);
int
ifxmips_port_clear_altsel1 (unsigned int port, unsigned int pin)
ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_altsel1);
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
static inline void add_msg(struct sk_buff *skb, char *msg)
static inline void
add_msg(struct sk_buff *skb, char *msg)
{
char *scratch;
scratch = skb_put(skb, strlen(msg) + 1);
sprintf(scratch, msg);
}
static void hotplug_button(struct work_struct *wq)
static void
hotplug_button(struct work_struct *wq)
{
struct sk_buff *skb;
struct event_t *event;
@@ -280,21 +271,17 @@ static void hotplug_button(struct work_struct *wq)
char buf[128];
event = container_of(wq, struct event_t, wq);
if (!uevent_sock)
if(!uevent_sock)
goto done;
/* allocate message with the maximum possible size */
s = event->set ? "pressed" : "released";
len = strlen(s) + 2;
skb = alloc_skb(len + 2048, GFP_KERNEL);
if (!skb)
if(!skb)
goto done;
/* add header */
scratch = skb_put(skb, len);
sprintf(scratch, "%s@",s);
/* copy keys to our continuous event payload buffer */
add_msg(skb, "HOME=/");
add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin");
add_msg(skb, "SUBSYSTEM=button");
@@ -307,12 +294,12 @@ static void hotplug_button(struct work_struct *wq)
NETLINK_CB(skb).dst_group = 1;
netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL);
done:
kfree(event);
}
static void reset_button_poll(unsigned long unused)
static void
reset_button_poll(unsigned long unused)
{
struct event_t *event;
@@ -325,7 +312,7 @@ static void reset_button_poll(unsigned long unused)
pressed = 0;
else
pressed = 1;
printk("button was %s\n", (pressed ? "pressed" : "released"));
printk("reset button was %s\n", (pressed ? "pressed" : "released"));
event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
if (!event)
{
@@ -342,39 +329,30 @@ static void reset_button_poll(unsigned long unused)
#endif
static int
ifxmips_gpio_probe (struct platform_device *dev)
ifxmips_gpio_probe(struct platform_device *dev)
{
int retval = 0;
sema_init (&port_sem, 1);
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
ifxmips_port_set_open_drain(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN);
ifxmips_port_clear_altsel0(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN);
ifxmips_port_clear_altsel1(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN);
ifxmips_port_set_dir_in(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN);
seen = jiffies;
init_timer(&rst_button_timer);
rst_button_timer.function = reset_button_poll;
rst_button_timer.expires = jiffies + HZ;
add_timer(&rst_button_timer);
#endif
printk(KERN_INFO DRVNAME ": device successfully initialized #%d.\n", ifxmips_gpio_major);
return retval;
}
static int
ifxmips_gpio_remove (struct platform_device *pdev)
ifxmips_gpio_remove(struct platform_device *pdev)
{
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
del_timer_sync(&rst_button_timer);
#endif
unregister_chrdev(ifxmips_gpio_major, DRVNAME);
return 0;
}
@@ -383,22 +361,22 @@ platform_driver ifxmips_gpio_driver = {
.probe = ifxmips_gpio_probe,
.remove = ifxmips_gpio_remove,
.driver = {
.name = DRVNAME,
.name = "ifxmips_gpio",
.owner = THIS_MODULE,
},
};
int __init
ifxmips_gpio_init (void)
ifxmips_gpio_init(void)
{
int ret = platform_driver_register(&ifxmips_gpio_driver);
if (ret)
printk(KERN_INFO DRVNAME ": Error registering platfom driver!");
printk(KERN_INFO "ifxmips_gpio : Error registering platfom driver!");
return ret;
}
void __exit
ifxmips_gpio_exit (void)
ifxmips_gpio_exit(void)
{
platform_driver_unregister(&ifxmips_gpio_driver);
}

4
target/linux/ifxmips/files/arch/mips/ifxmips/gptu.c
View File

@@ -817,7 +817,7 @@ ifxmips_gptu_init(void)
}
void __exit
ifxmips_gptu_exit (void)
ifxmips_gptu_exit(void)
{
unsigned int i;
@@ -827,9 +827,7 @@ ifxmips_gptu_exit (void)
disable_irq (timer_dev.timer[i].irq);
free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
}
ifxmips_disable_gptu();
misc_deregister(&gptu_miscdev);
}

113
target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c
View File

@@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/interrupt.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -16,12 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 Wu Qi Ming infineon
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
@@ -37,17 +30,16 @@
#include <asm/ifxmips/ifxmips_irq.h>
#include <asm/irq_cpu.h>
void
disable_ifxmips_irq (unsigned int irq_nr)
ifxmips_disable_irq(unsigned int irq_nr)
{
int i;
u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
for(i = 0; i <= 4; i++)
{
if (irq_nr < INT_NUM_IM_OFFSET){
if(irq_nr < INT_NUM_IM_OFFSET){
ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
return;
}
@@ -55,19 +47,19 @@ disable_ifxmips_irq (unsigned int irq_nr)
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (disable_ifxmips_irq);
EXPORT_SYMBOL(ifxmips_disable_irq);
void
mask_and_ack_ifxmips_irq (unsigned int irq_nr)
ifxmips_mask_and_ack_irq(unsigned int irq_nr)
{
int i;
u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
for(i = 0; i <= 4; i++)
{
if (irq_nr < INT_NUM_IM_OFFSET)
if(irq_nr < INT_NUM_IM_OFFSET)
{
ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
ifxmips_w32((1 << irq_nr ), ifxmips_isr);
@@ -78,18 +70,18 @@ mask_and_ack_ifxmips_irq (unsigned int irq_nr)
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (mask_and_ack_ifxmips_irq);
EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
void
enable_ifxmips_irq (unsigned int irq_nr)
ifxmips_enable_irq(unsigned int irq_nr)
{
int i;
u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
for(i = 0; i <= 4; i++)
{
if (irq_nr < INT_NUM_IM_OFFSET)
if(irq_nr < INT_NUM_IM_OFFSET)
{
ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier);
return;
@@ -98,78 +90,79 @@ enable_ifxmips_irq (unsigned int irq_nr)
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (enable_ifxmips_irq);
EXPORT_SYMBOL(ifxmips_enable_irq);
static unsigned int
startup_ifxmips_irq (unsigned int irq)
ifxmips_startup_irq(unsigned int irq)
{
enable_ifxmips_irq (irq);
ifxmips_enable_irq(irq);
return 0;
}
static void
end_ifxmips_irq (unsigned int irq)
ifxmips_end_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_ifxmips_irq (irq);
if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
ifxmips_enable_irq (irq);
}
static struct hw_interrupt_type ifxmips_irq_type = {
static struct hw_interrupt_type
ifxmips_irq_type = {
"IFXMIPS",
.startup = startup_ifxmips_irq,
.enable = enable_ifxmips_irq,
.disable = disable_ifxmips_irq,
.unmask = enable_ifxmips_irq,
.ack = end_ifxmips_irq,
.mask = disable_ifxmips_irq,
.mask_ack = mask_and_ack_ifxmips_irq,
.end = end_ifxmips_irq,
.startup = ifxmips_startup_irq,
.enable = ifxmips_enable_irq,
.disable = ifxmips_disable_irq,
.unmask = ifxmips_enable_irq,
.ack = ifxmips_end_irq,
.mask = ifxmips_disable_irq,
.mask_ack = ifxmips_mask_and_ack_irq,
.end = ifxmips_end_irq,
};
static inline int
ls1bit32(unsigned long x)
{
__asm__ (
" .set push \n"
" .set mips32 \n"
" clz %0, %1 \n"
" .set pop \n"
".set push \n"
".set mips32 \n"
"clz %0, %1 \n"
".set pop \n"
: "=r" (x)
: "r" (x));
return 31 - x;
return 31 - x;
}
void
ifxmips_hw_irqdispatch (int module)
ifxmips_hw_irqdispatch(int module)
{
u32 irq;
irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
if (irq == 0)
if(irq == 0)
return;
irq = ls1bit32 (irq);
do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
irq = ls1bit32(irq);
do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
if ((irq == 22) && (module == 0)){
if((irq == 22) && (module == 0)){
ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
}
}
asmlinkage void
plat_irq_dispatch (void)
plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
unsigned int i;
if (pending & CAUSEF_IP7){
if(pending & CAUSEF_IP7)
{
do_IRQ(MIPS_CPU_TIMER_IRQ);
goto out;
} else {
for (i = 0; i < 5; i++)
for(i = 0; i < 5; i++)
{
if (pending & (CAUSEF_IP2 << i))
if(pending & (CAUSEF_IP2 << i))
{
ifxmips_hw_irqdispatch(i);
goto out;
@@ -182,7 +175,8 @@ out:
return;
}
static struct irqaction cascade = {
static struct irqaction
cascade = {
.handler = no_action,
.flags = IRQF_DISABLED,
.name = "cascade",
@@ -193,27 +187,16 @@ arch_init_irq(void)
{
int i;
for (i = 0; i < 5; i++)
{
for(i = 0; i < 5; i++)
ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
}
mips_cpu_irq_init();
for (i = 2; i <= 6; i++)
{
for(i = 2; i <= 6; i++)
setup_irq(i, &cascade);
}
for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
{
#if 0
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
#endif
for(i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
set_irq_chip_and_handler(i, &ifxmips_irq_type, handle_level_irq);
}
set_c0_status (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
}

7
target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
View File

@@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/pmu.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -16,7 +14,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/kernel.h>
@@ -25,7 +22,7 @@
#include <asm/ifxmips/ifxmips.h>
void
ifxmips_pmu_enable (unsigned int module)
ifxmips_pmu_enable(unsigned int module)
{
int err = 1000000;
@@ -38,7 +35,7 @@ ifxmips_pmu_enable (unsigned int module)
EXPORT_SYMBOL(ifxmips_pmu_enable);
void
ifxmips_pmu_disable (unsigned int module)
ifxmips_pmu_disable(unsigned int module)
{
ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
}

26
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
View File

@@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/prom.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -16,12 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 Wu Qi Ming infineon
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
@@ -29,10 +22,9 @@
#include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h>
static char buf[1024];
u32 *prom_cp1_base = NULL;
u32 prom_cp1_size = 0;
unsigned int *prom_cp1_base = NULL;
unsigned int prom_cp1_size = 0;
void
prom_free_prom_memory(void)
@@ -62,17 +54,15 @@ prom_printf(const char * fmt, ...)
buf_end = buf + l;
for(p = buf; p < buf_end; p++)
{
prom_putchar(*p);
}
}
u32 *prom_get_cp1_base(void)
unsigned int *prom_get_cp1_base(void)
{
return prom_cp1_base;
}
u32 prom_get_cp1_size(void)
unsigned int prom_get_cp1_size(void)
{
return prom_cp1_size;
}
@@ -117,13 +107,15 @@ prom_init(void)
prom_cp1_size = 2;
memsize -= prom_cp1_size;
prom_cp1_base = (u32*)(0xA0000000 + (memsize * 1024 * 1024));
prom_cp1_base = (unsigned int*)(0xA0000000 + (memsize * 1024 * 1024));
prom_printf(KERN_INFO "Using %dMB Ram and reserving %dMB for cp1\n", memsize, prom_cp1_size);
prom_printf(KERN_INFO "Using %dMB Ram and reserving %dMB for cp1\n",
memsize, prom_cp1_size);
memsize *= 1024 * 1024;
if(!*arcs_cmdline)
strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
strcpy(&(arcs_cmdline[0]),
"console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
}

8
target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
View File

@@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/prom.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -15,13 +13,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/kernel.h>

53
target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
View File

@@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/setup.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -16,12 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2004 peng.liu@infineon.com
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
@@ -30,26 +23,21 @@
#include <asm/traps.h>
#include <asm/cpu.h>
#include <asm/irq.h>
#include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_irq.h>
#include <asm/ifxmips/ifxmips_pmu.h>
#include <asm/ifxmips/ifxmips_prom.h>
static unsigned int r4k_offset; /* Amount to increment compare reg each time */
static unsigned int r4k_cur; /* What counter should be at next timer irq */
static unsigned int r4k_offset;
static unsigned int r4k_cur;
extern void ifxmips_reboot_setup (void);
void prom_printf (const char * fmt, ...);
void
__init bus_error_init (void)
{
/* nothing yet */
}
extern void ifxmips_reboot_setup(void);
unsigned int
ifxmips_get_ddr_hz (void)
ifxmips_get_ddr_hz(void)
{
switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
{
case 0:
return CLOCK_167M;
@@ -63,10 +51,10 @@ ifxmips_get_ddr_hz (void)
EXPORT_SYMBOL(ifxmips_get_ddr_hz);
unsigned int
ifxmips_get_cpu_hz (void)
ifxmips_get_cpu_hz(void)
{
unsigned int ddr_clock = ifxmips_get_ddr_hz();
switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
{
case 0:
return CLOCK_333M;
@@ -78,25 +66,24 @@ ifxmips_get_cpu_hz (void)
EXPORT_SYMBOL(ifxmips_get_cpu_hz);
unsigned int
ifxmips_get_fpi_hz (void)
ifxmips_get_fpi_hz(void)
{
unsigned int ddr_clock = ifxmips_get_ddr_hz();
if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
{
if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
return ddr_clock >> 1;
}
return ddr_clock;
}
EXPORT_SYMBOL(ifxmips_get_fpi_hz);
unsigned int
ifxmips_get_cpu_ver (void)
ifxmips_get_cpu_ver(void)
{
return ifxmips_r32(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
}
EXPORT_SYMBOL(ifxmips_get_cpu_ver);
static __inline__ u32 get_counter_resolution(void)
static __inline__ u32
ifxmips_get_counter_resolution(void)
{
u32 res;
__asm__ __volatile__(
@@ -123,9 +110,9 @@ ifxmips_be_handler(struct pt_regs *regs, int is_fixup)
}
void __init
plat_time_init (void)
plat_time_init(void)
{
mips_hpt_frequency = ifxmips_get_cpu_hz()/get_counter_resolution();
mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution();
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
@@ -136,23 +123,17 @@ plat_time_init (void)
ifxmips_w32(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
}
extern const char* get_system_type (void);
//void (*board_time_init)(void);
void __init
plat_mem_setup (void)
plat_mem_setup(void)
{
u32 status;
prom_printf("This %s has a cpu rev of 0x%X\n", get_system_type(), ifxmips_get_cpu_ver());
//TODO WHY ???
/* clear RE bit*/
status = read_c0_status();
status &= (~(1<<25));
write_c0_status(status);
ifxmips_reboot_setup();
// board_time_init = ifxmips_time_init;
board_be_handler = &ifxmips_be_handler;
ioport_resource.start = IOPORT_RESOURCE_START;