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lots of code cleanup for ifxmips

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11570 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2008-06-23 20:31:34 +00:00
parent 9f4462d801
commit 43ba67e0d5
17 changed files with 375 additions and 468 deletions
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53
target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
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@@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/setup.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -16,12 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2004 peng.liu@infineon.com
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
@@ -30,26 +23,21 @@
#include <asm/traps.h>
#include <asm/cpu.h>
#include <asm/irq.h>
#include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_irq.h>
#include <asm/ifxmips/ifxmips_pmu.h>
#include <asm/ifxmips/ifxmips_prom.h>
static unsigned int r4k_offset; /* Amount to increment compare reg each time */
static unsigned int r4k_cur; /* What counter should be at next timer irq */
static unsigned int r4k_offset;
static unsigned int r4k_cur;
extern void ifxmips_reboot_setup (void);
void prom_printf (const char * fmt, ...);
void
__init bus_error_init (void)
{
/* nothing yet */
}
extern void ifxmips_reboot_setup(void);
unsigned int
ifxmips_get_ddr_hz (void)
ifxmips_get_ddr_hz(void)
{
switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
{
case 0:
return CLOCK_167M;
@@ -63,10 +51,10 @@ ifxmips_get_ddr_hz (void)
EXPORT_SYMBOL(ifxmips_get_ddr_hz);
unsigned int
ifxmips_get_cpu_hz (void)
ifxmips_get_cpu_hz(void)
{
unsigned int ddr_clock = ifxmips_get_ddr_hz();
switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
{
case 0:
return CLOCK_333M;
@@ -78,25 +66,24 @@ ifxmips_get_cpu_hz (void)
EXPORT_SYMBOL(ifxmips_get_cpu_hz);
unsigned int
ifxmips_get_fpi_hz (void)
ifxmips_get_fpi_hz(void)
{
unsigned int ddr_clock = ifxmips_get_ddr_hz();
if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
{
if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
return ddr_clock >> 1;
}
return ddr_clock;
}
EXPORT_SYMBOL(ifxmips_get_fpi_hz);
unsigned int
ifxmips_get_cpu_ver (void)
ifxmips_get_cpu_ver(void)
{
return ifxmips_r32(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
}
EXPORT_SYMBOL(ifxmips_get_cpu_ver);
static __inline__ u32 get_counter_resolution(void)
static __inline__ u32
ifxmips_get_counter_resolution(void)
{
u32 res;
__asm__ __volatile__(
@@ -123,9 +110,9 @@ ifxmips_be_handler(struct pt_regs *regs, int is_fixup)
}
void __init
plat_time_init (void)
plat_time_init(void)
{
mips_hpt_frequency = ifxmips_get_cpu_hz()/get_counter_resolution();
mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution();
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
@@ -136,23 +123,17 @@ plat_time_init (void)
ifxmips_w32(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
}
extern const char* get_system_type (void);
//void (*board_time_init)(void);
void __init
plat_mem_setup (void)
plat_mem_setup(void)
{
u32 status;
prom_printf("This %s has a cpu rev of 0x%X\n", get_system_type(), ifxmips_get_cpu_ver());
//TODO WHY ???
/* clear RE bit*/
status = read_c0_status();
status &= (~(1<<25));
write_c0_status(status);
ifxmips_reboot_setup();
// board_time_init = ifxmips_time_init;
board_be_handler = &ifxmips_be_handler;
ioport_resource.start = IOPORT_RESOURCE_START;