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ath9k: use the maximum rate power for the channel txpower limits
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23543 3c298f89-4303-0410-b956-a3cf2f4a3e73
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0457e48f9d
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@ -21,16 +21,28 @@
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{
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
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@@ -768,6 +768,9 @@ static void ath9k_hw_4k_set_txpower(stru
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@@ -751,15 +751,20 @@ static void ath9k_hw_4k_set_txpower(stru
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regulatory->max_power_level = ratesArray[i];
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ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
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+ regulatory->max_power_level = 0;
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for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
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ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
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if (ratesArray[i] > AR5416_MAX_RATE_POWER)
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ratesArray[i] = AR5416_MAX_RATE_POWER;
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+
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+ if (ratesArray[i] > regulatory->max_power_level)
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+ regulatory->max_power_level = ratesArray[i];
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}
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+ if (test)
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+ return;
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+
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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for (i = 0; i < Ar5416RateSize; i++)
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ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
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/* Update regulatory */
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-
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i = rate6mb;
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if (IS_CHAN_HT40(chan))
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i = rateHt40_0;
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--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
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+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
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@@ -853,7 +853,7 @@ static void ath9k_hw_ar9287_set_txpower(
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@ -42,24 +54,34 @@
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{
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
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@@ -883,6 +883,16 @@ static void ath9k_hw_ar9287_set_txpower(
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@@ -877,12 +877,26 @@ static void ath9k_hw_ar9287_set_txpower(
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ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
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+ regulatory->max_power_level = 0;
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for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
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ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
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if (ratesArray[i] > AR9287_MAX_RATE_POWER)
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ratesArray[i] = AR9287_MAX_RATE_POWER;
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+
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+ if (ratesArray[i] > regulatory->max_power_level)
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+ regulatory->max_power_level = ratesArray[i];
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}
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+ if (test)
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+ return;
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+
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+ if (IS_CHAN_2GHZ(chan))
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+ i = rate1l;
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+ else
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+ i = rate6mb;
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+
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+ regulatory->max_power_level = ratesArray[i];
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+
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+ if (test)
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+ return;
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+
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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for (i = 0; i < Ar5416RateSize; i++)
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ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
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@@ -971,17 +981,6 @@ static void ath9k_hw_ar9287_set_txpower(
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@@ -971,17 +985,6 @@ static void ath9k_hw_ar9287_set_txpower(
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| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
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| ATH9K_POW_SM(ratesArray[rateDupCck], 0));
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}
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@ -88,18 +110,29 @@
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{
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#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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@@ -1291,6 +1291,33 @@ static void ath9k_hw_def_set_txpower(str
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@@ -1285,12 +1285,44 @@ static void ath9k_hw_def_set_txpower(str
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ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
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+ regulatory->max_power_level = 0;
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for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
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ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
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if (ratesArray[i] > AR5416_MAX_RATE_POWER)
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ratesArray[i] = AR5416_MAX_RATE_POWER;
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+ if (ratesArray[i] > regulatory->max_power_level)
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+ regulatory->max_power_level = ratesArray[i];
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}
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+ i = rate6mb;
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+ if (!test) {
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+ i = rate6mb;
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+
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+ if (IS_CHAN_HT40(chan))
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+ i = rateHt40_0;
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+ else if (IS_CHAN_HT20(chan))
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+ i = rateHt20_0;
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+ if (IS_CHAN_HT40(chan))
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+ i = rateHt40_0;
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+ else if (IS_CHAN_HT20(chan))
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+ i = rateHt20_0;
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+
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+ regulatory->max_power_level = ratesArray[i];
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+ regulatory->max_power_level = ratesArray[i];
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+ }
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+
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+ switch(ar5416_get_ntxchains(ah->txchainmask)) {
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+ case 1:
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@ -122,7 +155,7 @@
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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for (i = 0; i < Ar5416RateSize; i++) {
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int8_t pwr_table_offset;
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@@ -1387,34 +1414,6 @@ static void ath9k_hw_def_set_txpower(str
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@@ -1387,34 +1419,6 @@ static void ath9k_hw_def_set_txpower(str
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REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
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ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
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| ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
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@ -168,7 +201,25 @@
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{
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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struct ath_common *common = ath9k_hw_common(ah);
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@@ -2160,9 +2160,6 @@ static void ath9k_hw_ar9300_set_txpower(
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@@ -2145,7 +2145,16 @@ static void ath9k_hw_ar9300_set_txpower(
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twiceMaxRegulatoryPower,
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powerLimit);
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- while (i < ar9300RateSize) {
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+ regulatory->max_power_level = 0;
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+ for (i = 0; i < ar9300RateSize; i++) {
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+ if (targetPowerValT2[i] > regulatory->max_power_level)
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+ regulatory->max_power_level = targetPowerValT2[i];
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+ }
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+
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+ if (test)
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+ return;
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+
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+ for (i = 0; i < ar9300RateSize; i++) {
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ath_print(common, ATH_DBG_EEPROM,
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"TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
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i++;
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@@ -2160,9 +2169,6 @@ static void ath9k_hw_ar9300_set_txpower(
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i++;
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}
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@ -178,16 +229,13 @@
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/*
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* This is the TX power we send back to driver core,
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* and it can use to pass to userspace to display our
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@@ -2181,8 +2178,13 @@ static void ath9k_hw_ar9300_set_txpower(
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@@ -2181,8 +2187,10 @@ static void ath9k_hw_ar9300_set_txpower(
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i = ALL_TARGET_HT20_0_8_16; /* ht20 */
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ah->txpower_limit = targetPowerValT2[i];
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- regulatory->max_power_level = ratesArray[i];
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+ regulatory->max_power_level = targetPowerValT2[i];
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+ if (test)
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+ return;
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+
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+ /* Write target power array to registers */
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+ ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
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ar9003_hw_calibration_apply(ah, chan->channel);
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