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[s3c24xx] Add ioctls to glamo framebuffer driver to enable/disable glamo

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engines.


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16686 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
lars
2009-07-05 12:05:20 +00:00
parent 1f6241ad90
commit 465f0ffdb5
7 changed files with 132 additions and 44 deletions
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54
target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-core.c
View File

@@ -536,6 +536,9 @@ int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
__reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
GLAMO_HOSTBUS2_MMIO_EN_2D,
GLAMO_HOSTBUS2_MMIO_EN_2D);
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
0xffff);
break;
case GLAMO_ENGINE_CMDQ:
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
@@ -543,10 +546,13 @@ int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
__reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
GLAMO_HOSTBUS2_MMIO_EN_CQ,
GLAMO_HOSTBUS2_MMIO_EN_CQ);
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
0xffff);
break;
/* FIXME: Implementation */
default:
break;
return -EINVAL;
}
glamo->engine_enabled_bitfield |= 1 << engine;
@@ -589,17 +595,42 @@ int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
break;
case GLAMO_ENGINE_MMC:
// __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
// GLAMO_CLOCK_MMC_EN_M9CLK |
// GLAMO_CLOCK_MMC_EN_TCLK |
// GLAMO_CLOCK_MMC_DG_M9CLK |
// GLAMO_CLOCK_MMC_DG_TCLK, 0);
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
GLAMO_CLOCK_MMC_EN_M9CLK |
GLAMO_CLOCK_MMC_EN_TCLK |
GLAMO_CLOCK_MMC_DG_M9CLK |
GLAMO_CLOCK_MMC_DG_TCLK, 0);
/* disable the TCLK divider clk input */
// __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
// GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
default:
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
break;
case GLAMO_ENGINE_CMDQ:
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
GLAMO_CLOCK_2D_EN_M6CLK,
0);
__reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
GLAMO_HOSTBUS2_MMIO_EN_CQ,
GLAMO_HOSTBUS2_MMIO_EN_CQ);
/* __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
0);*/
break;
case GLAMO_ENGINE_2D:
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
GLAMO_CLOCK_2D_EN_M7CLK |
GLAMO_CLOCK_2D_EN_GCLK |
GLAMO_CLOCK_2D_DG_M7CLK |
GLAMO_CLOCK_2D_DG_GCLK,
0);
__reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
GLAMO_HOSTBUS2_MMIO_EN_2D,
GLAMO_HOSTBUS2_MMIO_EN_2D);
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
0);
break;
default:
return -EINVAL;
}
glamo->engine_enabled_bitfield &= ~(1 << engine);
@@ -667,6 +698,9 @@ struct glamo_script reset_regs[] = {
[GLAMO_ENGINE_MMC] = {
GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
},
[GLAMO_ENGINE_CMDQ] = {
GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
},
[GLAMO_ENGINE_2D] = {
GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
},

24
target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-core.h
View File

@@ -2,6 +2,7 @@
#define __GLAMO_CORE_H
#include <asm/system.h>
#include <linux/glamo-engine.h>
/* for the time being, we put the on-screen framebuffer into the lowest
* VRAM space. This should make the code easily compatible with the various
@@ -40,29 +41,6 @@ struct glamo_script {
int glamo_run_script(struct glamo_core *glamo,
struct glamo_script *script, int len, int may_sleep);
enum glamo_engine {
GLAMO_ENGINE_CAPTURE,
GLAMO_ENGINE_ISP,
GLAMO_ENGINE_JPEG,
GLAMO_ENGINE_MPEG_ENC,
GLAMO_ENGINE_MPEG_DEC,
GLAMO_ENGINE_LCD,
GLAMO_ENGINE_CMDQ,
GLAMO_ENGINE_2D,
GLAMO_ENGINE_3D,
GLAMO_ENGINE_MMC,
GLAMO_ENGINE_MICROP0,
GLAMO_ENGINE_RISC,
GLAMO_ENGINE_MICROP1_MPEG_ENC,
GLAMO_ENGINE_MICROP1_MPEG_DEC,
#if 0
GLAMO_ENGINE_H264_DEC,
GLAMO_ENGINE_RISC1,
GLAMO_ENGINE_SPI,
#endif
__NUM_GLAMO_ENGINES
};
struct glamo_mci_pdata {
struct glamo_core * pglamo;
unsigned int gpio_detect;

26
target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-fb.c
View File

@@ -535,6 +535,31 @@ static int glamofb_setcolreg(unsigned regno,
return 0;
}
static int glamofb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg) {
struct glamofb_handle *gfb = (struct glamofb_handle*)info->par;
struct glamo_core *gcore = gfb->mach_info->glamo;
int retval = -ENOTTY;
switch (cmd) {
case GLAMOFB_ENGINE_ENABLE:
retval = glamo_engine_enable(gcore, arg);
break;
case GLAMOFB_ENGINE_DISABLE:
retval = glamo_engine_disable(gcore, arg);
break;
case GLAMOFB_ENGINE_RESET:
glamo_engine_reset(gcore, arg);
retval = 0;
break;
default:
break;
}
return retval;
}
#ifdef CONFIG_MFD_GLAMO_HWACCEL
static inline void glamofb_vsync_wait(struct glamofb_handle *glamo,
int line, int size, int range)
@@ -770,6 +795,7 @@ static struct fb_ops glamofb_ops = {
.fb_set_par = glamofb_set_par,
.fb_blank = glamofb_blank,
.fb_setcolreg = glamofb_setcolreg,
.fb_ioctl = glamofb_ioctl,
#ifdef CONFIG_MFD_GLAMO_HWACCEL
.fb_cursor = glamofb_cursor,
#endif

40
target/linux/s3c24xx/files-2.6.30/include/linux/glamofb.h
View File

@@ -1,40 +0,0 @@
#ifndef _LINUX_GLAMOFB_H
#define _LINUX_GLAMOFB_H
#include <linux/spi/glamo.h>
#include <linux/fb.h>
struct glamo_core;
struct glamofb_platform_data {
int width, height;
int fb_mem_size;
int num_modes;
struct fb_videomode *modes;
struct glamo_spi_info *spi_info;
struct glamo_spigpio_info *spigpio_info;
struct glamo_core *glamo;
struct platform_device *mmc_dev;
/* glamo mmc platform specific info */
int (*glamo_can_set_mci_power)(void);
/* glamo-mci asking if it should use the slow clock to card */
int (*glamo_mci_use_slow)(void);
int (*glamo_irq_is_wired)(void);
void (*glamo_external_reset)(int);
};
int glamofb_cmd_mode(struct glamofb_handle *gfb, int on);
int glamofb_cmd_write(struct glamofb_handle *gfb, u_int16_t val);
#ifdef CONFIG_MFD_GLAMO
void glamo_lcm_reset(int level);
#else
#define glamo_lcm_reset(...) do {} while (0)
#endif
#endif

10
target/linux/s3c24xx/patches-2.6.30/053-glamo.patch
View File

@@ -19,13 +19,3 @@
obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -124,6 +124,7 @@ struct dentry;
#define FB_ACCEL_TRIDENT_BLADE3D 52 /* Trident Blade3D */
#define FB_ACCEL_TRIDENT_BLADEXP 53 /* Trident BladeXP */
#define FB_ACCEL_CIRRUS_ALPINE 53 /* Cirrus Logic 543x/544x/5480 */
+#define FB_ACCEL_GLAMO 50 /* SMedia Glamo */
#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */