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[brcm63xx] fix SPI message control handling for BCM6338/6348

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BCM6338 and BCM6338 have their MSG_CONTROL register width of 8-bits instead of
16-bits. We were previously using a 16-bits write which corrupted the first
byte of the TX FIFO. Also the message type was always set to Full-duplex even
in the case of half-duplex messages.

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32409 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
2012-06-17 16:17:29 +00:00
parent e200a200fa
commit 4666e9b56d
5 changed files with 133 additions and 5 deletions
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2
target/linux/brcm63xx/patches-3.3/103-MIPS-BCM63XX-add-TRNG-peripheral-definitions.patch
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@@ -85,7 +85,7 @@ Signed-off-by: Florian Fainelli <florian@openwrt.org>
static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1092,4 +1092,18 @@
@@ -1099,4 +1099,18 @@
#define SPI_SSOFFTIME_SHIFT 3
#define SPI_BYTE_SWAP 0x80